Garbage collection method and control device for solid state disk

Abstract

Disclosed are a garbage collection method and control device for a solid state disk, the control device comprising: a processor for initiating a garbage collection comparison request, receiving a comparison result between a forward mapping table and a reverse mapping table output from an accelerator, and obtaining valid data in a storage medium according to the comparison result, and rewriting the valid data in the storage medium, the accelerator is connected with the processor and used for sequentially comparing the multiple mapping relations between the forward mapping table and the reverse mapping table according to a garbage collection comparison request initiated by the processor and returning a comparison result to the processor, and the processor releases hardware resources for a new system task after initiating the garbage collection request. According to the garbage collection method for the solid state disk and the control device, the accelerator is additionally arranged in the control device of the solid state disk, the task of comparing P2L and L2P is completed through the accelerator, garbage collection is completed through a method of combining firmware with hardware, and the garbage collection speed is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state hard disks, and in particular to a garbage collection method and a control device for solid state hard disks. Background Art

[0002] Garbage collection is an important part of the solid state disk (SSD) firmware design and is also the main factor affecting the steady-state performance of the SSD. Therefore, the processing efficiency of garbage collection is a key aspect that needs to be optimized in the SSD firmware.

[0003] The granular characteristics of flash memory (NAND) are: the physical block (Block) must be erased before data can be written. If there are some valid data pages (physical pages storing user data) in a physical block before erasing, in order not to lose user data, the data in the valid data page must be read out and written to another physical block before the physical block can be erased. This is garbage collection.

[0004] In order to read out valid data, the SSD needs to compare the forward mapping table (L2P, logical address to physical address) and the reverse mapping table (P2L, physical address to logical address) one by one. When there are simultaneous matches between the two, it means that valid data has been obtained. However, most of the current software is used to compare P2L and L2P to achieve garbage collection, which will occupy a lot of CPU resources. Summary of the invention

[0005] In view of the above problems, the purpose of the present invention is to provide a garbage collection method and control device for a solid-state hard disk, by adding a hardware accelerator in the solid-state hard disk, using the accelerator to complete the task of comparing P2L and L2P, thereby completing garbage collection through a firmware combined with hardware method to improve the garbage collection speed.

[0006] According to one aspect of the present invention, a control device for a solid-state hard disk is provided, wherein the control device comprises: a processor, configured to initiate a garbage collection comparison request, receive a comparison result between a forward mapping table and a reverse mapping table outputted from an accelerator, obtain valid data in a storage medium according to the comparison result, and rewrite the valid data in the storage medium; and the accelerator, connected to the processor, configured to sequentially compare a plurality of mapping relationships between the forward mapping table and the reverse mapping table according to the garbage collection comparison request initiated by the processor, and return the comparison result to the processor ， The processor releases hardware resources for new system tasks after initiating a garbage collection request.

[0007] Optionally, the accelerator includes: a comparator connected to the processor via an input queue, for receiving a reverse mapping table input from the input queue, and comparing multiple mapping relationships at the same time; a multi-way selection module connected to the comparator, for selecting valid data addresses whose comparison results are matches and outputting them to the processor, and outputting the number of valid data whose comparison results are matches to a buffer; a buffer connected to the multi-way selection module, for outputting the number of valid data to the processor after the comparator completes the comparison of the reverse mapping table; a second storage unit connected to the comparator, for storing a forward mapping table for comparison.

[0008] Optionally, the control device also includes a cache unit; the cache unit includes a first storage unit, which is respectively connected to the processor and the accelerator, and is used to cache the valid data address output from the accelerator and transmit it to the processor; the processor obtains the valid data from the storage medium according to the number of valid data and the valid data address.

[0009] Optionally, whenever the multiplexer receives a valid data address whose comparison result is a match, the multiplexer transmits the received valid data address to the first storage unit.

[0010] Optionally, the comparator includes a plurality of comparison units, the plurality of comparison units sequentially receive different reverse mapping relationships, and the plurality of comparison units simultaneously perform comparison operations on the received reverse mapping relationships and a plurality of forward mapping relationships in the forward mapping table.

[0011] Optionally, the plurality of comparison units are further used to output comparison results to the multiplexer when a corresponding forward mapping relationship and a reverse mapping relationship are matched or when no match is found after the comparison operation is performed; the multiplexer is further used to output unmatched comparison results to the buffer.

[0012] Optionally, the accelerator also includes: a collection control module, connected to the buffer and connected to the processor via an output queue; the collection control module is used to receive the number of valid data and the unmatched comparison results and output them to the processor in a comparison response that conforms to the output queue format.

[0013] Optionally, the accelerator is an application specific integrated circuit ASIC.

[0014] According to another aspect of the present invention, there is provided a garbage collection method for a solid-state hard disk, comprising: a processor initiating a garbage collection comparison request; an accelerator receiving the garbage collection comparison request and comparing a plurality of mapping relationships between a forward mapping table and a reverse mapping table in sequence, and returning a comparison result to the processor; the processor checking the comparison result of the accelerator, obtaining valid data in the storage medium according to the comparison result, and rewriting the valid data in the storage medium; wherein, after initiating the garbage collection request, the processor releases hardware resources for new system tasks.

[0015] Optionally, the step of the accelerator comparing multiple mapping relationships in the forward mapping table and the reverse mapping table in sequence includes: multiple comparison units in the accelerator obtain a reverse mapping relationship in the reverse mapping table in sequence; multiple comparison units simultaneously perform comparison with multiple forward mapping relationships in the forward mapping table; determine whether the traversal comparison of the reverse mapping table is completed; if the traversal is not completed, multiple comparison units repeat the step of obtaining reverse mapping relationships in sequence until the traversal is completed.

[0016] Optionally, the step of the multiple comparison units simultaneously performing comparison with multiple forward mapping relationships in the forward mapping table includes: the multiple comparison units respectively compare an acquired reverse mapping relationship with the multiple forward mapping relationships at the same time to determine whether the reverse mapping relationship and the forward mapping relationship correspond to each other; if they correspond, the physical address in the reverse mapping relationship is used as the physical allocation unit address corresponding to the valid data.

[0017] Optionally, the comparison result between the forward mapping table and the reverse mapping table includes: unmatched comparison results, the number of valid data and the address of valid data.

[0018] Optionally, the method further includes: updating the forward mapping table and the reverse mapping table according to a rewriting operation of valid data of the storage medium.

[0019] The garbage collection method and control device for a solid-state hard disk provided by the present invention adds an accelerator to the solid-state hard disk and uses the accelerator to complete the task of comparing P2L and L2P, thereby accelerating the completion of garbage collection through a method of combining firmware with hardware to improve the garbage collection speed. Furthermore, after the processor submits a garbage collection request to the accelerator, the hardware resources of the processor are released, so that the processor can process other tasks or do the next garbage collection task, thereby achieving the overall acceleration purpose. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram of the structure of a solid state hard disk according to the prior art is shown;

[0022] Figure 2a shows the change of physical blocks in garbage collection according to the prior art;

[0023] Figure 2b A schematic diagram of an L2P table and a P2L table in garbage collection according to the prior art is shown;

[0024] Figure 3 A schematic diagram of the structure of a solid state hard disk according to an embodiment of the present invention is shown;

[0025] Figure 4 A flowchart of garbage collection according to an embodiment of the present invention is shown;

[0026] Figure 5 A flowchart showing the interaction between software and hardware in garbage collection according to an embodiment of the present invention is shown;

[0027] Figure 6 A schematic diagram of the structure of garbage collection according to an embodiment of the present invention is shown;

[0028] Figure 7 A schematic diagram showing a comparison between an L2P table and a P2L table in garbage collection according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0029] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0030] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0031] Figure 1 A schematic diagram of the structure of a solid state hard disk according to the prior art is shown; Figure 2a shows the change of physical blocks in garbage collection according to the prior art; Figure 2b A schematic diagram of an L2P table and a P2L table in garbage collection according to the prior art is shown.

[0032] refer to Figure 1 , a conventional solid state drive 200 includes: a control device 210 and a storage medium 220. In this embodiment, the control device 210 is connected to the host 100, for example, to exchange read and write data with the host 100, and the storage medium 220 is, for example, a NAND flash memory chip array. Specifically, the control device 210 is used to store the read and write data of the host 100 into the storage medium 220. In addition, the control device 210 is also used to execute a garbage collection method, for example.

[0033] In the solid state drive 200, the control device 210 includes a host interface 211, a processor 212, a cache unit 213, and a medium interface 214. The host interface 211 of the control device 210 is connected to the host 100 to transmit read and write data and read and write instructions. The processor 212 is connected to the host interface 211, the cache unit 213, and the storage medium 220. The processor 212 is used to control the transmission and storage of data, and to execute a garbage collection method. The cache unit 213 is, for example, an SRAM, which is used to store a first-level mapping table or index table corresponding to the read and write data. Further, the processor 212 is also used to implement the core software layer of memory control, namely FTL (flash Translation Layer), so that the operating system and the file system can access the memory like accessing a hard disk. The FTL also has the characteristics of supporting bad block management, wear leveling, garbage collection, power failure recovery, write balancing technology, etc. The medium interface 214 is connected to the processor 212 to control the read and write data written to the storage medium 220.

[0034] Among them, FTL is the core software of the firmware. Firmware refers to the software program embedded in the SSD controller, which is responsible for managing and controlling various operations and functions of the SSD. The firmware includes the controller driver, the management algorithm of the solid-state memory, the data transmission protocol, the error detection and correction mechanism, etc. It is responsible for converting the instructions issued by the host into the internal operations of the SSD, and is responsible for managing operations such as data reading, writing, erasing and garbage collection.

[0035] The storage medium 220 includes a flash memory chip array, including multiple physical blocks for storing write data, mapping tables or index tables. The physical blocks storing write data are, for example, user physical blocks, and the physical blocks storing mapping tables are, for example, mapping physical blocks. The control device 210 is also used to store the secondary mapping table in the physical blocks (mapping physical blocks) of the storage medium 220 to prevent data loss and facilitate the recovery and extraction of mapping table data. The physical blocks can be used not only to store write data and mapping tables, but also to store index values ​​corresponding to the write data to establish an index table.

[0036] Furthermore, due to the particle characteristics of flash memory NAND: the physical block (B1ock) must be erased before data can be written. If there are some valid data pages (physical pages storing user data) in a physical block before erasing, in order not to lose user data, the data in the valid data page must be read out and written to another physical block before erasing the physical block. This is garbage collection. The garbage collection process can be divided into three steps:

[0037] 1. Select the source physical block (usually the physical block with the least valid data pages) and find the valid data pages;

[0038] 2. Write the valid data page to the new physical block;

[0039] 3. Clear the source physical block.

[0040] refer to Figure 2a , there are some valid data pages in physical blocks (B1ock) 0, 1, and 2 (i.e., the Valid physical pages shown in the figure), so the valid data pages must be read out and written to the new physical block N, and then the invalid data physical pages in physical blocks 0, 1, and 2 (i.e., the invalid physical pages shown in the figure) are erased, so that physical blocks 0, 1, and 2 become writable physical blocks (the physical pages contained are all writable blank pages None), and the garbage collection process is completed.

[0041] The firmware in the SSD needs to maintain the mapping information of the logical page (LPA, assuming the size is 16KB) to the physical page (PPA, assuming the size is 16KB). Among them, the complete mapping information of the logical page to the physical page can be called a mapping table (L2P table), and the L2P table uses the logical page information as the index value: in the garbage collection process, after the data in the valid data page is migrated, the corresponding mapping table of the logical page information to the physical page information (i.e., the L2P table) also needs to be updated synchronously. In addition, in the SSD, each user data physical block has a mapping table of physical page information to logical page information (i.e., P2L table). The P2L table is established and updated in the Random Access Memory (RAM) when the user data physical block is writing data. The P2L table uses the physical page information as the index value and records the logical page information corresponding to each physical page information in the user data physical block.

[0042] Figure 2b is a schematic diagram of the L2P table and the P2L table; Figure 2bAs shown in the example, when logical page 0 is written for the first time, it is written to physical page 0 of physical block 1, so the information in the L2P table is L0 mapped to P0, and the information in the P2L table is P0 mapped to L0. Not long after that, the host rewrites logical page 0 again. At this time, the SSD writes the data of logical page 0 to physical page 2 of physical block 1, so the L2P table information is updated to L0 mapped to P2, and the P2L table information is P2 mapped to L0. Obviously, the data in physical page 0 of physical block 1 is invalid at this time, and the data in physical page 2 is valid. When the user data physical block 1 is written, the corresponding P2L table has also been updated, and the P2L table is written to physical page 0 of physical block 0 of the mapping table. The firmware needs to remember the mapping relationship between user data physical block 1 and physical page 0 in physical block 0 of the mapping table for subsequent reading, that is, the firmware needs to maintain the physical location information of the P2L table written to the NAND. Among them, P2L is located in a fixed position (mapping table physical block) in NAND, and needs to be read from a fixed position when comparison is required.

[0043] In the aforementioned garbage collection method, in order to read out valid data, the solid-state drive needs to compare the forward mapping table (L2P, logical address to physical address) and the reverse mapping table (P2L, physical address to logical address) one by one. When there are simultaneous matching items between the two, it means that valid data has been obtained. However, currently, the purpose of garbage collection is often achieved by using the CPU to use software to compare P2L and L2P to reduce the amount of writing, and the software acceleration capability is limited and will occupy a large amount of CPU resources.

[0044] Figure 3 FIG. 2 shows a structural diagram of a solid state hard disk according to an embodiment of the present invention. Figure 3 As shown, the solid state drive 200 includes a control device 210 and a storage medium 220 .

[0045] The control device 210 includes a host interface 211, a processor 212, a cache unit 213, a medium interface 214 and an accelerator 215. The accelerator 215 is used to compare the L2P table and the P2L table according to the garbage collection comparison request initiated by the processor 212 during the garbage collection process, and provide the comparison result to the processor 212.

[0046] The host interface 211 is connected to the host 100 for communication with the host 100. The processor 212 is connected to the host interface 211 for read / write control, and in garbage collection, obtaining valid data in the storage medium 220, and rewriting valid data in the storage medium 220. The cache unit 213 is connected to the processor 212 for storing the forward mapping table. The medium interface 214 is connected to the processor 212 and the storage medium 220, and is used to write write data to the storage medium 220. The accelerator 215 is connected to the processor 212 for sequentially comparing multiple mapping relationships between the forward mapping table L2P and the reverse mapping table P2L in garbage collection to determine valid data and invalid data in the storage medium 220.

[0047] Furthermore, the storage medium 220 is used to store read and write data and a reverse mapping table P2L corresponding to the write data. The storage medium 220 includes at least a first physical block and a second physical block, and the rewrite operation in the garbage collection process is, for example, writing valid data in the first physical block into the second physical block. In other embodiments, the storage medium 220 may also include a greater number of physical blocks.

[0048] Figure 4 A flowchart of a garbage collection method for a solid state drive according to an embodiment of the present invention is shown. The storage medium 220 of the solid state drive 200 includes at least a first physical block and a second physical block. The specific steps of the garbage collection method include:

[0049] Step S10: Obtain L2P and P2L corresponding to the first physical block.

[0050] In this step, when garbage collection is performed on the selected first physical block, the forward mapping table L2P and the reverse mapping table P2L corresponding to the write data in the first physical block are first obtained. In this embodiment, the first physical block is the user physical block that currently needs to be garbage collected.

[0051] The obtained forward mapping table L2P and reverse mapping table P2L are provided to the accelerator 215 .

[0052] Step S20: Initiate a garbage collection request and prepare data and configuration registers.

[0053] In the present application, the accelerator 215 is used to compare the L2P and P2L corresponding to the first physical block, so the processor 212 generates a comparison request during the garbage collection process and submits the request to the accelerator 215. In this embodiment, the firmware executed by the processor 212 initiates the garbage collection comparison request and prepares data and configuration registers at the same time. In this embodiment, the prepared data is, for example, as shown in Table 1 below.

[0054] Table 1: Data prepared for garbage collection comparison request

[0055]

[0056]

[0057] In this embodiment, the processor 212 configures registers, for example, to configure an input queue and an output queue, so that the reverse mapping table and the comparison result respond in a format that conforms to the input queue and the output queue. The input queue and the output queue are respectively located between the accelerator 215 and the processor 212, the input queue is used to transmit the reverse mapping table, and the output queue is used to transmit the comparison result.

[0058] Step S30: the accelerator compares L2P and P2L in sequence;

[0059] In this step, the accelerator 215 compares the L2P and P2L corresponding to the first physical block according to the garbage collection comparison request to determine the number of valid data and the address of the valid data (e.g., valid FRAG position) in the first physical block. Further, before the comparison, the accelerator 215 also obtains information of the forward mapping table and the reverse mapping table according to the data prepared by the processor 212, such as the information shown in the table above including the starting address of the forward mapping table and the starting address of the reverse mapping table, so that the comparison process can proceed normally and the comparison result can be output according to the comparison response conforming to the output queue format.

[0060] The accelerator 215 includes a plurality of comparison units, which can compare a plurality of mapping records in the reverse mapping table with the mapping records in the forward mapping table at the same time, thereby improving the comparison speed.

[0061] Step S40: The processor processes other tasks or the next garbage collection task.

[0062] This step can be performed simultaneously with step S30, that is, after the processor 212 submits a garbage collection comparison request to the accelerator 215, while the accelerator 215 performs a mapping relationship comparison, the processor 212 can release its own hardware resources for new system tasks, such as processing other tasks or the next garbage collection task.

[0063] Step S50: Move valid data to the second physical block and update the L2P table and the P2L table according to the comparison result.

[0064] In this step, after completing the comparison, the accelerator 215 temporarily stores the corresponding number of valid data and the mapping relationship of the failed match, and stores the address of the valid data in the storage unit 213. Then the processor 212 checks the comparison result of the accelerator 215, and rewrites the valid data into the second physical block according to the number of valid data and the physical allocation unit address FAA of the valid data, and updates the L2P table and P2L table corresponding to the second physical block.

[0065] Step S60: Erasing all data in the first physical block.

[0066] All data in the first physical block are erased, so that the first physical block becomes a blank physical block, which can be used for subsequent data writing.

[0067] Specifically, in the above garbage collection method, the comparison process of the accelerator 215 is as follows: Figure 5 As shown, including:

[0068] Step S31: the accelerator obtains P2L mapping relationships one by one and compares them with multiple L2P mapping relationships.

[0069] In this step, the forward mapping table and the reverse mapping table corresponding to the first physical block both include multiple mapping relationships. When comparing, each reverse mapping relationship in the reverse mapping table is compared with the multiple forward mapping relationships in the forward mapping table one by one to determine whether the physical address stored in the reverse mapping table is a physical address of valid data. Therefore, it is necessary to obtain the mapping relationships of P2L one by one and compare them with L2P.

[0070] In this embodiment, in order to increase the comparison efficiency, a plurality of comparison units are provided in the accelerator 215, so that a plurality of P2L mapping relationships can be compared with L2P at the same time.

[0071] Step S32: Record the address corresponding to the valid data.

[0072] In this step, when a mapping relationship in the reverse mapping table can match a mapping relationship in the forward mapping table, it indicates that the data in the physical page corresponding to the mapping relationship is valid data. The physical allocation unit address FAA corresponding to the valid data is recorded.

[0073] Step S33: Determine whether the traversal comparison of P2L is completed.

[0074] In this step, by sequentially comparing the multiple mapping relationships in P2L with L2P, the amount of valid data in the first physical block and the corresponding physical allocation unit address FAA can be determined.

[0075] Furthermore, the structure of the accelerator 215 Figure 6The accelerator 215 includes: a comparator 2151, including multiple comparison units, for comparing multiple mapping relationships at the same time; a second storage unit 2152, for storing the forward mapping table L2P; a multi-way selection module 2153, connected to the comparator 2151, for selecting the output results of the multiple comparison units; a buffer 2154, connected to the multi-way selection module 2153, for storing the number of valid data and the comparison results that failed to match; and a collection control module 2155, connected to the buffer 2154, for outputting the number of valid data to the processor 212.

[0076] In addition, between the accelerator 215 and the processor 212, there are also an input queue 2161, an output queue 2162 and a first storage unit 2163. The input queue 2161 is connected to the comparator 2151; the output queue 2162 is connected to the collection control module 2155; and the first storage unit 2163 is connected to the multi-way selection module 2153.

[0077] In this embodiment, the input queue 2161 and the output queue 2162 are, for example, interactive interfaces, the input queue 2161 can transmit the reverse mapping table, and the output queue 2162 can output the data of the collection control module 2155 to the processor 212 in a comparison response format that conforms to the configuration. The first storage unit 2163 is, for example, a part of the cache unit 213, and is used to store the address corresponding to the valid data.

[0078] The comparator 2151 is connected to the processor 212 via the input queue 2161, and the comparator 2151 is used to receive the reverse mapping table transmitted from the input queue, and compare the multiple mapping relationships of the reverse mapping table with the forward mapping table through multiple comparison units at the same time; the multi-way selection module 2153 is connected to the comparator 2151, and is used to select the comparison results of the multiple comparison units, for example, outputting the valid data address with the comparison result matching to the first storage unit 2163, outputting the number of valid data with the comparison result matching to the buffer 2154, and outputting the comparison result matching to the buffer 2155. The result is an unmatched mapping relationship which is output to the buffer 2154; the buffer 2154 is connected to the multi-way selection module 2153, and is used to output the number of valid data to the processor 212 via the collection control module 2155 after the comparator 2151 completes the comparison of the reverse mapping table; the second storage unit 2152 is connected to the comparator 2151, and is used to store the forward mapping table used for comparison; the collection control module 2155 is used to receive the number of valid data and the unmatched comparison result and output it to the processor 212 in a comparison response that conforms to the format of the output queue 2162.

[0079] Furthermore, the comparator 2151 includes a plurality of comparison units, which receive different reverse mapping relationships from the input queue 2161 in turn, and compare the reverse mapping relationship with the plurality of forward mapping relationships in the forward mapping table. After completing the comparison, any comparison unit among the plurality of comparison units reacquires the uncompared reverse mapping relationship from the input queue 2161 and compares them. In addition, during the comparison process, the comparison unit outputs the comparison result to the multi-way selection module 2153, whether the corresponding forward mapping relationship and reverse mapping relationship are matched or the comparison operation is performed but still not matched.

[0080] In this embodiment, the second storage unit 2152 is, for example, a DDR (Double Data Rate) synchronous dynamic random access memory. The first storage unit 2163 is, for example, a static random access memory.

[0081] In an embodiment for comparing L2P with P2L, any comparison unit of the comparator 2151 takes out a mapping relationship of P2L from the input queue 2161, and then compares it with multiple mapping relationships of the forward mapping table L2P in the second storage unit 2152 in turn, such as Figure 7 As shown, the comparison result is output to the multi-way selection module 2153, and multiple comparison units can perform comparison operations simultaneously. If the mapping relationship of P2L can match the mapping relationship of L2P, that is, the mapping relationship corresponds to valid data, then the multi-way selection module 2153 stores the comparison result and the number of valid data in the buffer 2154, and records the physical allocation unit address FAA corresponding to the matching mapping relationship in the first storage unit 2163. When all P2Ls are compared, the set control module 2155 sends the number of all valid data to the output queue 2162, and the processor 212 migrates data according to the number of valid data and the address of the valid data stored in the first storage unit 2163.

[0082] In this embodiment, the accelerator 215 is, for example, an application specific integrated circuit ASIC.

[0083] The garbage collection method and control device for a solid-state hard disk provided by the present invention increase the garbage collection speed by adding an accelerator to the solid-state hard disk and using the accelerator to complete the task of comparing P2L and L2P, thereby completing garbage collection by combining firmware with the accelerator.

[0084] Furthermore, by using a firmware-accelerator approach to complete garbage collection, the request can be submitted to the accelerator during the valid data reconstruction phase, freeing up the central processor during this period to handle other tasks or perform the next garbage collection task, thereby achieving the purpose of acceleration.

[0085] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A control device for a solid state hard disk, wherein: The control device comprises: a processor, configured to initiate a garbage collection comparison request, receive a comparison result between a forward mapping table and a reverse mapping table outputted from an accelerator, obtain valid data in a storage medium according to the comparison result, and rewrite the valid data in the storage medium; and The accelerator is connected to the processor and is used to compare the multiple mapping relationships between the forward mapping table and the reverse mapping table in sequence according to the garbage collection comparison request initiated by the processor, and return the comparison result to the processor. ， The processor releases hardware resources for new system tasks after initiating a garbage collection request.

2. The control device according to claim 1, wherein: The accelerator comprises: A comparator, connected to the processor via an input queue, configured to receive a reverse mapping table input from the input queue and compare multiple mapping relationships simultaneously; A multi-way selection module, connected to the comparator, for selecting valid data addresses with matching comparison results and outputting them to the processor, and outputting the number of valid data with matching comparison results to the buffer; a buffer, connected to the multi-way selection module, for outputting the number of valid data to the processor after the comparator completes the comparison of the reverse mapping table; The second storage unit is connected to the comparator and is used to store a forward mapping table used for comparison.

3. The control device according to claim 1, wherein: The control device also includes a cache unit; The cache unit includes a first storage unit, which is connected to the processor and the accelerator respectively, and is used to cache the valid data address output from the accelerator and transmit it to the processor; The processor obtains the valid data from the storage medium according to the number of valid data and the valid data address.

4. The control device according to claim 3, wherein: Whenever the multiplexer receives a valid data address with a matching comparison result, the multiplexer transmits the received valid data address to the first storage unit.

5. The control device according to claim 2, wherein: The comparator includes a plurality of comparison units, and the plurality of comparison units sequentially receive different reverse mapping relationships, and the plurality of comparison units simultaneously perform comparison operations on the received reverse mapping relationships and a plurality of forward mapping relationships in the forward mapping table.

6. The control device according to claim 5, wherein: The plurality of comparison units are further configured to output comparison results to the multiplexer when a corresponding forward mapping relationship and a reverse mapping relationship are matched or when no match is found after the comparison operation is performed; The multiplexer is further configured to output unmatched comparison results to the buffer.

7. The control device according to claim 6, wherein: The accelerator further includes: a collection control module connected to the buffer and connected to the processor via an output queue; The set control module is used to receive the number of valid data and the unmatched comparison result and output a comparison response conforming to the output queue format to the processor.

8. The control device according to claim 1, wherein: The accelerator is an application specific integrated circuit ASIC.

9. A garbage collection method for a solid state hard disk, characterized in that: include: The processor initiates a garbage collection comparison request; The accelerator receives the garbage collection comparison request and compares the multiple mapping relationships of the forward mapping table and the reverse mapping table in sequence, and returns the comparison result to the processor; The processor checks the comparison result of the accelerator, obtains valid data in the storage medium according to the comparison result, and rewrites the valid data in the storage medium; The processor releases hardware resources for new system tasks after initiating a garbage collection request.

10. The garbage collection method according to claim 9, wherein: The step of the accelerator sequentially comparing the multiple mapping relationships in the forward mapping table and the reverse mapping table comprises: The multiple comparison units in the accelerator sequentially obtain a reverse mapping relationship in the reverse mapping table; The plurality of comparison units simultaneously perform comparison with the plurality of forward mapping relationships in the forward mapping table; Determine whether the traversal comparison of the reverse mapping table is completed; If the traversal is not completed, the multiple comparison units repeatedly execute the step of sequentially acquiring the reverse mapping relationship until the traversal is completed.

11. The garbage collection method according to claim 10, wherein: The step of the multiple comparison units simultaneously performing comparison with the multiple forward mapping relationships in the forward mapping table comprises: The plurality of comparison units respectively compare an acquired reverse mapping relationship with the plurality of forward mapping relationships at the same time to determine whether the reverse mapping relationship corresponds to the forward mapping relationship; If they correspond, the physical address in the reverse mapping relationship is used as the physical allocation unit address corresponding to the valid data.

12. The garbage collection method according to claim 9, wherein: The comparison result between the forward mapping table and the reverse mapping table includes: unmatched comparison results, the number of valid data and the address of valid data.

13. The garbage collection method according to claim 9, further comprising: The forward mapping table and the reverse mapping table are updated according to the rewriting operation of the valid data of the storage medium.

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