Method for processing real-time multi-task conflict based on Kylin operating system

Abstract

The invention relates to a method for processing real-time multi-task conflicts based on a Kylin operating system, which comprises the following steps of: establishing a data transmission priority of each subsystem, setting task interruption of the subsystem with the highest priority as reference interruption, and performing cycle counting on the period of the reference interruption to determine as an interruption counter; collecting interruption response time of task interruption of other subsystems; setting a counting interval of each subsystem in an interrupt counter; through logic design, in a counting interval corresponding to each subsystem, only task interruption of the system can take effect, and task interruption of other subsystems waits. According to the method, the data transmission priority of each subsystem is established, the task interruption of the subsystem with the highest priority is set as the reference interruption, the resource allocation efficiency is relatively high, and only one interruption task is responded in a counting interval, so that the task response conflict is eliminated, and the resource allocation efficiency is improved. Therefore, when asynchronous multiple tasks are executed, the tasks are not executed easily, and the error rate of execution errors is reduced.

Description

Technical Field

[0001] The present application relates to the field of computer data communication technology, and in particular to a method for processing real-time multi-task conflicts based on the Kylin operating system. Background Art

[0002] Kylin OS is an operating system product independently developed by China Aerospace Science and Technology Corporation based on domestically produced CPUs. It is specially customized for national security needs and is usually used in the military, government and critical information infrastructure. This operating system is based on the open source Linux kernel and emphasizes security and controllability.

[0003] The domestically produced hardware design and the Kylin operating system based on the open source system provide a strong guarantee for achieving the goal of 100% independent control. In the architecture of the domestic computer system, the PCIE high-speed serial bus is used for data transmission within the system, and different communication protocols are used for communication between systems according to needs, and FPGA is used to convert different data communication protocols. When the data communication and task response structures are complex, the Kylin operating system's ability to process tasks in real time will be stretched, and it is necessary to achieve control-wide real-time performance in the field of multi-system data communication and control to prevent control and communication conflicts between systems.

[0004] Therefore, it is necessary to propose a solution to improve one or more problems existing in the above-mentioned related technical solutions.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the present disclosure is to provide a method for processing real-time multi-task conflicts based on the Kylin operating system, thereby overcoming one or more problems caused by the limitations and defects of related technologies at least to a certain extent.

[0007] According to an embodiment of the present disclosure, a method for processing real-time multitasking conflicts based on the Kylin operating system includes the following steps:

[0008] Establish the data transmission priority of each subsystem, set the subsystem task interrupt with the highest priority as the reference interrupt, use a high-frequency clock as a driver in the FPGA of the main system, and count the period of the reference interrupt as an interrupt counter;

[0009] Collecting the interrupt response time of the task interrupts of other subsystems through the reference interrupt and the interrupt counter;

[0010] According to the interrupt response time of each subsystem, the counting interval of each subsystem in the interrupt counter is set so that each subsystem has a corresponding counting interval;

[0011] Through logical design, within the counting interval corresponding to each subsystem, only the task interruption of that system is effective, and the task interruptions of other subsystems are waiting.

[0012] In an exemplary embodiment of the present application, the steps before establishing the data transmission priority of each subsystem also include: each subsystem transmits data to the FPGA of the main system, and the FPGA of the main system converts and stores the data in the cache area according to the communication protocol with each subsystem.

[0013] In an exemplary embodiment of the present application, each subsystem has a corresponding counting interval, and the counting intervals corresponding to each subsystem have no intersection.

[0014] In an exemplary embodiment of the present application, the subsystem with the highest priority is a subsystem that has high real-time requirements, large data transmission volume, complex data structure, and regular transmission time interval compared to other subsystems.

[0015] In an exemplary embodiment of the present application, each subsystem and the main system use the same or different asynchronous communication transmission methods.

[0016] In an exemplary embodiment of the present application, the communication transmission mode includes RapidIO, RS422 and RS485.

[0017] In an exemplary embodiment of the present application, the establishment of the data transmission priority of each subsystem also includes establishing a system priority routing table.

[0018] In an exemplary embodiment of the present application, a subsystem in the subsystem whose transmission frequency is asynchronous and different from the reference interruption sets a counting interval that does not conflict with task interruptions of other subsystems.

[0019] In an exemplary embodiment of the present application, the interrupt response time of the task interrupts of the remaining subsystems is collected by using a logic analyzer.

[0020] In an exemplary embodiment of the present application, the main system is Kylin Operating System V10.

[0021] The present application proposes a method for handling real-time multi-task conflicts based on the Kylin operating system. On the one hand, by establishing the data transmission priority of each subsystem, the subsystem task interrupt with the highest priority is set as the benchmark interrupt, which has better resource allocation efficiency and improves the event execution rate. On the other hand, by responding to only one interrupt task within a counting interval, task response conflicts are eliminated, thereby reducing the error rate of task non-execution and execution errors that are prone to occur when executing asynchronous multi-tasking. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A schematic diagram showing the steps of a method for processing real-time multi-task conflicts based on the Kylin operating system in an exemplary embodiment of the present application;

[0024] Figure 2 A schematic diagram of the functional structure of the system in an exemplary embodiment of the present application is shown;

[0025] Figure 3 A schematic diagram of the system function flow in an exemplary embodiment of the present application is shown;

[0026] Figure 4 A schematic diagram of the message unit structure in an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0027] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0028] In addition, the accompanying drawings are only schematic illustrations of the present application and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0029] This example implementation provides a method for handling real-time multi-task conflicts based on the Kylin operating system. Figure 1 As shown, the following steps may be included:

[0030] Step S101: Establish data transmission priorities for each subsystem, set the highest priority subsystem task interrupt as a reference interrupt, use a high-frequency clock as a driver in the FPGA of the main system, and count the period of the reference interrupt as an interrupt counter.

[0031] Step S102: collecting the interrupt response time of the remaining subsystem task interrupts through the reference interrupt and the interrupt counter.

[0032] Step S103: according to the interrupt response time of each subsystem, set the counting interval of each subsystem in the interrupt counter so that each subsystem has a corresponding counting interval.

[0033] Step S104: through logic design, in the counting interval corresponding to each subsystem, only the task interruption of the system is effective, and the task interruptions of other subsystems are waiting.

[0034] The embodiment of the present application proposes a method for handling real-time multi-task conflicts based on the Kylin operating system. On the one hand, by establishing the data transmission priority of each subsystem, the subsystem task interrupt with the highest priority is set as the benchmark interrupt, which has better resource allocation efficiency and improves the event execution rate. On the other hand, by responding to only one interrupt task within a counting interval, task response conflicts are eliminated, thereby reducing the error rate of task non-execution and execution errors that are prone to occur when executing asynchronous multi-tasking.

[0035] Below, as Figure 1-Figure 4 As shown, a method for handling real-time multi-task conflicts based on the Kylin operating system proposed in this example embodiment will be described in more detail.

[0036] The computer system is the main system (CPU+FPGA) and other subsystems (such as Beidou system, servo system, signal processing system, etc.). Each subsystem uses the same or different asynchronous communication transmission methods with the main system, such as RapidIO, RS422, RS485, etc. For details of the system function structure, see Figure 2 shown.

[0037] After the system is powered on and started normally, a reset signal is sent to each subsystem through the FPGA of the main system to initialize the communication links and message units of all systems.

[0038] Step S101: Establish data transmission priorities for each subsystem, set the highest priority subsystem task interrupt as a reference interrupt, use a high-frequency clock as a driver in the FPGA of the main system, and count the period of the reference interrupt as an interrupt counter.

[0039] Specifically: After each subsystem transmits data to the FPGA, the FPGA takes on the responsibility of data conversion and caching, organizes the data in order according to different communication protocols, and stores it in the cache area. Subsequently, determining the priority according to the characteristics of the task becomes a key link. Tasks with high real-time requirements, such as tasks involving real-time control of key equipment, must be given priority to ensure that the system responds immediately; tasks with large data transmission volumes, such as large-scale data acquisition and transmission tasks, can be given priority to avoid data backlogs and transmission delays; tasks with complex data structures, such as image processing tasks containing multi-layer nested data structures, can improve processing efficiency by giving priority to their resources; tasks with regular transmission time intervals, such as periodic sensor data acquisition tasks, can help to reasonably allocate system resources and effectively utilize time slices by arranging priorities according to regularity.

[0040] Setting the highest priority task interrupt as the benchmark interrupt is like setting a "benchmark" among many tasks. Using the high-frequency clock drive in the FPGA, the interrupt counter is obtained by cyclically counting the period of the benchmark interrupt. This counter becomes the "ruler" for measuring the interrupt time of other tasks. At the same time, the system priority routing table established, as shown in Table 1, clearly draws a "map" of the system task priority, providing clear guidance for subsequent task scheduling.

[0041] Table 1. System priority routing table

[0042] Serial number system Priority 1 System One 1 2 System 2 2 3 System Three 3 … … … n System n

[0043] Step S102: collecting the interrupt response time of the remaining subsystem task interrupts through the reference interrupt and the interrupt counter.

[0044] Specifically: With the help of two key tools, the base interrupt and the interrupt counter, a logic analyzer is used to carefully sample the time relationship intervals between the remaining system task interrupts and the interrupt counter. Taking a specific system as an example, system 1 initiates a task request or completes data transmission to generate a task interrupt at a specific time (such as 100us) after the base interrupt is valid. If a 100MHz clock is selected as the interrupt counter driving clock, according to the relationship between the clock cycle and the count, it can be calculated that the system 1 task interrupt is transmitted within a certain interval (such as 9800-10200) of the interrupt counter. Through such precise time relationship determination, the system can clearly grasp the "time coordinates" of each subsystem task interrupt relative to the base interrupt, thereby providing a precise basis for the reasonable arrangement of subsequent tasks and ensuring that the tasks are carried out in an orderly manner.

[0045] Step S103: according to the interrupt response time of each subsystem, set the counting interval of each subsystem in the interrupt counter so that each subsystem has a corresponding counting interval.

[0046] Specifically: The logic analyzer collects the interrupt counter driving clock of each subsystem, and based on the relationship between the clock cycle and the count, calculates that a system-task interrupt is transmitted within a certain interval of the interrupt counter. However, there is overlap in the calculated count intervals. At this time, the interval of the system with the highest system priority is continued in sequence, and the count intervals corresponding to each subsystem are set to have no intersection.

[0047] In one embodiment of the present disclosure, the subsystem whose transmission frequency is asynchronous and different from the reference interrupt in the subsystem sets a counting interval that does not conflict with other subsystem task interrupts. It should be understood that the subsystem whose transmission frequency is asynchronous and different from the reference interrupt in the subsystem is a special subsystem task that performs data communication under specific conditions or is triggered by specific conditions, such as an emergency data transmission task triggered by an external emergency. Their triggering timing is difficult to predict and lacks a regular time pattern. Carefully selecting a counting interval that does not conflict with other system task interrupts in the interrupt counter is like finding an exclusive "time slot" for these special tasks on a busy timeline. Each time in this specific counting interval, the system accesses the data cache area of ​​the task and determines whether the interrupt is effective by judging whether the task is released. This mechanism opens up an independent "green channel" for irregular tasks, avoiding confusion and conflict between them and other tasks in interrupt triggering, ensuring that each task can be accurately triggered and executed at the right time, making the task scheduling of the entire system more flexible and reliable.

[0048] Step S104: through logic design, in the counting interval corresponding to each subsystem, only the task interruption of the system is effective, and the task interruptions of other subsystems are waiting.

[0049] Specifically: for each system task interrupt, after determining its effective counting interval in the interrupt counter, carefully designed logic rules are used to ensure that only this task interrupt can take effect within this interval, and other task interrupts must wait. The core of this logic lies in the dual judgment of time and task status. For example, for a system task interrupt, if it may take effect when the interrupt counter counts to 10,000,

[0050] The unique logic of the system task interrupt response can be designed as follows:

[0051] if((9800<interrupt counter≤10200)&(data write to buffer completed))

[0052] System 1 task interrupt == 1, indicating that the interrupt is effective;

[0053] else

[0054] System 1 task interrupt == 0, indicating that the interrupt is not effective.

[0055] At the same time, the judgment of whether the system data transmission or task request has all reached the cache area ensures that the task is interrupted only when the data is fully prepared, avoiding task execution errors caused by missing or incomplete data. This precise logic design is like the one-way rule in traffic control, which only allows one task to "pass" at each specific moment, effectively avoiding conflicts caused by multiple tasks competing for resources at the same time, and ensuring the orderliness and stability of system operation.

[0056] All system task interrupt logics are integrated into one logic module, which becomes the entire task interrupt management. The single execution feature of the if-else statement in the programming language is used to build strict rules for task interrupt response. When the system is running, at each time point, according to the value of the interrupt counter and the condition of each task, only one task interrupt that meets the specific conditions can be executed, and other tasks are in a waiting state. This precise control based on the code level fundamentally ensures that within the specified time zone, only one system task interrupt is responded to. Just like an intelligent dispatcher, it accurately directs the execution of each task according to the preset rules, eliminates the occurrence of task conflicts, ensures that the system runs stably and efficiently in a complex multi-task environment, and realizes effective handling of real-time multi-task conflicts.

[0057] Example 1

[0058] In this embodiment, the computer system uses a general embedded hardware architecture CPU+FPGA, the CPU uses Feiteng Tengrui D2000, the FPGA uses Fudan Micro JFM7K325T-N, and the operating system is Galaxy Kylin Operating System V10. In this embodiment, there are 7 subsystems, the data transmission with the signal processing system uses the RapidIO high-speed serial bus communication protocol, the data transmission with the Beidou timing system uses the RS485 serial port transmission protocol, and the remaining systems use the RS422 serial port transmission protocol.

[0059] It is important to understand that Feiteng Tengrui D2000 integrates 8 processor cores FTC663, is compatible with the 64-bit ARMV8 instruction set and supports both ARM64 and ARM32 execution modes; has a maximum main frequency of 2.3GHz, supports single-precision and double-precision floating-point operation instructions and ASIMD processing instructions; supports hardware virtualization; integrates system-level security mechanisms, and can meet the performance requirements and security and trust requirements in complex application scenarios. This product is suitable for building desktop terminals, portable terminals, lightweight servers and embedded low-power products with higher performance, energy efficiency and security needs.

[0060] Fudan Micro's JFM7K325T-N is a high-performance FPGA that integrates powerful and flexibly configurable programmable resources to implement multiple functions such as input and output interfaces, general digital logic, memory, digital signal processing, and clock management.

[0061] PCIe (PCI Express, a high-speed serial computer expansion bus standard) uses LVDS differential signal composition. Its 8b / 10b encoding and decoding mechanism can not only complete the clock embedding task, but also effectively prevent the frequency drift in the receiving PLL. It uses data packets for data transmission, which can ensure the reliability and accuracy of the data.

[0062] After the system starts normally, the FPGA sends a reset signal to each subsystem to initialize all communication links and message units.

[0063] The data transmission synchronization sequence generated inside the FPGA is used as the reference interrupt. The data transmission synchronization sequence is used as the interrupt for the computer system to actively send data to other subsystems. When the data transmission synchronization sequence is valid, the computer system will send data processing data or command requests to all levels of subsystems. The system priority establishes the routing table as shown in Table 2.

[0064] Table 2. System priority routing table

[0065] Serial number system Priority 1 Data transmission synchronization timing 1 2 Signal processing system 2 3 Attitude Indicator 3 4 Servo system 4 5 Wave control system 5 6 Frequency Synthesizer 6 7 BeiDou Timing System 7 8 Leveling system 8

[0066] The data transmission synchronization timing cycle is 12.5ms, and the interrupt drive clock uses a 200MHz clock, so the interrupt counter value ranges from 0 to 2499999. Through the relationship between the interrupt counter and the data transmission of each system sampled by the logic analyzer, it is determined that the interrupt response interval of the signal processing system is 1500000 to 1520000; the attitude instrument interrupt response interval is 1600000 to 1600200; the follow-up system interrupt response interval is 1620000 to 1620200; the wave control system interrupt response interval is 1640000 to 1640200; the frequency synthesizer interrupt response interval is 1660000 to 1660600.

[0067] The Beidou timing system has a fixed 1s transmission frequency, which is asynchronous and different from the reference interrupt. The Beidou timing system interrupt response interval is set to 1680000~1680600. The leveling system only transmits data when performing position correction after the system is started. The Beidou timing system interrupt response interval is set to 1700000~170020.

[0068] Take the above system interrupt response time, set the interrupt counter within the counting interval, only the system interrupt can take effect, and the other task interrupts are waiting; at the same time, determine that all the system data has been received in the buffer area (for example, a system interrupt can be generated when the interrupt counter counts to about 10000, and the unique interrupt response logic can be designed as follows:

[0069] if((1500000<interrupt counter≤1520000)&(signal processing data writing to buffer completed))

[0070] Signal processing system interrupt == 1, indicating that the interrupt is effective;

[0071] else

[0072] Signal processing system interrupt == 0, indicating that the interrupt is invalid;

[0073] All interrupt logic is designed in one logic module. Based on the single execution of if-else statements, it can be ensured that only one interrupt task is responded to within a period of time.

[0074] Through the above embodiments, the improved scheduling strategy based on priority has better resource allocation efficiency and higher event execution rate. On the basis of meeting real-time multi-tasking processing, it can complete the real-time response of radar events under forced resource occupation according to the priority, working status, temporary events and other related information of the event task.

[0075] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0076] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0077] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary technical means in the art that are not disclosed in the present application.

Claims

1. A method for processing real-time multi-task conflicts based on the Kylin operating system, characterized in that: The following steps are involved: Establish the data transmission priority of each subsystem, set the subsystem task interrupt with the highest priority as the reference interrupt, use a high-frequency clock as a driver in the FPGA of the main system, and count the period of the reference interrupt as an interrupt counter; Collecting the interrupt response time of the task interrupts of other subsystems through the reference interrupt and the interrupt counter; According to the interrupt response time of each subsystem, the counting interval of each subsystem in the interrupt counter is set so that each subsystem has a corresponding counting interval; Through logical design, within the counting interval corresponding to each subsystem, only the task interruption of that system is effective, and the task interruptions of other subsystems are waiting.

2. According to claim 1, the method for processing real-time multi-task conflicts based on the Kylin operating system is characterized in that: The steps before establishing the data transmission priority of each subsystem also include: each subsystem transmits data to the FPGA of the main system, and the FPGA of the main system converts the data and stores it in the buffer area according to the communication protocol with each subsystem.

3. According to claim 1, the method for processing real-time multi-task conflicts based on the Kylin operating system is characterized in that: Each of the subsystems has a corresponding counting interval, and the counting intervals corresponding to each subsystem have no intersection.

4. According to claim 1, the method for processing real-time multi-task conflicts based on the Kylin operating system is characterized in that: The subsystem with the highest priority is a subsystem that has high real-time requirements, large data transmission volume, complex data structure, and regular transmission time interval compared to other subsystems.

5. According to claim 1, the method for processing real-time multi-task conflicts based on the Kylin operating system is characterized in that: Each subsystem and the main system use the same or different asynchronous communication transmission methods.

6. The method for processing real-time multi-task conflicts based on the Kylin operating system according to claim 5 is characterized in that: The communication transmission modes include RapidIO, RS422 and RS485.

7. The method for processing real-time multitasking conflicts based on the Kylin operating system according to claim 1 is characterized in that: The establishment of the data transmission priority of each subsystem also includes establishing a system priority routing table.

8. The method for processing real-time multitasking conflicts based on the Kylin operating system according to claim 1 is characterized in that: The subsystem whose transmission frequency is asynchronous with the reference interrupt and whose source is different from that of the reference interrupt is set to a counting interval that does not conflict with task interrupts of other subsystems.

9. The method for processing real-time multitasking conflicts based on the Kylin operating system according to claim 1 is characterized in that: When collecting the interrupt response time of the task interruptions of the remaining subsystems, a logic analyzer is used to collect the interrupt response time of the task interruptions of the remaining subsystems.

10. The method for processing real-time multitasking conflicts based on the Kylin operating system according to claim 1, characterized in that: The main system is the Kylin operating system V10.

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