Slow-conversion serial interface IO transmitter with reduced delay PVT compensation

Abstract

A slow-conversion serial interface IO transmitter with PVT compensation with reduced latency is provided. More specifically, systems, apparatuses, and methods are provided for a serial peripheral interface, particularly a PVT compensated serial peripheral interface for a slow transition serial interface IO transmitter with reduced latency. The serial peripheral interface may include a driver circuit, a pre-driver circuit, a PVT compensation current sink circuit, and a PVT compensation current source circuit. The PVT compensation current sink circuit and the PVT compensation current source circuit may generate and transmit a signal that compensates for the PVT to a pre-driver circuit that may generate and transmit a signal that controls the IO data signal generated by the driver circuit. The generated IO data signal may be compensated for process, voltage, and temperature. The compensation may provide an IO data signal with slower transition times and reduced latency.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 543,380 filed on October 10, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments of the present invention generally relate to serial peripheral interfaces and, more particularly, to a PVT compensated serial peripheral interface with slow switching serial interface IO transmitters. Background Art

[0004] The Serial Peripheral Interface (SPI) is a serial interface for data communication. SPI is used in countless applications including mobile devices. SPI has transmit (Tx) and receive (Rx) functions for sending and receiving inputs and outputs at input / output terminals (IOs), respectively. SPI may have requirements on signals, including the rise time and fall time of the signal. Improvements in rise time and fall time and related extensions of rise time and fall time are needed, especially considering the range of capacitive loads used by IOs.

[0005] New SPI transmitters are needed. The inventors have identified many areas for improvement in the prior art and methods, which are the subject of the embodiments described herein. Through applied effort, creativity and innovation, many of these deficiencies, challenges and problems have been addressed by developing solutions included in the embodiments of the present disclosure, some examples of which are described in detail herein. Summary of the invention

[0006] Various embodiments described herein relate to systems, apparatus, and methods for a serial peripheral interface.

[0007] According to some embodiments of the present disclosure, an example serial peripheral interface is provided. The serial peripheral interface may include: a driver circuit including a P driver circuit and an N driver circuit; wherein the P driver circuit includes a first PMOSFET, the first PMOSFET being electrically connected to a voltage source at the source of the first PMOSFET and being electrically connected to a first terminal of a first resistor and a first terminal of a first capacitor at the drain of the first PMOSFET, wherein the second terminal of the first capacitor is electrically connected to a gate of the first PMOSFET; wherein the N driver circuit includes a first NMOSFET, the first NMOSFET being electrically connected to a first terminal of a second resistor and a first terminal of a second capacitor at the source of the first NMOSFET, and being electrically connected to ground at the drain of the first NMOSFET, wherein the second terminal of the second capacitor is electrically connected to a gate of the first PMOSFET; the second terminal being electrically connected to the gate of the first NMOSFET; wherein the second terminal of the first resistor is electrically connected to the second terminal of the second resistor and an input / output terminal; a pre-driver circuit comprising a P pre-driver circuit electrically connected to the gate of the first PMOSFET and an N pre-driver circuit electrically connected to the gate of the first NMOSFET, wherein the P pre-driver circuit is configured to generate a first PD signal and send the first PD signal to the gate of the first PMOSFET, wherein the N pre-driver circuit is configured to generate a first ND signal and provide the first ND signal to the gate of the NMOSFET; a PVT compensation current sink circuit electrically connected to the P pre-driver circuit; and a PVT compensation current source circuit electrically connected to the N pre-driver circuit.

[0008] According to some embodiments of the present disclosure, an example device is provided. The device includes: a serial peripheral interface, including: a driver circuit, including a P driver circuit and an N driver circuit; wherein the P driver circuit includes a first PMOSFET, the first PMOSFET is electrically connected to a voltage source at the source of the first PMOSFET and is electrically connected to a first terminal of a first resistor and a first terminal of a first capacitor at the drain of the first PMOSFET, wherein the second terminal of the first capacitor is electrically connected to the gate of the first PMOSFET; wherein the N driver circuit includes a first NMOSFET, the first NMOSFET is electrically connected to a first terminal of a second resistor and a first terminal of a second capacitor at the source of the first NMOSFET, and is electrically connected to ground at the drain of the first NMOSFET, wherein the second terminal of the second capacitor is electrically connected to the first NMOSFET. a gate of T; wherein the second terminal of the first resistor is electrically connected to the second terminal of the second resistor and an input / output terminal; a pre-driver circuit, comprising a P pre-driver circuit electrically connected to the gate of the first PMOSFET and an N pre-driver circuit electrically connected to the gate of the first NMOSFET, wherein the P pre-driver circuit is configured to generate a first PD signal and send the first PD signal to the gate of the first PMOSFET, wherein the N pre-driver circuit is configured to generate a first ND signal and provide the first ND signal to the gate of the NMOSFET; a PVT compensation current sink circuit electrically connected to the P pre-driver circuit; a PVT compensation current source circuit electrically connected to the N pre-driver circuit; and a processor configured to enable and disable the PVT compensation current sink circuit and the PVT compensation current source circuit.

[0009] In some embodiments, the PVT compensation current sink circuit is configured to generate a first current, wherein the P pre-driver circuit is configured to generate a second current equal to the first current.

[0010] In some embodiments, the first PD signal is generated based on at least the second current.

[0011] In some embodiments, the PVT compensation current source circuit is configured to generate a third current, wherein the N pre-driver circuit is configured to generate a fourth current equal to the third current.

[0012] In some embodiments, the first ND signal is generated based on at least the fourth current.

[0013] In some embodiments, the PVT compensation current sink circuit is configured to receive a first enable signal to control a first switch to enable the PVT compensation current sink circuit; and the PVT compensation current source circuit is configured to receive a second enable signal to control a second switch to enable the PVT compensation current source circuit.

[0014] In some embodiments, the PVT compensation current sink circuit is configured to generate a first current having a higher current value when the voltage of the voltage source increases.

[0015] According to some embodiments of the present disclosure, an example method for operating a circuit with a serial peripheral interface is provided. The method may include: providing a serial peripheral interface, the serial peripheral interface including: a driver circuit, including a P driver circuit and an N driver circuit; wherein the P driver circuit includes a first PMOSFET, the first PMOSFET is electrically connected to a voltage source at the source of the first PMOSFET and is electrically connected to a first terminal of a first resistor and a first terminal of a first capacitor at the drain of the first PMOSFET, wherein the second terminal of the first capacitor is electrically connected to the gate of the first PMOSFET; wherein the N driver circuit includes a first NMOSFET, the first NMOSFET is electrically connected to a first terminal of a second resistor and a first terminal of a second capacitor at the source of the first NMOSFET, and is electrically connected to ground at the drain of the first NMOSFET, wherein the The second terminal of the second capacitor is electrically connected to the gate of the first NMOSFET; the second terminal of the first resistor is electrically connected to the second terminal of the second resistor and the input / output terminal; a pre-driver circuit includes a P pre-driver circuit electrically connected to the gate of the first PMOSFET and an N pre-driver circuit electrically connected to the gate of the first NMOSFET; a PVT compensation current sink circuit electrically connected to the P pre-driver circuit; a PVT compensation current source circuit electrically connected to the N pre-driver circuit; a first PD signal is generated by the P pre-driver circuit based on at least a first enable signal; a first ND signal is generated by the N pre-driver circuit based on at least a second enable signal; and a first input / output signal is generated by the driver circuit at the input / output terminal based on the first PD signal and the first ND signal.

[0016] In some embodiments, the method further includes: generating a first current by the PVT compensation current sink circuit; generating a second current equal to the first current by the P pre-driver circuit; and wherein the first PD signal is generated based on at least the second current.

[0017] In some embodiments, the method further includes generating a third current by the PVT compensation current source circuit; generating a fourth current equal to the third current by the N pre-driver circuit; and wherein the first ND signal is generated based on at least the fourth current.

[0018] In some embodiments, generating the first current is based at least on compensating for process variations.

[0019] In some embodiments, generating the first current is based at least on compensating for a voltage change.

[0020] In some embodiments, generating the first current is based at least on compensating for temperature changes.

[0021] The above summary is provided only to summarize some example embodiments to provide a basic understanding of some aspects of the present disclosure. Therefore, it will be understood that the above embodiments are only examples and should not be interpreted as narrowing the scope or spirit of the present invention in any way. It will also be understood that the scope of the present disclosure covers many potential embodiments other than those summarized here, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Having thus generally described certain exemplary embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0023] Figure 1A illustrates a block diagram of a serial peripheral interface according to one or more embodiments of the present disclosure;

[0024] Figure 1B illustrates an example diagram of IO signals according to one or more embodiments of the present disclosure;

[0025] Figure 2 illustrates a block diagram of a transmitter of a serial peripheral device according to one or more embodiments of the present invention;

[0026] Figure 3 illustrates a block diagram of a transmitter of a serial peripheral device according to one or more embodiments of the present disclosure;

[0027] Figure 4A illustrates a block diagram of a PVT compensation current sink circuit according to one or more embodiments of the present disclosure;

[0028] Figure 4B illustrates a block diagram of a PVT compensation current sink circuit according to one or more embodiments of the present disclosure;

[0029] Figure 5 illustrates a diagram of example IO signals according to one or more embodiments of the present disclosure;

[0030] Fig. 6A A diagram illustrating example signals according to one or more embodiments of the present disclosure;

[0031] Figure 6B illustrates a zoom-in of a graph of an example signal according to one or more embodiments of the present disclosure;

[0032] Figure 7 illustrates a flowchart including an example method for operating a SPI according to one or more embodiments of the present disclosure; and

[0033] Figure 8 An example block diagram of a system or apparatus according to one or more embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0034] Some embodiments of the present disclosure will now be described more fully herein with reference to the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. Indeed, various embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure satisfies applicable legal requirements. Like reference numerals refer to like elements throughout.

[0035] As used herein, the term "comprising" means including but not limited to and should be interpreted in the manner in which it is commonly used in a patent context. The use of broader terms such as including, comprising, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and consisting primarily of.

[0036] The phrases "in various embodiments," "in one embodiment," "according to one embodiment," "in some embodiments," etc. generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0037] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0038] If the specification states that "may", "could", "should", "ought to", "preferably", "likely", "typically", "optionally", "for example", "often" or "might" (or other such language) be included or have a characteristic, a particular component or feature is not required to be included or have that characteristic. Such components or features may optionally be included in some embodiments or may be excluded.

[0039] The use of the term "circuit" as used herein with respect to a component of a system or device should be understood to include specific hardware configured to perform the functions associated with a particular circuit as described herein. The term "circuit" should be broadly understood to include hardware (e.g., electrical components, etc.) and, in some embodiments, software for configuring the hardware. For example, in some embodiments, a "circuit" may include processing circuits, communication circuits, input / output circuits, etc. In some embodiments, other elements may provide or supplement the functionality of a particular circuit.

[0040] Overview

[0041] The present invention relates to systems, devices and methods for slow switching serial interface IO transmitters with PVT compensation for reduced delay. In various embodiments, the circuits described herein provide current modulation of voltage mode IOs to reduce output delays through independent control of output rise / fall times by PVT compensation circuits. PVT refers to process, voltage, temperature.

[0042] Figure 1A A block diagram of a serial peripheral device according to one or more embodiments of the present disclosure is illustrated. SPI 100 is used as a serial interface for data communication. SPI communicates with input / output (IO) 110 (which may be an IO terminal) via a receiver (RX) 120 and a transmitter (Tx) 130. SPI 100 may provide bidirectional communication between a system or device incorporating SPI 100 (including SPI core 140) and an external device connected via IO 110 through a serial interface. Receiver 120 may receive data from IO 110 and send the data to SPI core 140. Transmitter may receive data from SPI core 140 and send the data to IO 110. In various embodiments, IO 110 may be an IO pad or terminal. SPI core 140 may include various hardware and / or software to control SPI, including the execution of one or more operations of receiver 120 and transmitter 130. Signals sent from IO 110 and signals sent to IO 110 have a rise time and a fall time.

[0043] Figure 1B An example diagram of IO signals according to one or more embodiments of the present disclosure is illustrated. Figure 1B The example diagrams of 120 include a receive diagram 150 and a transmit diagram 160. The receive diagram 150 illustrates a signal 152 received via the receiver 120, which may be an external clock signal. The transmit diagram 160 illustrates a signal transmitter via the transmitter 130. The received signal may include the external clock signal 152. The transmitter signal may include a transmitted output data signal 162.

[0044] like Figure 1BAs shown, both the external clock signal 152 and the output data signal 162 have rising edges and falling edges. Figure 1B As shown, the measurement between the rising edge of the external clock signal 152 and the similar point on the rising edge of the output data signal 162 is measured as Td. In various embodiments, Td can be referred to as a delay. This time delay Td can be a function of a loop delay. The loop delay can be the time taken to receive data (e.g., a receiver delay of the receiver 120), process data (e.g., a digital code logic delay in the SPI core 140), and send data (e.g., a transmitter delay of the transmitter 130).

[0045] The SPI interface 100 may need to comply with one or more standards. These standards may require specific speeds for various signals, which may place requirements on the time delay Td. For example, the SPI may require that the loop delay has a minimum and maximum time. Similarly, the transmitter delay may have a minimum and maximum time. However, high-speed devices may have loop delays within an acceptable time range, and this may be associated with a transmitter delay range that requires a slower transition time to reduce the transmitter delay.

[0046] The transmitter 130 of the SPI 100 may include programmable driver settings for resistor-based drivers, which may reduce process margins. The programmable driver settings may allow, for example, adjustment of capacitive loads to adjust time delays. These programmable drivers may introduce higher spreads by using MOSFETs and registers. For example, a MOSFET may have a 60% to 70% spread, while a register may have a 25% spread.

[0047] Various embodiments of the present disclosure may allow a single setting for a wide range of capacitive loads at the IO 110, and this may allow for the minimum rise time and fall time of the transition to be improved without adjusting driver settings. Various embodiments may reduce spread by providing PVT compensation, etc. as described herein. PVT compensation may reduce the need for programmable drivers and / or registers and allow for compensation of PVT without requiring programming to manage load and drive settings. Thus, PVT compensation may allow for not knowing the exact load (e.g., the capacitance of the IO 110, which may be between 10 pF and 50 pF) and provide a single setting that addresses the load range.

[0048] Various embodiments of the present disclosure may improve rise / fall times and associated spread. Additionally or alternatively, various embodiments of the present disclosure may improve SPI 100 by slowing down transmitter transition times, which may allow longer transmission lines to be used with SPI.

[0049] Figure 2A block diagram of a transmitter of a serial peripheral device according to one or more embodiments of the present disclosure is illustrated. Figure 2 The SPI 200 includes an IO 210, a driver circuit 220, a pre-driver circuit 230, a PVT compensation current sink circuit 240, a PVT compensation current source circuit 250, and a data processing circuit 260. As shown, the driver circuit 220 is electrically connected to the IO 210. The pre-driver circuit 230 is electrically connected to the driver circuit 220, the PVT compensation current sink circuit 240, the PVT compensation current source circuit 250, and the data processing circuit 260. The PVT compensation current sink circuit 240 and the PVT compensation current source circuit 250 are each electrically connected to the data processing circuit 260.

[0050] PVT compensation current sink circuit 240 and PVT compensation current source circuit 250 respectively provide signals that compensate for process, voltage, and / or temperature to pre-driver circuit 230. As further described herein, PVT compensation current sink circuit 240 includes a current sink and PVT compensation current source circuit 250 includes a current source.

[0051] Figure 3 A block diagram of a transmitter of a serial peripheral device according to one or more embodiments of the present disclosure is illustrated.

[0052] The capacitance of each drive capacitor, which is capacitor (CP) 326A and capacitor (CN) 326B, compensates and / or controls the IO rise / fall time based on the capacitance of the IO load, which is illustrated as capacitor (CIO) 306. The PVT compensation circuits (e.g., 240, 250) provide compensation to reduce the spread of charging and discharging the driver capacitors, and therefore reduce the rise / fall time associated with the capacitance of the IO load. Each PVT compensation circuit is associated with one of the specific drive capacitors. The PVT compensation current sink circuit 240 is associated with the drive capacitor of capacitor (CP) 326A. The PVT compensation current source circuit 250 is associated with the driver capacitor of capacitor (CP) 326B. Each PVT compensation circuit and associated capacitor provides control to slow down and / or speed up the rise / fall time of the IO signal. This includes, for example, slowing down the conversion of the IO signal to the IO 210. Additionally or alternatively, in various embodiments, the load capacitance, illustrated as capacitor (CIO) 306, may vary within a range of 10 pF to 50 pF, and the delay and transition time of the IO signal may be maintained within this capacitance range. The PVT compensation circuit may allow the driver 220 to be compensated to meet the desired time delay within this capacitance range.

[0053] like Figure 3As shown in FIG. 1 , the driver circuit 220 includes a P driver circuit 322A and an N driver circuit 322B. In various embodiments, the P driver circuit may be referred to as high logic and the N driver circuit may be referred to as low logic. The high logic of the SPI 100 may use one or more PMOSFETs, and the low logic may use one or more NMOSFETs. The PMOSFETs and NMOSFETs of the driver circuit 220 may be controlled by signals from the pre-driver circuit 230.

[0054] The P driver circuit 322A includes at least a PMOSFET (M1) 324A, a capacitor (CP) 326A, and a resistor (RPD) 328A. The gate of the PMOSFET (M1) 324A is electrically connected to the voltage source (VDD) 302A. The drain of the PMOSFET (M1) is electrically connected to the first terminal of the capacitor (CP) 326A and the first terminal of the resistor (RPD) 328A. The gate of the PMOSFET (M1) 324A is electrically connected to the second terminal of the capacitor (CP) 326A and the drain of the P pre-driver circuit 332A, in particular the PMOSFET (M3). In operation, when the PMOSFET (M1) 324A is particularly turned on, a first current (IDP) 382 can flow through the resistor (RPD) 328A.

[0055] The N-driver includes at least an NMOSFET (M2) 324B, a capacitor (CN) 326B, and a resistor (NPD) 328B. The source of the NMOSFET (M2) is electrically connected to the second terminal of the capacitor (CP) 326B and the second terminal of the resistor (NPD) 328B. The drain of the NMOSFET (M2) 324B is electrically connected to the ground (GND) 304A. The gate of the NMOSFET (M2) 324B is electrically connected to the first terminal of the capacitor (CO) 326B and the source of the N-pre-driver circuit 332B, in particular the NMOSFET (M8). In operation, when the NMOSFET (M2) 324B is particularly turned on, the second current (IDN) 384 can flow through the resistor (RPD) 328A.

[0056] IO 210 is electrically connected to a second terminal of resistor (RPD) 328A and a first terminal of resistor (RND) 328B. Resistor (RPD) 328A and resistor (RND) 328B may be used to reduce drive current and reduce drive current spread at the IO pad of IO 210. At the IO pad of IO 210, the external device will have a capacitance, which is illustrated as IO capacitor 306. Additionally or alternatively, capacitor (CP) 326A and capacitor (CN) 326B reduce the rise time and fall time of P driver circuit 332A and N driver circuit 332B, respectively.

[0057] In various embodiments, PMOSFET (M1) 324A may be a first MOSFET, FET, or transistor of driver circuit 220, and NMOSFET (M2) may be a second MOSFET, FET, or transistor of driver circuit 220. Capacitor (CP) 326A may be a first capacitor of driver circuit 220, and capacitor (CN) 326B may be a second capacitor. In various embodiments, first capacitor (CP) 326A and capacitor (CN) 326B may be Miller capacitors, such as a first Miller capacitor and a second Miller capacitor, respectively. Resistor (RPD) 328A may be a first resistor of driver circuit 220, and resistor (NPD) 328B may be a second resistor of the driver circuit.

[0058] In operation, for P driver circuit 332A, current IDP 382 will drive the charging and discharging of capacitor (CP) 326A. The charging and discharging of capacitor (CP) 326A will also be driven by the PD signal from P pre-driver circuit 332A, which will drive the rise and fall times of the transitions of IO 210.

[0059] In operation, for N driver circuit 332B, current IDN 384 will drive the charging and discharging of capacitor (CN) 326B. The charging and discharging of capacitor (CN) 326B will also be driven by the ND signal from N pre-driver circuit 332B, which will drive the rise and fall times of the transitions of IO 210.

[0060] Each of capacitor (CP) 326A and capacitor (CN) 326B) reduces the spread of the rise time and the fall time of the IO data signal sent to IO 210 .

[0061] In various embodiments, with lower capacitance IO loads (e.g., 10 pF capacitor (CIO) 306), the driver capacitors assist the lower capacitance (e.g., 10 pF) IO loads by increasing the speed of the rise and fall times. The capacitance of these driver capacitors will be lower due to coupling and also due to faster signal transitions associated with slower PD signals 372 and / or slower ND signals 374. At lower capacitance of the load at the IO 210, the corresponding PD signals 372 and / or ND signals 374 have slower transition times.

[0062] In various embodiments, with IO loads having higher capacitance (e.g., 50 pF capacitor (CIO) 306), the driver capacitors assist IO loads having higher capacitance (e.g., 50 pF) by slowing down the speed of the rise and fall times compared to IO loads having lower capacitance. These capacitors will reduce coupling with the corresponding PD signal 372 or ND signal 374. Therefore, the PD signal 372 or ND signal 374 will not appear to be slowed down.

[0063] In various embodiments, the PD signal 372 and the ND signal 374 may vary as the signal of the IO 210 varies.

[0064] Various embodiments may also include omitting additional current to or from the IO 210 , and thus no additional current leakage from the IO pad or IO terminal at the IO 210 .

[0065] Each of the P driver circuit 322A and the N driver circuit 322B is electrically connected to a corresponding portion of the pre-driver circuit 230. The pre-driver circuit 230 may include a P pre-driver circuit 332A and an N pre-driver circuit 322B. As shown, the P driver circuit 322A is electrically connected to the P pre-driver circuit 332A, and the N driver circuit 322B is electrically connected to the N pre-driver circuit 322B.

[0066] The P pre-driver circuit 332A may include a PMOSFET and two NMOSFETs. For example, the P pre-driver circuit 332A may include a PMOSFET (M3) 334A, an NMOSFET (M4) 334B, and an NMOSFET (M5) 334C.

[0067] In the P pre-driver circuit 322A, the source of the PMOSFET (M3) 334A may be electrically connected to the voltage source (302B). The drain of the PMOSFET (M3) 334A may be electrically connected to the source of the NMOSFET (M4) 334B and may also be electrically connected to the P driver circuit 322A, which may send the PD signal 372 to the P driver circuit 322A. The gate of the PMOSFET (M3) 334A and the gate of the NMOSFET (M4) 334B may be electrically connected together and connected to the data processing circuit 260, which may send the signal P pre-driver signal 266 to the P pre-driver circuit 332A at the electrical connection. The drain of the NMOSFET (M4) 334B may be electrically connected to the source of the NMOSFET (M5) 334C. The drain of the NMOSFET (M5) 334C may be electrically connected to the ground (GND) 304B. The gate of NMOSFET (M5) 334C may be electrically connected to PVT compensation current sink circuit 240, which may send P pre-driver compensation signal 242 to P pre-driver circuit 332A.

[0068] The N pre-driver circuit 332B may include an NMOSFET and two PMOSFETs. For example, the P pre-driver circuit 332B may include an NMOSFET (M6) 334D, an NMOSFET (M7) 334E, and a PMOSFET (M8) 334F.

[0069] In the N pre-driver circuit 322B, the source of the PMOSFET (M6) 334D may be electrically connected to the voltage source (302C). The drain of the PMOSFET (M6) 334D may be electrically connected to the source of the PMOSFET (M7) 334E. The gate of the PMOSFET (M6) 334D may be electrically connected to the PVT compensation current source circuit 250, which may send the N pre-driver compensation signal 252 to the N pre-driver circuit 332B. The drain of the PMOSFET (M7) 334E may be electrically connected to the source of the NMOSFET (M8) 334F, and may also be electrically connected to the N driver circuit 322B, which may send the ND signal 374 to the N driver circuit 322B. The gate of the PMOSFET (M7) 334E and the gate of the NMOSFET (M8) 334F may be electrically connected together and connected to the data processing circuit 260, which may send the signal N pre-driver signal 268 to the N pre-driver circuit 332B at the electrical connection. The drain of the NMOSFET (M8) 334F may be electrically connected to the ground (GND) 304C.

[0070] In various embodiments, voltage sources 302A, 302B, and 302C may be the same voltage source, different voltage sources, and / or different terminals to the same voltage source. Grounds 304A, 304B, and 304C may similarly be the same ground, different grounds, and / or different terminals to the same ground.

[0071] P pre-driver signal 266 may be generated by data processing circuit 260 to control P pre-driver circuit 332A to generate PD signal 372. N pre-driver signal 268 may be generated by data processing circuit 260 to control N pre-driver circuit 332B to generate NPD signal 374.

[0072] In various embodiments, the data processing circuit 260 may provide a first enable signal 262 to the PVT compensation current sink circuit 240 and a second enable signal 264 to the PVT compensation current source circuit. The first enable signal 262 and the second enable signal 264 may enable and / or disable the corresponding PVT compensation current sink circuit 240 and the PVT compensation current source circuit 250, for example, through a switch. When enabled, the PVT compensation current sink circuit 240 may compensate and / or control the PD signal 372 as described herein. When enabled, the PVT compensation current source circuit 250 may compensate and / or control the ND signal 374 as described herein.

[0073] Figure 4A A block diagram of a PVT compensation current sink circuit 240 according to one or more embodiments of the present disclosure is illustrated. The PVT compensation current sink circuit 240 may include a current sink 442 and four transistors. The four transistors may be a PMOSFET (M9) 444A, a PMOSFET (M10) 444B, a PMOSFET (M11) 444C, and an NMOSFET (M12) 444D. The PVT compensation current sink circuit 240 may also include a switch 446 controlled by a first enable signal 262. The first enable signal 262 may control the switch 446 to switch between connecting the gate of the PMOSFET (M9) 444A to ground (e.g., 404) and a voltage source (not shown). To disable the PMOSFET (M9), the gate of the PMOSFET (M9) may be switched to be electrically connected to a voltage source (e.g., voltage source (VDD) 402A).

[0074] like Figure 4AAs shown, the current sink 442 is electrically connected to the drain of the PMOSFET (M9) 444A. The drain of the PMOSFET (M9) 444A is also electrically connected to the gates of the PMOSFET (M10) 444B and the PMOSFET (M11) 444C. The source of the PMOSFET (M9) 444A is electrically connected to the voltage source (VDD) 402A. The sources of the PMOSFET (M10) 444B and the PMOSFET (M11) are electrically connected to the respective voltage sources (VDD) 402B and 402C. The drain of the PMOSFET 402B is electrically connected to the drain of the PMOSFET (M9) 444A, the first terminal of the current sink 442, and the gates of the PMOSFET (M10) 444B and the PMOSFET (M11) 444C. The drain of the PMOSFET (M11) 444C is electrically connected to the source and gate of the NMOSFET (M12) 444D and the pre-driver circuit 230 to send the P-pre-driver compensation signal 242. The drain of NMOSFET (M12) 444D is electrically connected to ground (GND) 404B.

[0075] In operation, the PVT compensation current sink circuit 240 may receive a first enable signal 262. The first enable signal 262 may cause the switch 446 to be electrically connected to ground. The connection to ground may operate to cause the four transistors to operate with the current sink 442 to generate a current IVP 496 from the source to the drain of the PMOSFET (M9) 444A and a current IBP 492A from the drain of the PMOSFET (M10) 444B. The current IBP 492A is the same as the current IBP 492B, which is also the same value as the current IBP 392 due to the P pre-driver compensation signal 242 provided to the pre-driver circuit 230. Therefore, the PVT compensation current sink circuit 240 compensates the pre-driver circuit 230, specifically the P pre-driver circuit 332A, thereby compensating the PD signal 372.

[0076] Figure 4BA block diagram of a PVT compensation current sink circuit 250 according to one or more embodiments of the present disclosure is illustrated. The PVT compensation current source circuit 250 may include a current source 444 and four transistors. The four transistors may be NMOSFET (M13) 454A, NMOSFET (M14) 454B, NMOSFET (M15) 454C, and PMOSFET (M16) 454D. The PVT compensation current source circuit 250 may also include a switch 456 controlled by a second enable signal 264. The second enable signal 264 may control the switch 456 to switch between connecting the gate of the NMOSFET (M13) 454A to a voltage source (e.g., 402F) and ground (not shown). To disable the NMOSFET (M13), the gate of the NMOSFET (M13) may be switched to be electrically connected to ground (e.g., ground (GND) 404C).

[0077] like Figure 4B As shown, a first terminal of current source 444 is electrically connected to voltage source (VDD) 402D. A second terminal of current source 444 is electrically connected to a source of NMOSFET (M13) 454A, a source of NMOSFET (M14) 454B, a gate of NMOSFET (M14) 454B, and a gate of NMOSFET (M15) 454C. A drain of NMOSFET (M13) 454A is electrically connected to ground (GND) 404C. A drain of NMOSFET (M14) 454B is electrically connected to ground (GND) 404D. A drain of NMOSFET (M15) 454C is electrically connected to ground (GND) 404E. A source of PMOSFET (M16) 454D is electrically connected to voltage source (VDD) 402E. The gate and source of the PMOSFET ( M16 ) 454D are electrically connected to the source of the NMOSFET ( M15 ) 454C and the pre-driver circuit 230 to send the N-pre-driver compensation signal 252 .

[0078] In operation, the PVT compensation current source circuit 250 may receive the second enable signal 264. The second enable signal 264 may cause the switch 448 to be electrically connected to the voltage source (VDD) 402F. The connection to the voltage source may operate to cause the four transistors to operate with the current source 444 to generate a current IVN 498 from the drain of the NMOSFET (M13) 454A and a current IBN 492A to the source of the NMOSFET (M14) 454B and the gates of the NMOSFET (M14) 454B and the NMOSFET (M15) 454C. The current IBN 494A is the same as the current IBN 494B, which is also the same value as the current IBN 394, due to the N pre-driver compensation signal 252 provided to the pre-driver circuit 230. Therefore, the PVT compensation current source circuit 250 compensates the pre-driver circuit 230, specifically the N pre-driver circuit 332B, which therefore compensates the ND signal 374.

[0079] In various embodiments, the PVT compensation circuit may compensate for process, voltage, and temperature. The compensation circuit 230 may reduce the spread of the PD signal 372 and the ND signal 374 , and thus may reduce the rise time and fall time of the IO 210 .

[0080] In various embodiments, the process can range from a fast process to a slow process. A fast process may be a process having a conversion time of input / output delay and propagation delay that is a minimum or lower than other processes. A slow process may be a process having a conversion time of input / output delay and a conversion time of propagation delay that is a maximum or higher than other processes.

[0081] When the process is fast, IVP 496 in PVT compensation current sink circuit 240 and IVN 498 in PVT compensation current sink circuit 250 may be larger, which respectively reduce IBP 492A and IBN 494A. When IBP 492A is reduced, IBP 392 of pre-driver circuit 230 is also reduced. Similarly, when IBN 494A is reduced, IBN 394 of pre-driver circuit 230 is also reduced.

[0082] When the process is slow, IVP 496 in the PVT compensation current sink circuit 240 and IVN 498 in the PVT compensation current source circuit 250 may be lower, which increases IBP 492A and IBN 494A, respectively. As IBP 492A increases, IBP 392 of the pre-driver circuit 230 also increases. Similarly, as IBN 494A increases, IBN 394 of the pre-driver circuit 230 also increases.

[0083] In various embodiments, the voltage may change, and the compensation circuit (e.g., 240, 250) may compensate for the change in voltage. For example, in various embodiments, the voltage may fluctuate between 1.68V and 1.98V. With compensation from the compensation circuit (e.g., 240, 250), when the voltage source 302 decreases, the current (e.g., current IDP 382 and current IDN 384) in the driver circuit 220 through the associated resistors (e.g., resistor (RPD) 328A and resistor (RND) 328B) will decrease. The decrease in current will cause the current (e.g., current IBP 392 and current IBN 394) in the pre-driver circuit 502 to decrease.

[0084] When the voltage increases or is at a maximum voltage, the IVP 496 in the PVT compensation current sink circuit 240 and the IVN 498 in the PVT compensation current sink circuit 250 may be larger, which respectively reduce the IBP 492A and the IBN 494A. When the IBP 492A decreases, the IBP 392 of the pre-driver circuit 230 also decreases. Similarly, when the IBN 494A decreases, the IBN 394 of the pre-driver circuit 230 also decreases.

[0085] When the voltage decreases or is at a minimum voltage, the IVP 496 in the PVT compensation current sink circuit 240 and the IVN 498 in the PVT compensation current source circuit 250 may be lower, which increases the IBP 492A and the IBN 494A, respectively. As the IBP 492A increases, the IBP 392 of the pre-driver circuit 230 also increases. Similarly, as the IBN 494A increases, the IBN 394 of the pre-driver circuit 230 also increases.

[0086] In various embodiments, the temperature may change, and the compensation circuit (eg, 240 , 250 ) may compensate for the change in temperature.

[0087] For the PVT compensation current sink circuit 240, the current of the current sink 442 compensates for changes in temperature. The current of the current sink 442 is a combination of the current IVP 496 and the current IBP 492A. The current IBP 492A is the same value as the current IBP 492B and the current IBP 392 of the P-pre-driver circuit 322A. Therefore, the temperature that causes the current of the current sink 442 to change compensates for the current IBP 392, which compensates or changes the voltage of the PD signal 372. As described herein, the compensation of the PD signal 372 to the signal to the IO 210.

[0088] For the PVT compensation current source circuit 250, the current of the current source 444 compensates for changes in temperature. The current of the current source 444 is a combination of the current IVN 498 and the current IBN 494A. The current IBN 494A is the same value as the current IBN 494B and the current IBN 394 of the N pre-driver circuit 322B. Therefore, the temperature change that causes the current of the current source 444 to change compensates for the current IBN 394, which compensates or changes the voltage of the ND signal 374. As described herein, the ND signal 374 compensates for the signal to the IO 210.

[0089] In various embodiments, the temperature to which the SPI 200 can be exposed can have a range, and the compensation circuit can compensate for changes in temperature. For example, the temperature can change with the operation of the SPI 200 and / or a system or device including or connected to the SPI 200. For example, the current sink 442 and / or the current source 444 can compensate for changes in temperature. The compensation can be achieved by controlling the pre-driver circuit 230 to generate a PD signal 372 and an ND signal 374, each signal respectively compensating and / or changing the charging and / or discharging of the associated capacitor (CP) 326A or capacitor (CN) 326B. The charging and / or discharging of these capacitors can control the IO rise time and fall time of the capacitor (CIO) 306. In addition and / or alternatively, this can be combined with (or not with) a resistor (RPD) 328A and a resistor (RND) 328B for reducing the process expansion of the driver circuit 220.

[0090] Figure 5 Graphs of example IO signals according to one or more embodiments of the present disclosure are illustrated. Graph 500 is a graph of voltage versus time for signals IO signal 540 , PD signal 20 , and ND signal 530 .

[0091] As illustrated, when the PD signal 520 goes low and the ND signal 530 goes high, the IO signal 510 changes from low to high (e.g., zero to 1). Likewise, when the PD signal 520 goes high and the ND signal 530 goes low, the IO signal 510 changes from high to low (e.g., 1 to zero). Furthermore, when the IO 210 is high (e.g., 1), then the ND signal is low and the PD signal is high. Alternatively, when the IO 210 is low (e.g., 0), the ND signal is high and the PD signal is low.

[0092] When the P driver circuit 322A is turned on (e.g., high or 1), then the IO capacitor 306 of the load will charge. Once charged, the closing of the N driver circuit 332B will not interfere with the charging of the IO capacitor (CIO) 306, which is performed by the P driver circuit 322A under the guidance of the PD signal 372, so the driver circuit 322A can follow the PD signal 372 to slowly charge the IO capacitor (CIO) 306 when the IO signal goes high.

[0093] In various embodiments, the PD signal 520 does not drop linearly. This reflects the behavior of the circuit of the SPI 200 and is based on the PD signal 520 generated from one PMOSFET (e.g., 334A) and two NMOSFETs (e.g., 334B and 33C) of the P pre-driver circuit 332A. The rise of the ND signal 530 does not rise linearly. This reflects the behavior of the circuit of the SPI 200 and is based on the ND signal 530 generated from two PMOSFETs (e.g., 334D and 334E) and one NMOSFET (e.g., 334F) of the N pre-driver circuit 332B. Therefore, in various embodiments, the falling signal can be faster than the rising signal.

[0094] Fig. 6A A diagram illustrating example signals according to one or more embodiments of the present disclosure is illustrated. Fig. 6A A first graph 602 including a voltage change of a data signal 610 (e.g., an input signal) over time and a second graph 604 showing a voltage change of multiple IO signals (e.g., output IO signals) over time. Compared to an improved SPI without the present disclosure, the multiple signals in graph 604 include rising and falling edges of an embodiment of the present disclosure.

[0095] Graph 602 illustrates a data signal 610 (eg, input signal) changing from low (eg, 0) to high (eg, 1.8) over time.

[0096] Diagram 604 illustrates four signals and how they respond to an SPI with a data signal 610. Two of the signals are a first signal 622 and a second signal 624, which are associated with an SPI that does not include an embodiment of the present disclosure. Two of the signals associated with an embodiment of the present disclosure include a third signal 632 and a fourth signal 634. The first signal 622 and the second signal 624 illustrate the expansion of the rise time of the data signal 610 according to the present disclosure over all corners. The third signal 632 and the fourth signal 634 illustrate the expansion of the rise time over all corners according to the present disclosure.

[0097] As illustrated in graph 604, the rising edge of signal 622 is faster than signal 632, and the rising edge of 634 is faster than signal 624. As also illustrated in graph 604, the falling edge of signal 622 is faster than signal 632, and the falling edge of 634 is faster than signal 624.

[0098] Figure 6B An enlargement of a graph of an example signal is illustrated in accordance with one or more embodiments of the present disclosure. Figure 6B To better illustrate the distinction between the four signals of graph 604 . Figure 6B It is demonstrated that embodiments according to the present disclosure reduce the spread of rise time (eg, the difference between the minimum rise time and the maximum rise time) and reduce the propagation rise delay (and vice versa for fall time and delay).

[0099] In various embodiments, the IO capacitor (CIO) 306 may range from 10 pF to 50 pF, the IO signal may be at a frequency of 27 MHz, and the supply voltage 302 may vary from 1.62 V to 1.98 V. Utilizing various embodiments of the present invention, the PVT compensation circuit of the PVT compensation current sink circuit 240 and the PVT compensation current source circuit 250 may be used to slow down the minimum transition time to 1.68 ns, which may be three times or 3x slower. This increase in transition time may allow the use of up to 4 inches of transmission line (TL) (which may be an increase from 0.66 inches). The longer TL is due to the frequency at 27 MHz not decaying as quickly. The increase in TL allows, for example, longer circuit traces. This allows larger circuits to be built. Additionally or alternatively, in various embodiments, the static pad leakage of the IO 210 may also not increase.

[0100] It should be readily understood that the embodiments of the systems and apparatus described herein may be configured in various additional and alternative ways besides those explicitly described herein.

[0101] Exemplary Methods

[0102] Figure 7 A flowchart including an example method for operating a SPI according to one or more embodiments of the present disclosure is illustrated.

[0103] At operation 702, one or more enable signals are generated. The data processing circuit 260 may be operated to generate one or more of a first enable signal 262 and / or a second enable signal 264. The first enable signal 262 may be sent to the PVT compensation current sink circuit 240. The second enable signal 264 may be sent to the PVT compensation current source circuit 250.

[0104] At operation 704, one or more PVT compensation circuits are enabled. The PVT compensation current sink circuit 240 may be enabled based on a first enable signal 262 received from the data processing circuit 260. The enable signal 262 may cause the switch 446 to operate to allow the PVT compensation current sink circuit 240 to generate the first enable signal 262.

[0105] The PVT compensation current source circuit 250 may be enabled according to the second enable signal 264 received from the data processing circuit 260. The second enable signal 264 may cause the switch 456 to operate to allow the PVT compensation current sink circuit 240 to generate the first enable signal 262.

[0106] At operation 706, one or more compensation currents are generated. After being enabled, the PVT compensation current sink circuit 240 may generate a P pre-driver compensation signal 242, which is sent to the P pre-driver circuit 332A. After being enabled, the PVT compensation current source circuit 250 may generate an N pre-driver compensation signal 252, which is sent to the N pre-driver circuit 332B.

[0107] At operation 708, a PD signal and / or an ND signal is generated. After receiving the P predriver compensation signal 242 and the P predriver signal 266, the P predriver circuit 332A generates a PD signal 372. After receiving the N predriver compensation signal 252 and the N predriver signal 268, the N predriver circuit 332A generates an ND signal 374.

[0108] At operation 710 , compensated IO signal(s) are generated. After receiving the PD signal 372 and / or the ND signal 374 , the driver circuit 220 generates compensated IO data signals that are sent to the IO 210 .

[0109] It will be appreciated that if the PVT compensation circuit is subject to changes in process, voltage and / or temperature, the PVT compensation circuit may generate one or more compensated, adjusted or new compensation currents (e.g., IBP 492A, IBN 494A) that will compensate for the PD signal 372 and / or ND signal 374, which will compensate and / or adjust the compensated IO signal to IO 210.

[0110] Exemplary Systems and Apparatus

[0111] Embodiments of the present disclosure herein include systems and apparatus having the SPI 200 described herein, which may be implemented in various embodiments.

[0112] Figure 8An example block diagram of a system or device according to one or more embodiments of the present disclosure is illustrated. Various embodiments may include a system or device of a mobile device, and the SPI interface 200 may be, for example, on a semiconductor chip of the mobile device. An example of such a semiconductor chip may be a system on chip (SOC) integrated circuit including the SPI 200.

[0113] The illustrated apparatus 800 may be a system and / or device including a processor 802, memory 804, communication circuitry 806, input / output circuitry 808, and all of which may be connected. While such connections are illustrated as a bus 310, it will be readily appreciated that there may be multiple other connections.

[0114] Although shown as a single box, the processor 802 may include multiple components and / or processor circuits. The processor 802 may be implemented as, for example, various components including one or more microprocessors and accompanying digital signal processors; one or more processors without an accompanying digital signal processor; one or more coprocessors; one or more multi-core processors; processing circuits; and various other processing elements. The processor may include an integrated circuit. In various embodiments, the processor 802 may be configured to execute applications, instructions, and / or programs stored in the processor 802, the memory 804, or otherwise accessible to the processor 802. When executed by the processor 802, these applications, instructions, and / or programs may enable the execution of one or more operations and / or functions described herein. Whether or not it is configured by hardware, firmware / software methods, or a combination thereof, the processor 802 may include an entity capable of performing operations and / or functions according to embodiments of the present disclosure when configured accordingly.

[0115] The memory 804 may include, for example, volatile memory, non-volatile memory, or a specific combination thereof. Although illustrated as a single block, the memory 804 may include multiple memory components. In various embodiments, the memory 804 may include, for example, random access memory, cache memory, flash memory, hard disk, a circuit configured to store information, or a combination thereof. The memory 804 may be configured to write or store data, information, applications, instructions, etc., so that the processor 802 can perform various operations and / or functions according to the embodiments of the present disclosure. For example, in at least some embodiments, the memory 804 may be configured to cache or cache data for processing by the processor 802. Additionally or alternatively, in at least some embodiments, the memory 804 may be configured to store program instructions for execution by the processor 802. The memory 804 may store information in the form of static and / or dynamic information. When performing operations and / or functions, the stored information may be stored and / or used by the processor 802.

[0116] The communication circuit 806 can be implemented as a circuit, hardware, a computer program product, or a combination thereof, which is configured to receive and / or send data from / to another component or device. The computer program product may include computer-readable program instructions stored on a computer-readable medium (e.g., memory 804) and executed by the processor 802. In various embodiments, the communication circuit 806 (such as with other components discussed herein) may be at least partially implemented as a part of the processor 802 or otherwise controlled by the processor 802. The communication circuit 806 may communicate with the processor 802, for example, via a bus 810. Such a bus 810 may be connected to the processor 802, and it may also be connected to one or more other components of the processor 802. The communication circuit 806 may include, for example, a transmitter, a receiver, a transceiver, a network interface card, and / or supporting hardware and / or firmware / software, and may be used to establish communication with (one or more) another component, (one or more) device, and / or (one or more) system. The communication circuitry 806 may be configured to receive and / or send data that may be stored by, for example, the memory 804 by using one or more protocols that may be used for communications between components, devices, and / or systems.

[0117] In various embodiments, the communication circuit 806 may be a SPI 200 as described herein, which may be connected to one or more external devices via the SPI 200 .

[0118] Input / output circuitry 808 can communicate with processor 802 to receive instructions input by an operator and / or provide auditory, visual, mechanical or other output to the operator. Input / output circuitry 808 may include support devices such as keyboards, mice, user interfaces, displays, touch screen displays, lights (e.g., warning lights), indicators, speakers and / or other input / output mechanisms. Input / output circuitry 808 may include one or more interfaces to which support devices may be connected. In various embodiments, aspects of input / output circuitry 808 may be implemented on a device used by an operator to communicate with processor 802. Input / output circuitry 808 may, for example, communicate with memory 804, communication circuitry 806 and / or any other component via bus 810.

[0119] It should be readily understood that the embodiments of the systems and apparatus described herein may be configured in various additional and alternative ways besides those explicitly described herein. SUMMARY OF THE INVENTION

[0121] The operation and / or function of the present disclosure have been described herein, such as in a flow chart. As will be understood, computer program instructions can be loaded onto a computer or other programmable device (e.g., hardware) to generate a machine so that the resulting computer or other programmable device implements the operation and / or function described in the flow chart box herein. These computer program instructions can also be stored in a computer-readable memory, which can guide a computer, a processor or other programmable device to operate and / or function in a particular manner so that the instructions stored in the computer-readable memory generate a product, the execution of which implements the operation and / or function described in the flow chart box. Computer program instructions can also be loaded onto a computer, a processor or other programmable device so that a series of operations are performed on a computer, a processor or other programmable device to generate a computer-implemented process, so that the instructions executed on a computer, a processor or other programmable device provide operations for implementing the functions and / or operations specified in the flow chart box. The flow chart box supports a combination of devices for performing specified operations and / or functions and a combination for performing specified operations and / or functions. It will be understood that one or more boxes of the flow chart and the combination of boxes in the flow chart can be implemented by a computer system based on special-purpose hardware or a combination of special-purpose hardware and computer instructions that perform specified operations and / or functions.

[0122] Although this specification includes many specific embodiments and implementation details, these should not be interpreted as limitations on the scope of any disclosure or content that can be claimed, but should be interpreted as descriptions of features peculiar to the specific embodiments of specific disclosures. Certain features described herein in the context of a separate embodiment may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although features may be described above as working in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may be directed to a variation of a sub-combination or a sub-combination.

[0123] Although operations and / or functions are illustrated in a particular order in the drawings, this should not be understood as requiring that such operations and / or functions be performed in the particular order shown or in a continuous order, or that all illustrated operations be performed to achieve the desired results. In some cases, operations and / or functions in an alternative order may be advantageous. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired results. Therefore, although specific embodiments of the subject matter have been described, other embodiments are within the scope of the appended claims.

[0124] Although this detailed description has set forth some embodiments of the invention, the appended claims cover other embodiments of the invention according to various modifications and improvements that differ from the described embodiments.

[0125] In the following claims, unless the specific terms "for" or "the step of" are used in a given claim, it is not intended that the claim should be interpreted under 35 U.S. Patent 112, paragraph 6.

Claims

1. A serial peripheral interface, comprising: A driver circuit, including a P driver circuit and an N driver circuit; wherein the P driver circuit includes a first PMOSFET electrically connected to a voltage source at a source of the first PMOSFET and electrically connected to a first terminal of a first resistor and a first terminal of a first capacitor at a drain of the first PMOSFET, wherein a second terminal of the first capacitor is electrically connected to a gate of the first PMOSFET; wherein the N-driver circuit includes a first NMOSFET electrically connected at a source of the first NMOSFET to a first terminal of a second resistor and a first terminal of a second capacitor and electrically connected to ground at a drain of the first NMOSFET, wherein a second terminal of the second capacitor is electrically connected to a gate of the first NMOSFET; wherein the second terminal of the first resistor is electrically connected to the second terminal of the second resistor and the input / output terminal; a pre-driver circuit including a P pre-driver circuit electrically connected to a gate of the first PMOSFET and an N pre-driver circuit electrically connected to a gate of the first NMOSFET, wherein the P pre-driver circuit is configured to generate a first PD signal and send the first PD signal to the gate of the first PMOSFET, wherein the N pre-driver circuit is configured to generate a first ND signal and provide the first ND signal to the gate of the NMOSFET; A PVT compensation current sink circuit electrically connected to the P pre-driver circuit; as well as The PVT compensation current source circuit is electrically connected to the N pre-driver circuit.

2. The serial peripheral interface of claim 1, wherein the PVT compensation current sink circuit is configured to generate a first current, wherein the P pre-driver circuit is configured to generate a second current equal to the first current. 3 . The serial peripheral interface of claim 2 , wherein the first PD signal is generated based on at least the second current. 4 . The serial peripheral interface of claim 1 , wherein the PVT compensation current source circuit is configured to generate a third current, wherein the N pre-driver circuit is configured to generate a fourth current equal to the third current. 5 . The serial peripheral interface according to claim 4 , wherein the first ND signal is generated based on at least the fourth current.

6. The serial peripheral interface of claim 1 , wherein the PVT compensation current sink circuit is configured to receive a first enable signal to control a first switch to enable the PVT compensation current sink circuit; and The PVT compensation current source circuit is configured to receive a second enable signal to control the second switch to enable the PVT compensation current source circuit. 7 . The serial peripheral interface of claim 1 , wherein the PVT compensation current sink circuit is configured to generate a first current having a higher current value when a voltage of a voltage source increases.

8. An apparatus comprising: Serial peripheral interfaces, including: A driver circuit, including a P driver circuit and an N driver circuit; wherein the P driver circuit includes a first PMOSFET electrically connected to a voltage source at a source of the first PMOSFET and electrically connected to a first terminal of a first resistor and a first terminal of a first capacitor at a drain of the first PMOSFET, wherein a second terminal of the first capacitor is electrically connected to a gate of the first PMOSFET; wherein the N-driver circuit includes a first NMOSFET electrically connected at a source of the first NMOSFET to a first terminal of a second resistor and a first terminal of a second capacitor and electrically connected to ground at a drain of the first NMOSFET, wherein a second terminal of the second capacitor is electrically connected to a gate of the first NMOSFET; wherein the second terminal of the first resistor is electrically connected to the second terminal of the second resistor and the input / output terminal; a pre-driver circuit including a P pre-driver circuit electrically connected to a gate of the first PMOSFET and an N pre-driver circuit electrically connected to a gate of the first NMOSFET, wherein the P pre-driver circuit is configured to generate a first PD signal and send the first PD signal to the gate of the first PMOSFET, wherein the N pre-driver circuit is configured to generate a first ND signal and provide the first ND signal to the gate of the NMOSFET; A PVT compensation current sink circuit electrically connected to the P pre-driver circuit; A PVT compensation current source circuit electrically connected to the N pre-driver circuit; and A processor is configured to enable and disable the PVT compensation current sink circuit and the PVT compensation current source circuit. 9 . The apparatus of claim 8 , wherein the PVT compensation current sink circuit is configured to generate a first current, wherein the P pre-driver circuit is configured to generate a second current equal to the first current.

10. The apparatus of claim 9, wherein the first PD signal is generated based on at least the second current. 11 . The apparatus of claim 8 , wherein the PVT compensation current source circuit is configured to generate a third current, wherein the N pre-driver circuit is configured to generate a fourth current equal to the third current. 12 . The apparatus of claim 11 , wherein the first ND signal is generated based on at least the fourth current.

13. The apparatus of claim 8, wherein the PVT compensation current sink circuit is configured to receive an enable signal to control a first switch to enable the PVT compensation current sink circuit; and The PVT compensation current source circuit is configured to receive a second enable signal to control the second switch to enable the PVT compensation current source circuit. 14 . The apparatus of claim 8 , wherein the PVT compensation current sink circuit is configured to generate the first current having a higher current value when a voltage of a voltage source increases.

15. A method of operating a circuit having a serial peripheral interface, comprising: A serial peripheral interface is provided, the serial peripheral interface comprising: A driver circuit, including a P driver circuit and an N driver circuit; wherein the P driver circuit includes a first PMOSFET electrically connected to a voltage source at a source of the first PMOSFET and electrically connected to a first terminal of a first resistor and a first terminal of a first capacitor at a drain of the first PMOSFET, wherein a second terminal of the first capacitor is electrically connected to a gate of the first PMOSFET; wherein the N-driver circuit includes a first NMOSFET electrically connected at a source of the first NMOSFET to a first terminal of a second resistor and a first terminal of a second capacitor and electrically connected to ground at a drain of the first NMOSFET, wherein a second terminal of the second capacitor is electrically connected to a gate of the first NMOSFET; wherein the second terminal of the first resistor is electrically connected to the second terminal of the second resistor and the input / output terminal; a pre-driver circuit comprising a P pre-driver circuit electrically connected to a gate of the first PMOSFET and an N pre-driver circuit electrically connected to a gate of the first NMOSFET; A PVT compensation current sink circuit electrically connected to the P pre-driver circuit; A PVT compensation current source circuit electrically connected to the N pre-driver circuit; generating, by the P pre-driver circuit, a first PD signal based at least on a first enable signal; generating, by the N pre-driver circuit, a first ND signal based at least on a second enable signal; and A first input / output signal is generated at the input / output terminal by the driver circuit based on the first PD signal and the first ND signal.

16. The method according to claim 15, further comprising: generating a first current by the PVT compensation current sink circuit; generating, by the P pre-driver circuit, a second current equal to the first current; as well as The first PD signal is generated based on at least the second current.

17. The method according to claim 15, further comprising: generating a third current by the PVT compensation current source circuit; generating, by the N pre-driver circuit, a fourth current equal to the third current; as well as The first ND signal is generated based on at least the fourth current. The method of claim 16 , wherein generating the first current is based at least on compensating for process variations.

19. The method of claim 16, wherein generating the first current is based at least on compensating for voltage changes.

20. The method of claim 16, wherein generating the first current is based at least on compensating for temperature changes.

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