SPI data transceiving sampling method based on MCU

Abstract

The invention discloses an MCU (Microprogrammed Control Unit)-based SPI (Serial Peripheral Interface) data transceiving sampling method, which comprises the following steps that: when an MCU chip communicates with peripheral equipment through an SPI, a TXD (Transmit Data) pin of the SPI samples data at a clk1 sampling clock rising edge, and the data is sent out by the TXD pin of the SPI, passes through a data sending logic circuit and then is sent to a PAD port of a slave through a PAD port of a host; the slave receives data and then processes the data, the data is sent to a PAD port of the host through a PAD port of the slave and reaches an RXD pin of the SPI interface after passing through a data receiving logic circuit in the host, and the RXD pin samples the data at the rising edge of a clk2 sampling clock. According to the invention, the sampling clock for sending the data and the sampling clock for receiving the data respectively adopt clock signals with different phases, so that received data sampling errors caused by time delay in the data transmission process are avoided, and the stability of SPI interface data transmission is ensured.

Description

Technical Field

[0001] The invention relates to the technical field of chip SPI interface data transmission, and in particular to an SPI data transceiver sampling method based on an MCU. Background Art

[0002] With the rapid development of the integrated circuit industry and the continuous improvement of IP integration technology and process technology, the scale of chips has grown exponentially and the structure has become more complex. Among them, MCU, the full name of Microcontroller Unit, integrates the central processing unit, storage module and many other interface modules into one chip. It is small, flexible and low-cost and has been widely used in the fields of industry and consumer electronics. SPI, the full name of Serial Peripheral Interface, is a high-speed, full-duplex, synchronous communication bus with the advantages of a small number of pins, simple communication and fast data transmission rate. SPI is an important interface method for MCU to communicate with various peripheral chips. When MCU communicates with peripheral devices through the SPI interface, MCU acts as the master, that is, the host, and the peripheral device acts as the slave. The communication process between the master and the slave includes sending and receiving data, and in the process of sending and receiving data, it is necessary to send and receive data according to clock sampling.

[0003] At present, in traditional SPI communication, there is a method for serial peripheral interface bus data transmission. The method first needs to detect the actual path delay of the serial peripheral interface bus data transmission. When the actual path delay is greater than the preset path delay, when the data transmission rate of the serial peripheral interface is high, the duty cycle and sampling time of the data transmission are calculated and adjusted according to the clock division parameters to reduce the impact of the path delay and improve the accuracy of sampling.

[0004] However, the current method for serial peripheral interface bus data transmission contains at least the following three problems: 1) The process is cumbersome. In order to improve the accuracy of data sampling, the existing data transmission method needs to first obtain the actual path delay of data transmission, and then calculate the duty cycle and sampling time of data transmission through the clock division parameter, and adjust the obtained duty cycle and sampling time according to the actual path delay to improve the sampling accuracy. The data transmission process requires multiple steps, which is cumbersome. 2) Unstable data transmission: The existing data transmission method can significantly improve the sampling accuracy by calculating and adjusting the duty cycle and sampling time of data transmission when the data transmission rate is high. However, when the data transmission rate is low, adjusting the duty cycle and sampling time of data transmission cannot significantly improve the sampling accuracy. In the data transmission process, unstable data transmission may occur, resulting in data sampling errors. 3) Low data transmission efficiency: In the existing data transmission method, the actual path delay corresponding to different data transmission rates is different. For each change in the data transmission rate, the duty cycle and sampling time of the data transmission need to be recalculated, thereby reducing the efficiency of data transmission. Summary of the invention

[0005] In view of the above three problems, the purpose of the present invention is to propose an SPI data transmission and reception sampling method based on MCU. By using clock signals of different phases for the sampling clock of the sending data and the sampling clock of the receiving data, when the MCU chip communicates with the peripheral device through the SPI interface, the sampling error of the receiving data caused by the delay in the data transmission process is avoided, the stability of the SPI interface data transmission is ensured, and the efficiency of the SPI interface data transmission is improved.

[0006] This is achieved through the following technical solutions: The invention discloses an SPI data receiving and sending sampling method based on an MCU. The method comprises the following steps: S1, when an MCU chip communicates with a peripheral device through an SPI interface, the MCU chip is used as a host and the peripheral device is used as a slave; in the host, the clk1 sampling clock and the clk2 sampling clock of the SPI interface are first set to rising edge sampling; when data is sent, the TXD pin of the SPI interface in the host samples data at the rising edge of the clk1 sampling clock, and the sampled data is first sent out by the TXD pin of the SPI interface in the host, reaches a PAD port of the host through a logic data sending logic circuit, reaches the PAD port of the slave through a MOSI data transmission line, and finally reaches the slave; S2, after the slave receives the data sent by the host, the slave returns the data to the host after processing, the returned data is sent to the PAD port of the host through a MISO data transmission line, reaches the RXD pin of the SPI interface in the host after passing through a logic data receiving logic circuit in the host, and finally the RXD pin of the SPI interface in the host samples data at the rising edge of the clk2 sampling clock.

[0007] The present invention proposes a method for realizing data sampling by adopting clocks with different phase relationships, which avoids sampling errors of received data caused by various delays when the host sends data to the slave, enables data to be stably transmitted from the host to the slave, and ensures the reliability and accuracy of data transmission via the SPI interface.

[0008] Preferably, in step S1, the communication process between the host and the slave includes sending data and receiving data. During the sending and receiving process, the SPI interface in the host needs to sample the sending and receiving data according to the sampling clock. By sampling the data, the burden of data storage and processing can be reduced, thereby increasing the data transmission speed.

[0009] Preferably, in step S1, the clk1 sampling clock represents the sampling clock for sending data, the clk2 sampling clock represents the sampling clock for receiving data, and the sampling clock for sending data and the sampling clock for receiving data respectively use clock signals with different phases. By using sampling clocks with different phases, the received data can be correctly sampled.

[0010] Preferably, the phase difference between the sampling clock for sending data and the sampling clock for receiving data is adjusted and determined according to the total delay of the data transmission process, wherein the total delay at least includes: the delay through the PAD port, the delay through the logic sending data logic circuit, and the delay through the logic receiving data logic circuit during the transmission process. By adjusting the phase difference of the sampling clock according to the specific delay, it is possible to avoid sampling errors of received data caused by various delays, so that data can be stably sampled.

[0011] Preferably, in step S1, rising edge sampling is used to trigger a sampling operation and sample data when the sampling clock jumps from a low level to a high level in each sampling clock cycle. By sampling data in a rising edge sampling manner, it is possible to ensure that data is acquired at the beginning of each cycle of the sampling clock, thereby reducing errors caused by signal fluctuations and improving the accuracy of data sampling.

[0012] Preferably, in step S1, both the host and the slave include a PAD port, and the PAD port is used to connect the MOSI data transmission line and the MISO data transmission line between the host and the slave for data input and output. By connecting the data transmission line between the host and the slave through the corresponding PAD port, network communication can be achieved between the host and the slave, and accurate data transmission can be ensured.

[0013] Preferably, the logic data sending logic circuit and the logic data receiving logic circuit both control and transmit the input data through multiple gate circuits, wherein the multiple gate circuits at least include: an AND gate, an OR gate, and a NOT gate. The flow and storage of the input data are controlled by the logic rules in the data logic circuit, which can ensure the accuracy of data transmission.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention adopts clock signals of different phases for the sampling clock of the sent data and the sampling clock of the received data, and the phase difference of the sampling clocks is adjusted and determined according to the total delay of the data transmission process. When the MCU chip communicates with the peripheral device through the SPI interface, the sampling error of the received data caused by the delay of the PAD port and the like during the data transmission process is avoided, so that the sent data can be efficiently and stably transmitted from the host to the slave, and the received data is correctly sampled, thereby ensuring the stability and accuracy of the SPI interface data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural diagram of an SPI data receiving and sending sampling method based on MCU; Figure 2 The figure shows a sampling signal square wave diagram and data signal timing diagram of an SPI data transmission and reception sampling method based on MCU. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0017] like Figure 1 As shown, it is a structural schematic diagram of an SPI data receiving and sending sampling method based on MCU, which includes two parts, SPI host and SPI slave, both of which include a PAD port for sending data and a PAD port for receiving data, and data is transmitted between them through MOSI data transmission line and MISO data transmission line; at the same time, the SPI host also includes two different logic circuits and two pins, TXD and RXD, and each pin has two component identifiers, D and Q. When the SPI host and SPI slave communicate through the SPI interface, the data is sent from the TXD pin of the SPI interface in the host, passes through the logic data transmission logic circuit, and is then sent to the PAD port of the slave through the PAD port of the host; after the slave receives the data sent by the host, it returns the data to the host after processing, and the data is sent to the PAD port of the host through the PAD port of the slave, and reaches the RXD pin of the SPI interface in the host after passing through the logic data receiving logic circuit in the host, thereby stably completing the SPI interface data transmission.

[0018] The method specifically comprises the following steps: S1. When the MCU chip communicates with the peripheral device through the SPI interface, the MCU chip is used as the host and the peripheral device is used as the slave; in the host, the clk1 sampling clock and the clk2 sampling clock of the SPI interface are first set to rising edge sampling; when sending data, the TXD pin of the SPI interface in the host samples the data at the beginning of each cycle of the clk1 sampling clock, and the sampled data is sent out by the TXD pin of the SPI interface in the host, and the data passes through the logic sending data logic circuit, and the logic sending data logic circuit controls the data flow to the PAD port of the host sending data according to the logic rules in the circuit. After the data reaches the PAD port of the host sending data, it reaches the PAD port of the slave receiving data through the MOSI data transmission line, and finally reaches the slave. Among them, TXD, namely Transmit Data, refers to the pin for sending data, and is used in the present invention to send data after sampling the rising edge of the data; the MOSI data transmission line, namely Master OutSlave In, is the data transmission line from the host to the slave, and is used to send data from the host to the slave; the PAD port is used to connect the MOSI data transmission line and the MISO data transmission line between the host and the slave, so as to realize network communication between the host and the slave, and at the same time ensure the accurate transmission of data.

[0019] In this embodiment, in step S1, rising edge sampling is used to trigger a sampling operation and sample data when the sampling clock jumps from a low level to a high level in each sampling clock cycle. By sampling data in a rising edge sampling manner, it is possible to ensure that data is acquired at the beginning of each cycle of the sampling clock, thereby reducing errors caused by signal fluctuations and improving the accuracy of data sampling.

[0020] S2, after receiving the data sent by the host, the slave returns the data to the host after processing, and the returned data is sent from the PAD port of the slave to the PAD port of the host to receive data through the MISO data transmission line, and passes through the logic receiving data logic circuit in the host. The logic receiving data logic circuit controls the return data to flow to the RXD pin of the SPI interface in the host according to the logic rules in the circuit, and finally the RXD pin of the SPI interface in the host samples the data at the beginning of each cycle of the clk2 sampling clock. Among them, the MISO data transmission line, namely Master In Slave Out, is a data transmission line from the slave to the host, which is used to send data from the slave to the host; the RXD pin, namely Received Data, refers to the pin for receiving data, which is used to receive data and sample data in the present invention.

[0021] In this embodiment, the logic data transmission logic circuit and the logic data receiving logic circuit are both conventional logic control circuits, which control and transmit input data through multiple gate circuits. The logic data transmission logic circuit is used to control the transmission data flow to the PAD port of the host to send data, and the logic data receiving logic circuit is used to control the reception data flow to the RXD pin; wherein the multiple gate circuits at least include: an AND gate, an OR gate, and a NOT gate. By controlling the flow and storage of input data through the logic rules in the data logic circuit, the accuracy of data transmission can be ensured.

[0022] In this embodiment, the communication process between the host and the slave includes sending data and receiving data. During the process of sending data and receiving data, the SPI interface in the host needs to sample the sending data and receiving data according to the sampling clock, and the sampling clock of the sending data and the sampling clock of the receiving data respectively use clock signals of different phases, and their phase difference is adjusted and determined according to the total delay of the data transmission process. Among them, the total delay at least includes: the delay through the PAD port during the transmission process, the delay through the logic sending data logic circuit, and the delay through the logic receiving data logic circuit. By sampling the data, the burden of data storage and processing can be reduced, thereby increasing the data transmission speed; at the same time, by adjusting the phase difference of the sampling clock according to the specific delay, obtaining sampling clocks of different phases, it is possible to avoid sampling errors of received data caused by various delays, so that the received data can be sampled correctly and stably.

[0023] like Figure 2 As shown in the figure, it is a sampling signal square wave diagram and data signal timing diagram of the SPI data receiving and transmitting sampling method based on MCU. In the figure, the clk1 clock signal represents the sampling clock for sending data, the clk2 clock signal represents the sampling clock for receiving data, MOSI represents the data information transmitted from the host to the slave, and MISO represents the data information transmitted from the slave to the host. Among them, bit0, bit1, bit2, bit3, bit4, bit5, bit6 and bit7 are eight binary numbers with different values, which respectively represent different data transmitted between the host and the slave. The symbol Δ represents the phase difference between the clk1 sampling clock and the clk2 sampling clock. By adopting sampling clocks with different phases, the received data can be sampled correctly.

[0024] In summary, the present invention adopts clock signals of different phases for the sampling clock of sending data and the sampling clock of receiving data, and the phase difference of the sampling clock is adjusted and determined according to the total delay of the data transmission process. When the MCU chip communicates with the peripheral device through the SPI interface, the sampling error of the received data caused by the delay of the PAD port and the like during the data transmission process is avoided, so that the sent data can be efficiently and stably transmitted from the host to the slave, and the received data is correctly sampled, thereby ensuring the stability and accuracy of the SPI interface data transmission, and having significant progress.

[0025] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A SPI data transceiver sampling method based on MCU, characterized in that: The method comprises the following steps: S1. When the MCU chip communicates with the peripheral device through the SPI interface, the MCU chip is used as the host and the peripheral device is used as the slave. In the host, the clk1 sampling clock and the clk2 sampling clock of the SPI interface are first set to rising edge sampling. When sending data, the TXD pin of the SPI interface in the host samples data at the rising edge of the clk1 sampling clock, and the sampled data is first sent out by the TXD pin of the SPI interface in the host, and then reaches the PAD port of the host through the logic data transmission logic circuit, and then reaches the PAD port of the slave through the MOSI data transmission line, and finally reaches the slave. S2. After the slave receives the data sent by the host, it returns the data to the host after processing. The returned data is sent to the PAD port of the host through the MISO data transmission line, and reaches the RXD pin of the SPI interface in the host after passing through the logic receiving data logic circuit in the host. Finally, the RXD pin of the SPI interface in the host samples the data at the rising edge of the clk2 sampling clock.

2. A SPI data transceiver sampling method based on MCU according to claim 1, characterized in that, In step S1, the communication process between the host and the slave includes sending data and receiving data. During the process of sending data and receiving data, the SPI interface in the host needs to sample the sending data and receiving data according to the sampling clock.

3. A SPI data transceiver sampling method based on MCU according to claim 1, characterized in that, In step S1 , the clk1 sampling clock represents the sampling clock for sending data, and the clk2 sampling clock represents the sampling clock for receiving data. The sampling clock for sending data and the sampling clock for receiving data respectively use clock signals with different phases.

4. A SPI data transceiver sampling method based on MCU according to claim 3, characterized in that, The phase difference between the sampling clock for sending data and the sampling clock for receiving data is adjusted and determined according to the total delay of the data transmission process, wherein the total delay at least includes: the delay through the PAD port during the transmission process, the delay through the logic sending data logic circuit and the delay through the logic receiving data logic circuit.

5. A SPI data transceiver sampling method based on MCU according to claim 1, characterized in that, In step S1, rising edge sampling is used to trigger a sampling operation and sample data when the sampling clock jumps from a low level to a high level in each sampling clock cycle.

6. A SPI data transceiver sampling method based on MCU according to claim 1, characterized in that: In step S1, both the host and the slave include a PAD port, and the PAD port is used to connect the MOSI data transmission line and the MISO data transmission line between the host and the slave for data input and output.

7. A SPI data transceiver sampling method based on MCU according to claim 1, characterized in that: Both the logic data sending logic circuit and the logic data receiving logic circuit control and transmit the input data through multiple gate circuits, wherein the multiple gate circuits at least include: an AND gate, an OR gate and a NOT gate.

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