Integrated circuit and operating method thereof

Abstract

The invention provides an integrated circuit and an operation method thereof. A high order searched in a three-dimensional NAND gate memory is used to receive a search applied to select lines and word lines of a non-volatile three-dimensional memory array. The search word is presented in the three-dimensional NAND memory along a bit line direction of the three-dimensional NAND memory. Each character of the character includes a number of digits, each number matching a respective layer of the three-dimensional NAND memory. Each number may be used to represent one of a plurality of levels according to the selected coding. Selectively, characters of various lengths are accommodated by sequential and / or parallel operation of one or more three-dimensional NAND memories.

Description

Technical Field

[0001] The present invention relates to a three-dimensional memory search, which can be implemented by a three-dimensional NAND gate memory and can be applied to big data and / or artificial intelligence (AI) processing, and in particular to a high-level architecture of a three-dimensional NAND gate memory search and its application method. Background Art

[0002] The growth of big data and AI (e.g., AI hardware accelerators) is increasing the importance of searching, comparing, and / or sorting data. Conventional systems use ternary content addressable memory (TCAM) technology to implement concurrent searching.

[0003] Conventional TCAM technology may be implemented using static random access memory (SRAM) technology, and thus has relatively low memory density (eg, 16 transistors form a single TCAM cell) and relatively high power consumption.

[0004] Recently proposed TCAM technology can be implemented using non-volatile memory technology, such as two transistor two resistor (2T2R) technology and two ferroelectric field-effect transistor (2FeFET) technology. However, TCAM technology implemented with non-volatile memory requires paired memories for a single TCAM cell (or paired memory cells to implement one search bit or one data bit), so the efficiency of search and data storage is limited.

[0005] PHTseng et al. describe an example technology for an in-memory search function using a NAND-based flash memory capable of performing both exact and approximate match operations. Example technology for an in-memory search architecture based on 3D-NAND technology with ultra-high parallelism (IEDM) (2020). PHTseng et al. describe an example technology for an in-memory approximate computing architecture based on 3D-NAND flash memory (VLSI) (2022).

[0006] Therefore, there is a need for technologies that can achieve efficient searching, comparison and / or classification, such as technologies related to big data and / or AI processing. Summary of the invention

[0007] A system of one or more computers may be configured to perform specific operations or actions by virtue of software, firmware, hardware, or a combination thereof installed on the system, which in operation causes or results in the system performing specific operations or actions. One or more computer programs may be configured to perform specific operations or actions by virtue of containing instructions that, when executed by a data processing device, cause the device to perform specific operations or actions.

[0008] A first aspect includes an integrated circuit, the integrated circuit including a three-dimensional NAND (3D-NAND) memory array, a data encoder, a search encoder, and a logic operation module. The three-dimensional NAND memory array includes a plurality of bit lines coupled to respective sense amplifiers. The data encoder is capable of encoding data according to a specific code for storage in the three-dimensional NAND memory array. The search encoder is capable of (i) encoding a first search word to generate an encoded first search word encoded according to the specific code, (ii) encoding a second search word to generate an encoded second search word encoded according to the specific code, and (iii) applying the encoded first search word and the encoded second search word to respective first and second portions of the three-dimensional NAND memory array, respectively. The logic operation module is capable of performing one of a plurality of selectable logic operations. The first portion of the three-dimensional NAND memory array is capable of responding to a first portion of data stored therein, and further responding to the encoded first search word to generate a first sensing result using a first portion of the respective sense amplifiers. The second portion of the three-dimensional NAND gate memory array is responsive to a second portion of the data stored therein and further responsive to the encoded second search word to generate a second sensing result using a second portion of the respective sense amplifiers. The logic operation module is capable of processing the first sensing result and the second sensing result according to a selected one of the selectable logic operations. Other examples of this aspect include corresponding computer systems, devices, and computer programs recorded on one or more computer storage devices, each of which is configured to perform the actions of the method.

[0009] A variation may optionally include one or more of the following features. In the integrated circuit, the plurality of selectable logic operations include a logical AND operation, a logical OR operation, a logical XNOR operation, and a logical XOR operation. The specific encoding is based on a pair of memory devices using a three-dimensional NAND gate memory array to store a number of data values ​​of a first portion of the data, and further based on using a pair of word lines to apply a number of first search words to the pair of memory devices. The specific encoding is based on the states of 0, 1, and X respectively set by the threshold voltage (Vt) of the first and second memory devices of the pair of memory devices. The specific encoding is based on the states of 0, 1, 2, 3, 4, 5, 6, and 7 respectively set by the threshold voltage of the first and second memory devices of the pair of memory devices. The first search word may optionally include a plurality of numbers, and the search encoder is further capable of encoding a number of the plurality of numbers corresponding to a plurality of layers storing the first portion of the data. The plurality of layers corresponds to one or more planar process layers of the integrated circuit. The word lines of a first portion of the three-dimensional NAND memory array are separated from the word lines of a second portion of the three-dimensional NAND memory array. The first search word element and the second search word element vary according to the number of characters, the number of digits per character, or both. Variations of the described techniques include hardware, methods or processes, or computer software on a computer-accessible medium.

[0010] A second aspect includes a method, the method comprising receiving a first search word and a second search word in a three-dimensional NAND gate memory; searching the first search word in the stored values ​​of the three-dimensional NAND gate memory to generate a first bit line sensing result; searching the second search word in the stored values ​​of the three-dimensional NAND gate memory to generate a second bit line sensing result; combining the first bit line sensing result and the second bit line sensing result according to a selected one of a plurality of optional logical operations to generate an overall search result; and wherein the combination is performed using circuits on the same integrated circuit chip including the three-dimensional NAND gate memory. Other examples of this aspect include corresponding computer systems, apparatuses, and computer programs recorded on one or more computer storage devices, each of which is configured to perform the actions of the method.

[0011] The variant may optionally include one or more of the following features. In this method, the plurality of selectable logical operations optionally include a logical AND operation, a logical OR operation, a logical XOR operation, and a logical XOR operation. The storage value is encoded according to a specific code, the search for the first search word includes encoding the first search word according to the specific code, and the search for the second search word includes encoding the second search word according to the specific code. The specific code is based on a pair of memory devices using a three-dimensional AND gate memory to store a number of the storage values, and further based on using a pair of word lines to apply a number of the first search word to the pair of memory devices. The specific code is based on representing the states of 0, 1, and X by respectively setting the threshold voltages of the first and second memory devices of the pair of memory devices. The specific code is based on representing the states of 0, 1, 2, 3, 4, 5, 6, and 7 by respectively setting the threshold voltages of the first and second memory devices of the pair of memory devices. The first search word includes a plurality of digits, and the search for the first search word includes searching for each of these digits in layers corresponding to a plurality of layers organizing the stored values ​​of the three-dimensional NAND memory. The layers correspond to one or more planar processing layers of an integrated circuit including the three-dimensional NAND memory. The search for the first search word and the search for the second search word are performed in parallel using a first portion of the three-dimensional NAND memory and a second portion of the three-dimensional NAND memory, respectively, the word lines of the first portion are separated from the word lines of the second portion, and the bit lines of the first portion are separated from the bit lines of the second portion. The first search word and the second search word vary according to the number of characters, the number of digits per character, or both. Variations of the described technology selectively include hardware, methods or processes, or computer software on a computer-accessible medium.

[0012] The third aspect includes an integrated circuit. The integrated circuit includes a first three-dimensional NAND gate memory array and a second three-dimensional NAND gate memory array, a data encoder, a search encoder, and a logic operation module. The first three-dimensional NAND gate memory array includes a first bit line coupled to a respective first sense amplifier, and the second three-dimensional NAND gate memory array includes a second bit line coupled to a respective second sense amplifier. The data encoder is capable of encoding data according to a specific code to be stored in the first three-dimensional NAND gate memory array and the second three-dimensional NAND gate memory array. The search encoder is capable of (i) encoding a first search word to generate an encoded first search word encoded according to the specific code, (ii) encoding a second search word to generate an encoded second search word encoded according to the specific code, and (iii) applying the encoded first search word and the encoded second search word to the first three-dimensional NAND gate memory array and the second three-dimensional NAND gate memory array, respectively. The logic operation module is capable of performing one of a plurality of selectable logic operations. Wherein, the first three-dimensional NAND gate memory array is responsive to a first portion of the data stored therein and further responsive to the encoded first search word to generate a first sensing result using these respective sense amplifiers. Wherein, the second three-dimensional NAND gate memory array is responsive to a second portion of the data stored therein and further responsive to the encoded second search word to generate a second sensing result using these respective second sense amplifiers. Wherein, the logic operation module is capable of processing these first sensing results and these second sensing results according to one selected from these selectable logic operations. Other examples of this aspect include corresponding computer systems, devices, and computer programs recorded on one or more computer storage devices, each of which is configured to perform the actions of the method. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A , Figure 1B and Figure 1C (collectively, FIG. 1 ) collectively illustrate selected details of the implementation of a high-level architecture for searching within a 3D-NAND based memory;

[0014] Figure 2 An example of a word, character, base and digit showing a high-level architecture for searching within a 3D-NAND based memory;

[0015] Figure 3 An example of data storage for subsequent searching of a NAND array is shown;

[0016] Figure 4 Another example of data storage for subsequent searching of a NAND array is shown;

[0017] Figure 5 A technique for searching a word in a 3D-NAND array is shown;

[0018] Figure 6 A technique for searching for words in large data sets in multiple 3D-NAND arrays is shown;

[0019] Figure 7 A technique for searching long words in multiple 3D-NAND arrays is shown;

[0020] Figure 8 A technique for searching long words in multiple non-contiguous data segments in a single 3D-NAND array is shown;

[0021] Fig. 9 A technique for searching long words in multiple consecutive data segments in a single 3D-NAND array is shown;

[0022] Fig.10 A technique for searching short words or small data groups in a 3D-NAND array is shown;

[0023] Fig.11 A technique for searching multiple words in parallel in multiple 3D-NAND arrays is shown;

[0024] Fig. 12A and Fig. 12B (collectively, FIG. 12 ) collectively illustrate a technique for searching between multiple word groups in a single 3D-NAND array;

[0025] Fig.13 An example operational flow for searching a system within a 3D-NAND memory is shown;

[0026] Fig.14 The search within the memory is shown in the context of a memory string pair connected to a bit line (BL).

[0027] Fig.15A and Fig. 15B An example of an encoding technique using 2 threshold levels and providing a high current indication of a mismatch between search data and stored data is shown;

[0028] Fig.16A , Fig. 16B and Fig. 16C Together, an example of an encoding technique using eight threshold levels and providing a larger current indication for a mismatch between search data and stored data is shown;

[0029] Fig.17A and Fig. 17BTogether, an example of a p-level encoding technique using p threshold levels and providing a larger current indication of a mismatch between search data and stored data is shown;

[0030] Fig.18 An example of an encoding technique that uses analog levels and provides a larger current indication for a mismatch between search data and stored data is shown;

[0031] Fig.19A and Fig.19B An example of an encoding technique using 2 threshold levels and providing a small current as an indication of a mismatch between search data and stored data is shown;

[0032] Fig. 20A , Fig. 20B and Fig. 20C together illustrate an example of an encoding technique using eight threshold levels and providing a smaller current indication for a mismatch between search data and stored data; and

[0033] Fig.21A and Fig. 21B Together, examples of a p-level encoding technique are shown that uses p threshold levels and provides a small current indication for a mismatch between search data and stored data.

[0034] Description of Reference Numerals

[0035] 100: Three-dimensional NAND gate memory search system

[0036] 110: Data

[0037] 111: Encoded data

[0038] 120: Search

[0039] 130,135: Page buffer

[0040] 131, 132, 138, 139: Memory serial pair

[0041] 140: Encoding

[0042] 149: Serial unit in memory

[0043] 150,159: NAND gate array

[0044] 151: NAND gate array 1

[0045] 152: NAND gate array 2

[0046] 160: Data encoder

[0047] 170: Search encoder

[0048] 171: Serial selection line

[0049] 172,1888,1889: word line + word line'

[0050] 180,181,BL:Bit line

[0051] 182: Ground

[0052] 190: Results

[0053] 191: Result combination + sorting

[0054] 194-199: Two-dimensional memory array

[0055] 210,361,368,369,461,468,469,471,478,479,561,568,569: Characters

[0056] 212,311: Characters

[0057] 214: m-based coding example

[0058] 219: Example value

[0059] 310,410,510,610,1010,1110,1210: character input

[0060] 312: N numbers => N layers

[0061] 319: L characters

[0062] 330,431,432,530,631,632,731,732,831,832,931,932,1131,1132,1231,1232,1881,WL: word line

[0063] 540: Batch size

[0064] 621: Array 1

[0065] 622: Array 2

[0066] 641: Array 1 data

[0067] 642: Array 2 data

[0068] 710,810,910: long character input

[0069] 711,721,811,821,911,921: Segment 1

[0070] 712, 722, 812, 822, 912, 922: Segment 2

[0071] 741, 841, 941: Segment 1 data

[0072] 742,842,942: Segment 2 data

[0073] 1011, 1031: Part 1

[0074] 1012,1032:Part 2

[0075] 1041: Part 1 Data

[0076] 1042: Part 2 Data

[0077] 1111: Character group 1

[0078] 1112: Character group 2

[0079] 1121, 1221: Group 1

[0080] 1122,1222: Group 2

[0081] 1141, 1241: Group 1 data

[0082] 1142,1242: Group 2 data

[0083] 1199: Logical Operations

[0084] 1211: Character input 1

[0085] 1212: Character input 2

[0086] 1300: Search process

[0087] 1301-1306: Action

[0088] 1307: Provide results

[0089] 1480: Memory search unit

[0090] 1572, 1972: Memory Status LVT

[0091] 1573, 1973: Memory Status HVT

[0092] 1670~1677,1770~1776,2070~2077,21770~2176,Vt 0~Vt p: threshold level

[0093] 1878, 1879: Tunable Vt

[0094] 1882: Word Line'

[0095] 1883: Electricity

[0096] 1884: The Current

[0097] 1885, 1887: Mismatch

[0098] 1886: Match

[0099] CSL: Common Source Line

[0100] FG, FG': floating gate device

[0101] GSL: Ground Select Line

[0102] HVT: High Threshold Voltage

[0103] I1~I8, Ioff: total current

[0104] LVT: Low Threshold Voltage

[0105] SSL: Serial Select Line

[0106] V0~V8,Vp-3,Vp-2,Vp-1,Vp,Vp+1: Encoding voltage

[0107] VH: High Voltage

[0108] VL: Low voltage

[0109] Vt: threshold voltage

[0110] X, Y, Z: Dimensions DETAILED DESCRIPTION

[0111] Please refer to Figure 1A , Figure 1B , Figure 1C , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig. 12A , Fig. 12B , Fig.13 , Fig.14 , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig.18 , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A and Fig. 21B , which provides a detailed technical description of a high-level architecture for searching within 3D-NAND-based memories.

[0112] A high-level architecture for searching within a 3D-NAND-based memory provides a search for an application that receives lines and word lines for selecting a non-volatile 3D memory array. This architecture uses 2 word lines for each search information unit and 2 memory devices for each storage feature unit for searching. This architecture uses individual bit lines of a non-volatile 3D memory array as individual match lines for searching. Individual memory strings (e.g., NAND memory strings) of a non-volatile 3D memory array may be used to store, for example, individual data values ​​corresponding to elements to be searched. Respective multiple memory strings are coupled in parallel to respective shared bit lines. In addition to searches in application areas such as artificial intelligence (AI) and big data, this architecture is also applicable to comparison and classification.

[0113] The present disclosure describes one or more flow charts. The processing described in the flow chart can be implemented and / or managed (directable) using a processor, which is programmed using a computer program stored in a memory accessible by a computer system, and can be executed by a processor, using dedicated logic hardware (including field programmable integrated circuits), and using various combinations thereof. Various actions are combinable, can be performed in parallel, and / or can be performed in different orders without affecting the processing implemented. In some cases, the same result can be achieved by rearranging the operations only if certain other changes are made. In other cases, the same result can be achieved by rearranging the actions only if certain conditions are met. In addition, for clarity, some flow charts in this article omit certain actions that are not necessary for understanding the disclosed technology. Various additional actions can be performed before, after, and / or between the actions shown.

[0114] Examples of selected acronyms, mnemonics, and abbreviations used in the description are as follows.

[0115] (Acronyms, Mnemonics, and Abbreviations) Examples (2FeFET) 2 ferroelectric field effect transistor (2T0C (DRAM-like device)) 2 transistors 0 capacitors (2T2R) 2 transistors 2 capacitors (AI) Artificial Intelligence (BL) Bit Line (CSL) Common Source Line (DNA) deoxyribonucleic acid (DRAM) Dynamic Random Access Read / Write Memory (FeFET) Ferroelectric Field Effect Transistor (GSL) Ground Select Line (IMS) In-Memory Search (NAND) Not AND, for example, devices are connected in series to form a memory string (NVM) Non-volatile Memory (SONOS (memory)) Silicide-Oxide-Nitride-Oxide-Silicide (memory) (SRAM) Static Random Access Read / Write Memory (SSD) Solid State Drive (SSL) Serial Select Line (TCAM) Ternary Content Addressable Memory (WL) Word Line

[0116] An example of a search criterion is a collection of information indicating what to search for and how to perform the search. The search criterion includes any combination of a search value and one or more instructions on how to perform the search. The instructions on how to perform the search include the length of the search word, the number of numbers in the search word, which and / or how many NAND arrays to search, which logical operation (if any) to use to combine search results from more than one NAND array, whether to perform the search in series or in parallel, how to slice long words, how to segment long words, how to group parts of words, etc., as applicable to Figure 5 , Figure 6, Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig. 12A and Fig. 12B Any one or more of .

[0117] An example of a search value is a search word containing one or more characters. An example of a data value (such as can be stored in a NAND array or can be searched in a NAND array) is a data word containing one or more characters. Each character (of the search word or data word) contains one or more digits. Each digit can represent multiple mutually exclusive states. Mutually exclusive states are based on the radix of the digit representation, such as base 2 for binary digits (bits), or base 8 for octal numbers.

[0118] An example of a memory string is a plurality of memory devices connected in series. An example of a memory device is an element capable of storing information indicating one of at least two mutually exclusive states of the memory device. These states can be set by programming the memory device and can be read by activating a control input of the memory device. In several types of memory devices (e.g., floating gate memory devices), programming is by configuring the threshold voltage of the memory device and the control input is a control gate input. Configuration is also referred to as programming the memory device (e.g., programming to 1 or 0, or some other value), and is also referred to as storing a value (e.g., 1 or 0, or some other value).

[0119] A three-dimensional (3D) memory array is comprised of a plurality of two-dimensional (2D) memory arrays. Each 2D memory array is comprised of a plurality of memory string pairs. Each memory string is comprised of non-volatile memory elements having source / drain connections in series, each non-volatile memory element having a corresponding control gate input. The control gate input is connected to a corresponding word line, and operates in pairs according to the memory string pairs and the individual device pairs therein. Each string also includes a string selection device source / drain connected in series to the non-volatile memory device. The string selection device has a gate input connected to the string selection control input. Each string further includes one or more source / drain series connected control devices having individual gates and associated control inputs.

[0120] Concept of searching within 3D-NAND memory.

[0121] The present disclosure provides a novel high-level architecture for searching within 3D-NAND-based memories, which can be implemented using 3D search memories (e.g., 3D-NAND memories) that can be efficiently searched, compared, and / or classified, such as those associated with big data and / or artificial intelligence processing. This architecture provides low latency, high resolution, high content density, multi-block functionality, and strong reliability. This architecture is suitable for big data search, AI hardware accelerators and / or classifiers, approximate computing, associative storage, small sample learning, SSD data management, DNA matching, data filtering, hyperdimensional computing, and other applications that benefit from in-memory search to achieve long search terms and large data capacity.

[0122] The host agent directs the storage of data in the 3D search memory. In response, the 3D search memory stores the data. The host agent then provides a search to the 3D search memory. In response, the 3D search memory processes the search by determining zero or more matches within the stored data according to the search.

[0123] The control agent of the 3D search memory receives data for storage from the host agent and, in response, directs the 3D search memory to configure the included memory device to store the data (e.g., via the included programming circuitry). The control agent receives the search and, in response, directs the search of one or more 2D memory resources of the 3D search memory to provide search results (e.g., match indications) to the host agent based on the search.

[0124] Techniques associated with a high-level architecture for searching within a 3D-NAND based memory enable efficient searching of a 3D search memory for matches to data stored in the 3D search memory based on search criteria, such as any combination of search values ​​and one or more instructions on how to perform the search.

[0125] For example, a 3D memory array is implemented using NVM technology, such as composed of floating gate programmable memory devices. The three dimensions of the 3D memory array are referred to herein as X, Y, and Z. One or more 3D search memories and / or 3D memory array instances may be implemented as all or any portion of an integrated circuit fabricated from wafer material using planar processing techniques. Processing techniques. The X and Y dimensions correspond to horizontal planes of planar processing. The Z dimension corresponds to a vertical dimension of planar processing, such as vertically stacked layers of material.

[0126] The 3D memory array is composed of multiple 2D memory arrays. Each 2D memory array is composed of multiple memory string pairs. Each memory string is composed of non-volatile memory devices with source / drain connected in series, and each non-volatile memory device has a separate control gate input. The control gate input is connected to a separate word line and operates in pairs according to the memory string pairs and the separate device pairs therein. Each string also includes a string selection device source / drain connected in series to the non-volatile memory. The string selection device has a gate input connected to the string selection control input. Each string further includes one or more source / drain control devices (with separate gates and associated control inputs) connected in series.

[0127] The search criteria include a search value and one or more instructions on how to perform the search. The search value is what to search for in the 3D search memory. The search value has a length, such as measured in characters (sometimes called numbers). These numbers are based on a number representation base, such as base 2 for binary digits (bits) or base 8 for octal numbers.

[0128] The encoding of the search input and data value is based on how the circuit determines a match (mismatch), such as via a large / larger or small / smaller current. For example, a portion of the page buffer (e.g., a sense amplifier) ​​determines that a match is indicated by a larger current than a mismatch. For another example, a page buffer determines that a match is indicated by a smaller current than a mismatch.

[0129] The encoding of the search input and data values ​​is further based on a unique representation of each number. Each unique representation corresponds to a level. The encoding can be implemented in 2 levels, 8 levels, p levels (multi-level) and similar techniques.

[0130] Techniques associated with a high-level architecture for searching within 3D-NAND based memories enable high-speed searching for long word data matches from a large number of stored values.

[0131] In some use cases, the read latency of a 3D search memory is reduced by operating multiple blocks simultaneously (at the potential expense of relatively large current transients). Simultaneous operation is performed by switching multiple enable controls, such as string select lines (SSL).

[0132] Example implementation of search in 3D-NAND memory

[0133] Figure 1A , Figure 1B and Figure 1C (collectively, FIG. 1 ) collectively illustrate selected details of the implementation of a high-level architecture for searching within a 3D-NAND based memory.

[0134] Figure 1AAn example implementation of a high-level architecture of a 3D-NAND based intra-memory search, such as a 3D-NAND intra-memory search system 100 is shown.

[0135] The 3D-NAND in-memory search system 100 is implemented in three dimensions (X, Y, and Z) and includes encoding, storage / search, and output resources. The encoding resource includes a data encoder 160 (e.g., a data encoding circuit) that is capable of receiving data 110 and providing encoded data 111 (e.g., programming data) to the storage / search resource in response. The encoding resource also includes a search encoder 170 that is capable of receiving a search 120 and providing a string select line (illustrated as a string select line (SSL) 171) and a pair of WLs (illustrated as word line + word line ') 172) to the storage / search resource in response to the search engine. The encoding performed by the encoding resource is based on a specific encoding technique, as shown in the dashed box encoding 140. The storage / search resource includes a NAND array 150, which in turn includes multiple 2D memory array instances, one of which is specifically identified as a 2D memory array (2D) 199. The output resources include page buffers 130 (which include, for example, sense amplifiers) capable of receiving bit line information (illustrated as a plurality of bit lines (BL) 180) from each 2D memory array of the NAND array 150. The output resources also include result combining + sequencing 191, which provides search results as results 190. The 3D-NAND in-memory search system 100 optionally further includes additional NAND arrays, illustrated as (multiple) NAND arrays 159 and corresponding page buffers, illustrated as (multiple) page buffers 135.

[0136] The 3D-NAND memory search system 100 can be implemented in a variety of ways, such as on a single integrated circuit chip, on multiple integrated circuits, or as a component of a system-on-a-chip (SOC). As a specific example, the 3D-NAND memory search system 100 is implemented on a single integrated circuit chip, so that the search and combinatorial logic operations can be performed entirely within the single integrated circuit chip.

[0137] For clarity, this figure omits selected details related to programming the programmable memory devices of the 2D memory array.

[0138] In some examples, the search encoder 170 (including, for example, a search encoding circuit), the bit line (BL) 180 and / or the result combination + sorting 191 can sort the layers, such as switching the search from the first layer to the second layer and / or the seventh layer, and so on.

[0139] Figure 1B Selected details of an example of a 2D memory array, such as a two-dimensional (2D) memory array 199, are shown.

[0140] 2D memory array (2D) 199 includes 256 memory string pairs. For clarity, this figure explicitly shows 4 pairs, namely memory string pairs 131, 132, 138 and 139. Each memory string pair includes a series of device strings connected between a bit line (BL) 181 and a ground 182. Each series of device strings includes a plurality of source / drain series-connected non-volatile memory devices, for a total of 256 devices. Each non-volatile memory element has a respective control gate input connected to a respective WL. As a specific example shown in the figure, memory string pair 131 includes 256 non-volatile memory devices in the left memory string of the memory string pair and 256 non-volatile memory devices in the right memory string of the memory string pair. For clarity, a subset of the devices is explicitly shown.

[0141] The control gate inputs of the non-volatile memory devices of the left memory string of the memory string pair 131 are connected to word lines (WL) WL1_1 . . . WL1_256, respectively.

[0142] Similarly, the control gate inputs of the nonvolatile memory devices of the right memory string of the memory string pair 131 are connected to word lines WL1_1′..WL1_256′, respectively. Note that the prime (′) is pronounced “prime” and indicates the relationship between a pair of WLs, e.g., WL1_1 and WL1_1′ are associated with respective memory devices coupled to the same memory cell.

[0143] Note that WL is identified by two integer character numbers (CharacterNumber) and layer numbers (LayerNumber) and an optional prime suffix: WL<CharacterNumber><LayerNumber>[′]. For example, WL1_8 corresponds to character 1 (e.g., of a stored data word) and layer 8 (of NAND array 150). Layer 8 of NAND array 150 corresponds to one or more material stacking layers formed in the vertical (e.g., Z) dimension due to planar processing of the integrated circuit, which is inserted between layers 7 and 9 of NAND array 150. Therefore, layer 8 of NAND array 150 corresponds to one or more planar processing layers of the integrated circuit. The lack of a prime suffix indicates the left string of the memory string pair. For another example, WL1_8′ corresponds to character 1 and layer 8, which is the same as WL1_8. The prime suffix indicates the right string of the memory string pair.

[0144] As described in more detail elsewhere herein, the non-volatile memory devices of the left and right memory strings are used in pairs according to a particular encoding technique (e.g., encoding 140 of FIG. 1 ) to perform matching for a search operation. An example of one of the non-volatile memory device pairs is shown as an In Memory String cell (IMS) 149. The control gate of the left non-volatile device of the pair is connected to WL1_249, and the control gate of the right non-volatile device is connected to WL1_249'.

[0145] Each series string of devices also includes a string select device having source / drain serial connections to the nonvolatile memory. The string select device has a gate input connected to a string select control input (e.g., SSL_1 for the left memory string of the memory string pair 131 and SSL_2 for the right memory string of the memory string pair 131). The string select line pair of each memory string pair (e.g., SSL_1 and SSL_2) can be operated as a pair (e.g., corresponding to a search operation) to enable (disable) the left memory string and the right memory string of the memory string pair together.

[0146] Each series string of devices also includes a ground selection device having a source / drain connected in series to the non-volatile memory device. The ground selection device has a gate input connected to a ground selection control input (e.g., GSL_1 for the left memory string of the memory string pair 131 and GSL_2 for the right memory string of the memory string pair 131). The ground selection line pair of each memory string pair (e.g., GSL_1 and GSL_2) can be operated as a pair (e.g., corresponding to a search operation) to enable (disable) the left memory string and the right memory string of the memory string pair together.

[0147] Each series of device strings also includes a common select device whose source / drain is connected in series to the nonvolatile memory. The common select device has a gate input connected to a common select control input (e.g., CSL_1 for the left memory string of the memory string pair 131 and CSL_2 for the right memory string of the memory string pair 131). The common select line pair of each memory string pair (e.g., CSL_1 and CSL_2) can be operated as a pair (e.g., corresponding to a search operation) to enable (disable) the left and right memory strings of the memory together.

[0148] Each element of the string select line pair (e.g., SSL_1 and SSL_2) of each memory string pair can be operated independently (e.g., in response to operations other than search operations, such as erase and / or program operations). For example, SSL_1 can be operated independently of SSL2 to enable programming of devices in the left memory string of the memory string pair 131. Similarly, each element of the pair of ground select lines and common select lines can be operated independently and / or independently of another element of the pair.

[0149] This figure illustratively depicts a 2D memory array (2D) 199 as having 256 memory string pairs, each memory string pair having 256 series-connected nonvolatile memory devices. Other examples have other numbers of memory string pairs and / or other numbers of series-connected nonvolatile memory devices.

[0150] Figure 1C Selected details of a NAND array, such as NAND array 150, are shown.

[0151] This figure shows several representative examples of 2D memory arrays of NAND array 150, and in particular 2D memory arrays (2D) 194-199. This figure also illustrates several representative interconnections of the gates of the devices of the 2D memory array. Specifically, all gates of the devices at a particular X, Y position of each 2D memory array are connected in parallel. This figure shows representative parallel connections of serial select lines SSL_1, SSL_2, SSL511, and SSL512; representative parallel connections of word line (WL) pairs WL1_8 and WL1_8′, word line pairs WL256_8 and WL256_8′; and representative parallel connections of common select lines CSL_1, CSL_2, CSL511, and CSL512.

[0152] Thus, in an example having a 2D memory array of 128K, each string select line is connected to a 128K gate, each WL in each pair of WLs is connected to a 128K gate, etc. Other examples have other numbers of 2D memory arrays.

[0153] Searching for data storage in 3D-NAND memory

[0154] Figure 2 An example of a high-level architecture for searching within a 3D-NAND based memory is shown for words, characters, bases, and digits in the contents of a 2D memory array (2D) 199 of the NAND array 150 of FIG. 1 .

[0155] Depending on the selected encoding (e.g., as determined by Figure 1A 140), storing data (e.g., in part via Figure 1A 160) and perform a search (e.g., in part via Figure 1A The data and search are represented as a word. An example of a word is Figure 2 The character (L-character) 210 has L characters (1, 2, 3, 4...L-2, L-1 and L). Each character can be interpreted as a plurality of digits, an example of which is a character (nv digit) 212 with n digits (1, 2...n-1 and n). Each digit can also optionally represent one of a plurality of mutually exclusive codes, an example of which is an m-based coding example 214.

[0156] A word line (WL) driver (e.g., word line (WL+WL') 172 of FIG. 1) drives a WL pair based on each digit according to a selected encoding (e.g., as shown in encoding 140 of FIG. 1). Thus, the WL driver drives WL2_1 and WL2_1' based on the first digit of the second character, and drives WL2_2 and WL2_2' based on the second digit of the second character.

[0157] Figure 2 The example encoding is shown as an m-based encoding example 214. Example m-based encoding examples include 2-based (e.g., binary) encodings that can represent 0 and 1 values, and 2-based encodings that can represent Don't Care X in addition to 0 and 1 values. Example m-based encodings also include 8-based (e.g., octal) encodings that can represent 0, 1, 2...6, and 7.

[0158] Figure 2 An example according to m-based encoding is shown as example value 219.

[0159] Depending on the usage scenario and implementation, the character set has, for example, from 1 to 256 characters.

[0160] Figure 3 An example of data storage for subsequent searching of a NAND array is shown. The illustrative context is a NAND array having bit lines (BL) 180 and page buffers 130 (all Figure 1A ) of the NAND array 150.

[0161] The host agent provides a search word as a word input (Word In) 310 (e.g., via search 120 of FIG. 1 as a search value for search criteria) having a plurality of characters, namely L characters 319. This figure shows one of the characters as character 311, and sequentially shows the characters having numbers illustrated as N numbers => N layers 312 to the layers of the NAND array 150. The WL driver drives the WLs encoded according to the selected encoding, conceptually shown as word lines (WL) 330.

[0162] In the example shown, there are 5 digits in each word. Therefore, each corresponding stored data word of NAND array 150 is stored using 5 layers, as shown as each of word 361, word 368, and word 369. This figure shows each stored word stored in a corresponding 2D array having a common coupling (bit line (BL) 180) to a respective BL of page buffer 130.

[0163] Each digit of each character of the character input 310 is encoded into a separate WL pair according to the selected encoding (e.g. Figure 2 shown).

[0164] Figure 4 Another example of subsequently searching the data storage of a NAND array is shown. Figure 3 , the contents are shown as a NAND array 150 having a bit line (BL) 180 and a page buffer 130 ( Figure 1A all). Figure 4 Shows stored data in multiple sets of layers, rather than Figure 3 All data is stored in a single set of layers as shown in FIG. The first set of layers is shown for use with characters 461, 468, and 469. The second set of layers is shown for use with characters 471, 478, and 479. Parallel searches can be performed on the first and second sets of layers.

[0165] The host agent provides a search word as word input 410 (eg, as a search value for search criteria via search 120 of FIG. 1 ). The WL driver drives WLs encoded according to the selected encoding, conceptually shown as wordline (WL) 431 and wordline (WL) 432 .

[0166] Each digit of each character of the character input 310 is encoded into a respective WL pair according to the selected encoding (e.g. Figure 2 shown).

[0167] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig. 12A and Fig. 12B Various techniques for searching one or more words in one or more 3D-NAND arrays are shown. Like numbered elements in these figures are the same, substantially similar, similar, or variations thereof relative to the elements of FIG. 1 . In these figures, the operations are as described in and with respect to FIG. 1 .

[0168] Furthermore, in these figures, the operation begins with the host agent performing the encoding according to the selected encoding technique (e.g. Figure 2Any of the techniques outlined in Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18 , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A and Fig. 21B Each encoding technique uses a memory string pair for each character in the search word. Storing includes programming the floating gate programmable memory device by setting the threshold voltage (Vt) according to the selected encoding technique. The stored value can then be used for searching.

[0169] Searching for characters in 3D-NAND memory

[0170] Figure 5 A technique for searching a word in a 3D-NAND array is shown. The NAND array 150 includes multiple 2D arrays, two of which are specifically labeled (2D memory array 199 and 2D memory array 194).

[0171] In preparation for the search, the host agent has already stored data values ​​in NAND array 150 (including in words 561, 568, and 569) according to the selected encoding technique.

[0172] The host agent then requests a search and provides corresponding search criteria. The search criteria include a search value, which is a search word provided via word input 510. The search criteria also include one or more instructions. For example, an instruction for the length of the search word (e.g., the number of characters is equal to how many memory string pairs are connected to each BL), an instruction that each character of the search word has five digits, and an instruction that a single 3D-NAND array is to be searched. A control agent (not shown) operating according to the instructions of the search criteria instructs the encoding of the value of word input 510 and the driving (e.g., as a bias) to the word lines of the array, such as the conceptually illustrated word lines (WL) 530, which conceptually indicate the characteristics of the array. In the specific example shown, each character of the word has 5 digits, so 5 layers of the NAND array 150 are enabled for searching. The enabled layers correspond to the batch size (Batch Size) 540.

[0173] As in other search operations, the control agent instructs the page buffer 130 to sense the bit line (BL) 180 (using the included sense amplifier) ​​and provide a sense result corresponding to evaluating how the word input 510 (e.g., represented as a bias value) matches the stored value (e.g., represented by a Vt value) and the result combination + ranking 191 (of FIG. 1 , not shown here). Figure 5 In the technique, result combination + sorting 191 operates to directly provide the sensing results as (search) results 190 without combining or sorting.

[0174] In a variation of the illustrated operation, a larger batch size is searched by searching more layers. In other variations of the illustrated operation, different layers are searched, such as intermediate layers, discontinuous layers, and so on.

[0175] Unused layers (if any, e.g., because the data set has fewer values ​​than the layers) are operated to be effectively ignored with respect to matching. A passing voltage (e.g., Vpass) is applied to the word lines of the unused layers, a wildcard encoding is applied to the control gates of the memory string pairs in the unused layers, and / or the memory devices of the memory string pairs in the unused layers are programmed to store a Don't Care value.

[0176] Unused memory string pairs (if any, e.g., because the data group has fewer characters than memory string pairs in the 2D array) are operated to be effectively ignored with respect to matching. Wildcard encoding is applied to the control gates of the unused memory string pairs and / or the memory devices of the unused memory string pairs are programmed to store don't care values.

[0177] Unused 2D arrays (if any, e.g., because the data set has fewer values ​​than the 2D array) are operated to be effectively ignored in terms of matching. For the first case, an SSL driver circuit (not shown) selectively enables SSLs corresponding to 2D arrays used by the search, and selectively disables SSLs corresponding to 2D arrays not used by the search (e.g., fewer data values ​​than the 2D array). For the second case, sense amplifiers associated with unused 2D arrays are not enabled. For the third example, sense amplifiers associated with unused 2D arrays are ignored by page buffer 130.

[0178] Any one or more of the foregoing techniques for unused layers, unused memory rank pairs, and unused 2D arrays may be used alone or in any combination.

[0179] 3D-NAND memory search scaling (Scaling) - large data sets / multiple 3D arrays

[0180] Figure 6 A technique for searching for words in a large data set in multiple 3D-NAND arrays is shown. The search is similar to the above except that multiple 3D-NAND arrays are searched to enable processing of large data sets. Figure 5 A control agent (e.g., result combination + sorting 191 of FIG. 1 ) instructs a search of multiple 3D-NAND arrays, either one after the other (e.g., serially), or two 3D-NAND arrays at a time (e.g., in parallel), and instructs subsequent search results to be merged. NAND array (NAND) 1151 and NAND array 2152 correspond to respective NAND array instances of NAND array 159 of FIG. 1 . For sensing, the BL of NAND array 1151 is coupled to a first page buffer instance of page buffer 135 of FIG. 1 . Similarly, the BL of NAND array 2152 is coupled to a second page buffer instance of page buffer 135 of FIG. 1 .

[0181] In preparation for the search, the host agent has stored the data values ​​in NAND array 1 151 and NAND array 2 152. The storage is based on the selected encoding technique. The storage is also based on storing the first portion of the data to be searched in NAND array 1 151 as array 1 data 641, and further based on storing the second portion of the data to be searched in NAND array 2 152 as array 2 data 642.

[0182] The host agent then requests a search and provides corresponding search criteria. The search criteria include a search value, which is a search word provided via word input 610. The search criteria also include one or more instructions. For example, an instruction for the length of the search word (e.g., the number of characters is equal to how many memory string pairs are connected to each BL), an instruction for each character of the search word to have five digits, and an instruction for two 3D-NAND arrays for the search word to be searched. The control agent (not shown) operating according to the instructions of the search criteria indicates the encoding of the value of word input 610 according to the selected encoding technique (e.g., via the search encoder 170 of Figure 1) and the driving of the word lines to the array (e.g., as a bias), as conceptually shown by word lines 631 and word lines 632. In the specific example shown, each character of the word has 5 digits, and therefore five layers of NAND array 1 151 (NAND array 2 152) are enabled for searching. The enabled layer corresponds to array 1 data 641 (array 2 data 642).

[0183] As in other search operations, the control agent instructs the page buffer to sense the searched bit lines of the array (using included sense amplifiers) and provide sense results corresponding to an evaluation of how the word input 610 matches relative to the stored value.

[0184] Two variations of operation with respect to NAND array 1 151 and NAND array 2 152 are (1) a serial technique and (2) a parallel technique. Optionally, the search criteria include an indication to perform the search using a serial technique or a parallel technique. Depending on hardware capabilities, the example system can perform the serial technique, the parallel technique, or both in various ways.

[0185] In the sequence technique, in a first portion of the operation, the control agent directs the application of word input 610 to NAND array 1151 via array 1 621 and word line (WL) 631. The first page buffer instance provides a first sense result for result combination + sort 191. Then, in a second portion of the operation, the control agent directs the application of word input 610 to NAND array 2 152 via array 2 622 and word line (WL) 632. The second page buffer instance provides a second sense result for result combination + sort 191. Result combination + sort 191 is an example of a control agent controlling sorting associated with the first and second portions of the operation. Result combination + sort 191 combines the first and second sense results to form an overall search result across array 1 data 641 and array 2 data 642 to provide as result 190.

[0186] In the parallel technique, the control agent directs the application of word input 610 to NAND array 1 151 (as in the first portion of the operation of the sequential technique), and in parallel directs the application of word input 610 to NAND array 2 152 (as in the second portion of the operation of the sequential technique). Result combination + sorting 191 is an example of a control agent that controls sorting associated with the parallel application of word input 610 to NAND array 1 151 and word input 610 to NAND array 2 152. Result combination + sorting 191 combines the sensing results from the first and second page buffer instances to form an overall search result across array 1 data 641 and array 2 data 642 to provide as result 190.

[0187] Conceptually, parallel techniques can produce twice as many search results per unit time as sequential techniques.

[0188] Figure 6Represents performing two searches (via either a sequential technique or a parallel technique) in a 3D-NAND memory array (NAND array 1 151 and NAND array 2 152 are collectively referred to). A first array (e.g., array 1 data 641) is stored in a first portion of the 3D-NAND memory array. A second array data (e.g., array 2 data 642) is stored in a second portion of the 3D-NAND memory array. The first of the two searches (corresponding to array 1 621) is performed using the respective BLs and WLs corresponding to the first portion of the 3D-NAND memory array. The second of the two searches (corresponding to array 2 622) is performed using the respective BLs and WLs corresponding to the second portion of the 3D-NAND memory array. The WLs of the first portion of the 3D-NAND array (e.g., the WLs coupled to array 1 data 641 stored in NAND array 1 151) are separated from the WLs of the second portion of the 3D-NAND array (e.g., the WLs coupled to array 2 data 642 stored in NAND array 2 152).

[0189] Unused layers, unused memory column pairs, and / or unused 2D arrays are manipulated to be effectively ignored with respect to matching, as described with respect to Figure 5 as described.

[0190] 3D-NAND memory search scaling (Scaling) - long word / multiple 3D arrays

[0191] Various techniques enable searching for long words (e.g., words with more than L characters). In one technique, the system can search for long words in multiple 3D-NAND arrays. In another technique, the system can search for long words in multiple non-contiguous data segments in a single 3D-NAND array. In yet another technique, the system can search for long words in multiple contiguous data segments in a single 3D-NAND array.

[0192] Figure 7 A technique for searching long words in multiple 3D-NAND arrays is shown. This search is similar to Figure 5 , except that the control agent (e.g., result combination + sorting 191 of FIG. 1 ) instructs searching multiple 3D-NAND arrays to enable processing of long words. The control agent instructs processing of long words into multiple segments, each segment corresponding to a respective one of the multiple 3D-NAND arrays. Similar to Figure 6 , the control agent instructs to search multiple 3D-NAND arrays one by one (e.g., sequentially) or simultaneously (e.g., in parallel). Figure 6 1, NAND array 1151 and NAND array 2152 correspond to respective NAND array instances of NAND array 159 of FIG. 1. Figure 61 , a first instance (not shown) of page buffer 135 senses NAND array 1151 , and a second instance (not shown) of page buffer 135 senses NAND array 2152 .

[0193] and Figure 6 Similarly, in preparation for the search, the host agent has stored data values ​​in NAND array 1151 and NAND array 2152. This storage is based on the selected encoding technique. This storage is also based on storing the first segment of the data to be searched in NAND array 1151 as segment 1 data 741, and further based on storing the second segment of the data to be searched in NAND array 2152 as segment 2 data 742.

[0194] The host agent then requests a search and provides corresponding search criteria. The search criteria include a search value, which is a search word provided via Long Word In 710. The search criteria also include one or more instructions. For example, an instruction for the length of the search word (e.g., the number of characters is equal to how many memory string pairs are connected to each BL), an instruction for each character of the search word to have five digits, and an instruction for individual segments of the search word of the two 3D-NAND arrays to be searched. Similar to Figure 6 , a control agent (not shown) operating in accordance with the instructions of the search criteria instructs the value of the long word input 710 to be encoded according to the selected encoding technique (e.g., via the search encoder 170 of FIG. 1 ) and driven onto the WL of the array (e.g., as a bias voltage), as conceptually indicated by word line (WL) 731 and word line (WL) 732. In the specific example shown, each character of the word has five digits, and therefore, five layers of NAND array 1 151 (NAND array 2 152) are enabled for search. The enabled layer corresponds to segment 1 data 741 (segment 2 data 742).

[0195] As with other search operations, the control agent instructs the page buffer to sense the BL of the searched array (using included sense amplifiers) and provide a sense result corresponding to an evaluation of how the long word input 710 matches relative to the stored value.

[0196] like Figure 6 As shown, NAND array 1 151 and NAND array 2 152 may be operated differently in sequence or in parallel. Optionally, the search criteria include instructions to perform the search using a sequential technique or a parallel technique. Depending on the hardware capabilities, the example system can perform the sequential technique, the parallel technique, or both in various ways.

[0197] and Figure 6Similarly, in the sequence technique, the control agent instructs in a first portion of the operation that segment 1 711 of the long word input 710 be applied to NAND array 1 151 via segment 1 721 and word line (WL) 731. The first page buffer instance provides a first sensing result to result combination + sorting 191. Then, the control agent instructs in a second portion of the operation that segment 2 712 of the long word input 710 be applied to NAND array 2 152 via segment 2 722 and word line (WL) 732. The second page buffer instance provides a second sensing result to result combination + sorting 191. Result combination + sorting 191 is an example of a control agent controlling sorting associated with the first and second portions of the operation. Result combination + sorting 191 combines the first and second sensing results to form an overall search result across segment 1 data 741 and segment 2 data 742 to provide as result 190.

[0198] and Figure 6 Similarly, in the parallel technique, the control agent directs that segment 1 711 of the long word input 710 be applied to NAND array 1 151 (as in the first portion of the operation of the sequential technique) and segment 2 712 of the long word input 710 be applied to NAND array 2 152 in parallel (as in the second portion of the operation of the sequential technique). Result combination + sorting 191 is an example of a control agent controlling sorting associated with applying segment 1 711 of the long word input 710 in parallel to NAND array 1 151 and segment 2 712 of the long word input 710 in parallel to NAND array 2 152. Result combination + sorting 191 combines the sensing results from the first and second page buffer instances to form an overall search result across segment 1 data 741 and segment 2 data 742 to provide as result 190.

[0199] Conceptually, parallel techniques can produce twice as many search results per unit time as sequential techniques.

[0200] similar Figure 6 , Figure 7Represents performing two searches (via either a sequential technique or a parallel technique) in a 3D-NAND memory array (NAND array 1 151 and NAND array 2 152 are collectively referred to). A first data segment (e.g., segment 1 data 741) is stored in a first portion of the 3D-NAND memory array. A second data segment (e.g., segment 2 data 742) is stored in a second portion of the 3D-NAND memory array. The first of the two searches (corresponding to segment 1 721) is performed using respective BLs and WLs corresponding to the first portion of the 3D-NAND memory array. The second of the two searches (corresponding to segment 2 722) is performed using respective BLs and WLs corresponding to the second portion of the 3D-NAND memory array. The word lines of the first portion of the 3D-NAND array (e.g., word lines coupled to segment 1 data 741 stored in NAND array 1 151) are separated from the word lines of the second portion of the 3D-NAND array (e.g., word lines coupled to segment 2 data 742 stored in NAND array 2 152).

[0201] Unused layers, unused memory column pairs, and / or unused 2D arrays are manipulated to be effectively ignored with respect to matching, as described with respect to Figure 5 as described.

[0202] 3D-NAND memory search scale (Scaling) - long word / single 3D array

[0203] Figure 8 A technique for searching for long words in multiple non-contiguous data segments in a single 3D-NAND array is shown. This search is similar to Figure 7 The difference is that multiple non-contiguous data segments are stored in a single 3D-NAND array instead of multiple 3D-NAND arrays. Each non-contiguous data segment is stored in a corresponding layer group in the 3D-NAND array. Figure 7 As shown, the processing is based on either a sequential technique or a parallel technique. In summary, the long word input 810 is processed serially as segment 1 811, then segment 2 812. Segment 1 811 is applied to segment 1 data 841 via segment 1 821 and word line (WL) 831. Then, segment 2 812 is applied to segment 2 data 842 via segment 2 822 and word line 832. Result combination + sorting 191 controls sorting (whether sequential or parallel) and combines the sensing results determined from NAND array 1 151 and NAND array 2 152 to produce an overall search result, such as result 190.

[0204] For example, the search criteria include instructions for the search word length (e.g., the number of characters is equal to how many memory string pairs each BL is connected to), instructions for each character of the search word to have five digits, instructions for searching a single NAND array in two segments corresponding to respective segments of a long search word provided via long word input 810, instructions for describing the starting positions of (non-contiguous) respective segments in a single 3D-NAND array, and optionally instructions for performing the search using either a sequential technique or a parallel technique.

[0205] Unused layers, unused memory column pairs, and / or unused 2D arrays are manipulated to be effectively ignored with respect to matching, as described with respect to Figure 5 as described.

[0206] Fig. 9 A technique for searching for long words in multiple consecutive data segments in a single 3D-NAND array is shown. This search is similar to Figure 8 The search is similar to that of the previous one, except that multiple consecutive data segments are stored in a single 3D-NAND array instead of multiple non-consecutive data segments stored in a single 3D-NAND array. Each consecutive data segment is stored in a corresponding layer group in the 3D-NAND array. Figure 8 As shown, the processing is based on either a sequential technique or a parallel technique. In summary, the long word input 910 is processed into segment 1 911 and segment 2 912. Segment 1 911 is applied to segment 1 data 941 via segment 1 921 and word line (WL) 931. Segment 2 912 is applied to segment 2 data 942 via segment 2 922 and word line (WL) 932. Result combination + sorting 191 controls sorting (whether sequential or parallel) and combines the sensing results determined from NAND array 1 151 and NAND array 2 152 to produce an overall search result, such as result 190.

[0207] For example, the search criteria include instructions for the search word length (e.g., a number of characters equal to twice the number of memory string pairs connected to each BL), instructions for each character of the search word to have five digits, instructions for searching a single 3D-NAND array in two segments corresponding to respective segments of a long search word provided via the long word input 810, instructions for describing the starting positions of (non-contiguous) respective segments in the single 3D-NAND array, and optionally instructions for performing the search using either a sequential technique or a parallel technique.

[0208] For each Figure 7 , Figure 8 and Fig. 9As shown, each word of each segment has any appropriate number of characters. Assume that a word has L characters. For the first example, consider a long word with 2*L characters. Therefore, the words of each segment are L characters. For the second example, consider a long word with L+1 characters. The words of the first segment and the words of the second segment are any number of characters totaling L+1.

[0209] Unused layers, unused memory column pairs, and / or unused 2D arrays are manipulated to be effectively ignored with respect to matching, as described with respect to Figure 5 as described.

[0210] 3D-NAND memory search scale (Scaling) - short words or small data groups

[0211] Fig.10 A technique for searching for short words or searching in small data groups in a 3D-NAND array is shown. Assume that there are L memory string pairs connected to each BL. An example of a short word is a word with less than L characters. Therefore, if the total number of characters in the first short word and the second short word is less than L, the first short word and the second short word are searchable within the same set of 2D arrays. An example of a small data group is a data group with data values, and the number of characters for each data value is less than L. Therefore, if the total number of characters in each word of the first small data group and the second small data group is less than L, the first small data group and the second small data group are searchable within the same set of 2D arrays.

[0212] In addition to storing multiple data portions in a single 3D-NAND array, this search and Figure 8 The search is similar to that of . Each data portion is stored in a corresponding set of memory string pairs in the 3D-NAND array, so that these portions share the BL. The processing is based on a single small word or multiple small words in parallel at a time and an implicit logical AND operation between the search results of each small word.

[0213] For the first example, a single small word of the two small words is processed separately, and the unused memory string pair corresponding to the unpressed one of the two small words is disabled by disabling the corresponding SSL (eg, by applying 0 volts to the corresponding SSL). The sensing result corresponds to the single small word.

[0214] For the second example, two small words are processed together, and the memory string pairs corresponding to the two small words are enabled by activating the corresponding SSLs (e.g., by applying a high voltage to the corresponding SSLs). The sensing result corresponds to the logical AND of the sensing result of the first small word and the sensing result of the second small word.

[0215] In summary, word input 1010 is processed into part 1 1011 and part 2 1012. Part 1 1011 is applied to part 1 data 1041 via part 1 1031 of word line (WL) 1030. Part 2 1012 is applied to part 2 data 1042 via part 21032 of word line (WL) 1030. Result combination + sorting 191 controls the sorting (whether sequential or parallel) and combines the sensing results determined from NAND array 1 151 and NAND array 2 152 to produce an overall search result, such as result 190.

[0216] For example, the search criteria include instructions for the length of a search word (e.g., a number of characters equal to how many memory string pairs are connected to each BL), instructions for a portion of the length of a search word (e.g., a portion of the search word length, such as measured in characters), instructions for each character of the search word to have five digits, instructions for searching a single 3D-NAND array in two portions corresponding to respective portions of the search word provided via word input 1010, instructions for describing the locations at which (contiguous) respective portions of the single 3D-NAND array begin, instructions for how many BLs will be part of the search (e.g., less than all), and instructions to optionally perform the search one small search word at a time or two small search words together.

[0217] and Figure 6 similar, Fig.10 Indicates that two searches are performed in a 3D-NAND memory array (e.g., NAND array 150) (either once through a small search word or through two small search words together). A first portion of data (e.g., portion 1 data 1041) is stored in the first portion of the 3D-NAND memory array. A second portion of data (e.g., portion 2 data 1042) is stored in the second portion of the 3D-NAND memory array. The first of the two searches (corresponding to portion 1 1031) is performed using respective BLs and WLs corresponding to the first portion of the 3D-NAND memory array. The second of the two searches (corresponding to portion 2 1032) is performed using respective BLs and WLs corresponding to the second portion of the 3D-NAND memory array. The WLs of the first portion of the 3D-NAND array (e.g., the WLs coupled to portion 1 data 1041 stored in NAND array 150) are separated from the WLs of the second portion of the 3D-NAND array (e.g., the WLs coupled to portion 2 data 1042 stored in NAND array 150).

[0218] Unused layers, unused memory column pairs, and / or unused 2D arrays are manipulated to be effectively ignored with respect to matching, as described with respect to Figure 5 as described.

[0219] 3D-NAND memory search scale (Scaling) - multiple characters / multiple 3D arrays

[0220] Fig.11 A technique for searching multiple words in parallel in multiple 3D-NAND arrays is shown. The operation is similar to Figure 7 However, Fig.11 Parallel processing of two word groups is shown, rather than parallel processing of 2 long words, with optional combinatorial logic operations. Examples of combinatorial logic operations are AND, OR, XOR, XNOR, and other, such as two-operand logic operations. Logic operations 1199 of result combination + sorting 191 are enabled to perform combinatorial logic operations. If there are no logic operations, separate search results are provided for each 3D-NAND array.

[0221] In summary, word input 1110 is processed into word group 1 1111 and word group 2 1112. Word group 1 1111 is applied to group 1 data 1141 via group 1 1121 and word line (WL) 1131. In parallel, word group 2 1112 is applied to group 2 data 1142 via group 2 1122 and word line (WL) 1132. Result combination + sorting 191 controls parallel sorting and optionally combines the sensing results determined from NAND array 1 151 and NAND array 2 152 via logical operations performed by logic operation 1199 to produce an overall search result, such as result 190.

[0222] For example, the search criteria include instructions for search word length (e.g., the number of words equal to how many memory string pairs are connected to each BL), instructions for a first set of search words with three digits for each word, instructions for a second set of search words with five digits for each word, instructions for searching two 3D-NAND arrays in separate sets of search words, and instructions for combining logical operations to perform.

[0223] The system is capable of varying the character length (eg, L), number of digits / levels (eg, n), and / or number of cardins / levels (eg, m) between data sets.

[0224] and Figure 6 similar, Fig.11Indicates that two searches are performed in a 3D-NAND memory array (NAND array 1 151 and NAND array 2 152 are collectively referred to). A first group of data (e.g., group 1 1141) is stored in a first portion of the 3D-NAND memory array. A second group of data (e.g., group 2 1142) is stored in a second portion of the 3D-NAND memory array. The first of the two searches (corresponding to group 1 1121) is performed using respective BLs and WLs corresponding to the first portion of the 3D-NAND memory array. The second of the two searches (corresponding to group 2 1122) is performed using respective BLs and WLs corresponding to the second portion of the 3D-NAND memory array. The WLs of the first portion of the 3D-NAND array (e.g., WLs coupled to group 1 data 1141 stored in NAND array 1 151) are separated from the WLs of the second portion of the 3D-NAND array (e.g., WLs coupled to group 2 data 1142 stored in NAND array 2 152).

[0225] Unused layers, unused memory column pairs, and / or unused 2D arrays are manipulated to be effectively ignored with respect to matching, as described with respect to Figure 5 as described.

[0226] Search scale in 3D-NAND memory - multiple words / single 3D array

[0227] Fig. 12A and Fig. 12B (collectively, FIG. 12 ) collectively illustrate a technique for searching between multiple word groups in a single 3D-NAND array. The operation is similar to Figure 8 However, it is not the processing of 2 long characters, but in Fig. 12A and Fig. 12B The sequence and parallel processing of two word groups are shown respectively. In the case of parallel processing, the sensing results of the search between word groups are implicitly combined by a logical AND operation.

[0228] In summary, in sequence operations ( Fig. 12A ), word input 1210 is processed sequentially via group 1 1221 and group 2 1222. Word input 1210 is applied to group 1 data 1241 via group 1 1221 and word line (WL) 1231. Layers of the NAND array 15 other than group 1 data 1241 are operated to be effectively ignored with respect to matching, such as by applying a pass voltage (e.g., Vpass) to the WL of unused layers (e.g., layers including group 2 data 1242).

[0229] The word input 1210 is then applied to the group 2 data 1242 via the group 21222 and the word line (WL) 1232. The layers of the NAND array 150 other than the group 2 data 1242 are operated to be effectively ignored in terms of matching, such as by applying a pass voltage (e.g., Vpass) to the WL of the unused layers (e.g., the layers including the group 1 data 1241). The result combination + sorting 191 controls the sequence sorting, and the respective sensing results determined from the NAND array 1151 and the NAND array 2 152 are provided sequentially as the results 190 of the respective search results, or provided in parallel as the results 190 of the search results.

[0230] In short, in parallel operation ( Fig. 12B ), character input 11211 and character input 21212 are processed in parallel.

[0231] Word input 1 1211 is applied to group 1 data 1241 via group 1 1221 and word line (WL) 1231. In parallel, word input 2 1212 is applied to group 2 data 1242 via group 2 1222 and word line (WL) 1232. Result combination + sorting 191 controls parallel sorting and provides result 190 of search results determined by a logical AND operation of the sensing result of NAND array 1 151 and the sensing result of NAND array 2 152.

[0232] For example, the search criteria include instructions for searching for a word length (e.g., a number of characters equal to how many memory string pairs are connected to each BL), instructions for searching for words with five digits per character, instructions for searching a single NAND array in two groups, instructions for describing the starting positions of the (non-contiguous) individual groups in a single 3D-NAND array, and optionally instructions for performing the search using serial processing or parallel processing.

[0233] The system is capable of varying the word length (e.g., L), number / level (e.g., n), and / or cardinality / level (e.g., m) between data groups. For example, for two word groups, one word group has fewer characters than the other word group, the unused memory devices corresponding to the unused characters in the NAND array 150 of the word group having fewer characters are programmed to a Don't Care value, or the corresponding WL is driven to a wildcard bias value.

[0234] Unused layers, unused memory column pairs, and / or unused 2D arrays are manipulated to be effectively ignored with respect to matching, as described with respect to Figure 5 as described.

[0235] Search operation in 3D-NAND memory

[0236] Fig.13 A search system within a 3D-NAND memory (eg, Figure 1A An example operation process of the 3D-NAND memory search system 100 is shown, such as the search process 1300.

[0237] The flow begins by selecting a specific encoding technique 1301. The specific encoding technique is used for programming data and searching.

[0238] Flow then proceeds to programming data according to the selected encoding technique 1302. For example, with respect to FIG. 1, data encoder 160 receives data 110, encodes it according to a particular encoding technique (e.g., as shown in encoding 140), and provides encoded data 111 to NAND array 150 to be programmed as the stored data to be searched.

[0239] Flow then proceeds to encoding the search according to the selected encoding technique 1303. Continuing with this example, the search encoder 170 receives the search 120, encodes the search value therein according to a particular encoding technique, and provides the word lines (WL, WL's) 172 to the NAND array 150 for searching. The search 120 optionally includes one or more instructions on how to perform the search. The search encoder 170 optionally uses one or more instructions to determine which layers to encode the search value with respect to the word lines (WL, WL's) 172. The search encoder 170 selectively overrides all or any portion of the word lines (WL, WL's) 172 with a voltage that enables current to pass through the memory string, regardless of the threshold voltage. The search encoder 170 selectively determines which SSLs to enable, as provided to the NAND array 150 on the string select line (SSL) 171.

[0240] Flow then proceeds to drive string select lines and word lines 1304. Continuing this example, circuitry in search encoder 170 and / or NAND array 150 drives information provided via string select lines (SSL) 171 and word lines (WL, WL's) 172 of the 2D memory array of NAND array 150, respectively.

[0241] The flow then proceeds to sense bit line 1305. Continuing with this example, circuitry (e.g., one or more sense amplifiers and / or comparators) in NAND array 150 and / or page buffer 130 senses the bit line in response to driving the SSL and word lines, and the subsequent current flow in the bit line is affected by the memory device.

[0242] Flow then proceeds to priority encode sense results 1306. Continuing with this example, one or more priority encoders of page buffer 130 determine from the results of the bit line sense which zero or greater stored data values ​​match when compared to the search value, based on any provided instructions on how to perform the search.

[0243] Flow then continues to provide results 1307. For example, the results are provided to the host agent, such as results 190. Flow then optionally continues back to encode the next search (encoding the search according to the selected encoding technique 1303).

[0244] In a sequence search, for example, one or more sensing results determined by the sequence are combined to produce an overall search result (e.g., regarding Figure 6 ), one or more of actions 1303, 1304, 1305, and / or 1306 are repeated before action 1307. In a parallel search, for example, one or more sensed results determined in parallel are combined to generate an overall search result (e.g., regarding Figure 6 As described above, one or more of actions 1303, 1304, 1305 and / or 1306 are performed in parallel for one or more search values ​​and / or instructions on how to perform the search.

[0245] 3D-NAND In-Memory Search In-Memory Search Cell

[0246] Fig.14 IMS cell 1480 is shown in the context of a memory string pair connected to a BL. Floating gate device (FG) 1483 (of the left memory string of the memory string pair) is connected to word line (WL) 1481. Floating gate device (FG′) 1484′ (of the right memory string of the memory string pair) is connected to word line ′ (WL′) 1482. Floating gate device (FG) 1483 and floating gate device ′ (FG′) 1484 are programmable, for example, by adjusting the threshold voltage by charging / discharging the included floating gates. Therefore, floating gate device (FG) 1483 and floating gate device ′ (FG′) 1484 can be programmed together to store various unique symbols called levels.

[0247] For example, Fig.15A and Fig. 15B as well as Fig.19A and Fig.19B A two-level technique is shown. In another example, Fig.16A , Fig. 16B and Fig. 16C as well as Fig. 20A , Fig. 20B and Fig. 20C An eight-level technique is shown. In another example, Fig.17A and Fig. 17B as well as Fig.21A and Fig. 21B In another example, Fig.18 An analog technique is shown.

[0248] Each of the two-level, eight-level, p-level, and analog techniques is based on a respective specific encoding technique implemented by the data encoder 160 and the search encoder 170 of FIG. 1 .

[0249] Searching for large mismatch current in 3D-NAND memory

[0250] Fig.15A and Fig. 15B An example of an encoding technique using two threshold levels and providing a high current indication of a mismatch between search data and stored data is shown. This encoding technique is referred to as a two-threshold high current mismatch encoding technique. These figures correspond to Fig.14 Implementation of a two-threshold large current mismatch of the IMS unit 1480.

[0251] Fig.15A Two threshold levels are shown, memory state LVT (low threshold voltage) 1572 and memory state HVT (high threshold voltage) 1573. This figure also shows that a mismatch between the search input and the stored data is indicated (resulting in a pass ( Fig.14 ) a large current through at least one of the floating gate device (FG) 1483 and the floating gate device '(FG′) 1484), and an indication of searching for a match between the input and stored data (resulting in a small current through each of the floating gate device (FG) 1483 and the floating gate device '(FG′) 1484).

[0252] Fig. 15B Search data encoding and storage data encoding according to the two-threshold large current mismatch encoding technique are shown.

[0253] Fig.16A , Fig. 16B and Fig. 16C Together, an example of an encoding technique using eight threshold levels and providing a larger current indication of a mismatch between search data and stored data is shown. This encoding is referred to as an eight-threshold larger current mismatch encoding technique. These figures correspond to Fig.14 An implementation of the IMS unit 1480 with eight threshold larger current mismatches.

[0254] Fig.16AEight threshold levels Vt 11671 ... Vt 71677 and zero threshold level Vt 01670 and corresponding encoding voltages V0 ... V8 are shown. This figure also shows a representation of the mismatch between the search input and the stored data (resulting in a pass ( Fig.14 ) a relatively large current through at least one of the floating gate device (FG) 1483 and the floating gate '(FG′) 1484), and an indication of searching for a match between the input and stored data (resulting in a relatively small current through each of the floating gate device (FG) 1483 and the floating gate device '(FG′) 1484).

[0255] Fig. 16B Search data encoding and storage data encoding according to the eight-threshold large current mismatch encoding technique are shown.

[0256] Fig. 16C An example of the total current flowing through floating gate device (FG) 1483 and floating gate device (FG′) 1484 together for various combinations of search input and stored data is shown. In general, darker boxes represent smaller currents. For example, a match between search input and stored data along a descending diagonal line results in a minimum total current Ioff.

[0257] Fig.17A and Fig. 17B Together, an example of a p-level encoding technique using p-threshold levels and providing a larger current indication of a mismatch between search data and stored data is shown. This encoding is referred to as a p-threshold larger current mismatch encoding technique. These figures correspond to Fig.14 1480 of the IMS unit 1480 has a larger current mismatch of the p threshold. Accordingly, these figures correspond to Fig.16A , Fig. 16B and Fig. 16C A p-level summary of the eight-level technique.

[0258] Fig.17A The p threshold levels Vt 1 1771 ... Vt p 1776 and the zero threshold level Vt 0 1770 are shown along with the corresponding encoding voltages V0, V1 ... V(p-2), v(p-1), V(p) and V(p+1). This figure also shows a representation of the mismatch between the search input and the stored data (resulting in a pass through Fig.14 ) a relatively large current through at least one of the floating gate device (FG) 1483 and the floating gate device '(FG′) 1484), and an indication of searching for a match between the input and stored data (resulting in a relatively small current through each of the floating gate device (FG) 1483 and the floating gate device '(FG′) 1484).

[0259] Fig. 17BSearch data encoding and storage data encoding according to the p-threshold large current mismatch encoding technique are shown.

[0260] Fig.18 An example of an encoding technique that uses analog levels and provides a larger current indication of a mismatch between search data and stored data is shown. This encoding is called analog large current mismatch encoding. This figure corresponds to Fig.14 Implementation of the IMS unit 1480 that simulates a larger current mismatch.

[0261] Current 1810 represents the vertical dimension of the memory device source-drain current plotted against the horizontal dimension of the memory device control gate voltage. Two graphs are shown, Fig.14 The source-drain current 1883 of the floating gate (FG) 1483, and Fig.14 1484. For the floating device gate (FG) 1483, the current 1883 is the source-drain current as a function of the voltage applied to the word line (WL) 1481, as shown by the word line (WL) 1881 within a range (e.g., 4 to 0 volts). Similarly, for the floating gate device '(FG') 1484, the current '1884 is the source-drain current as a function of the voltage applied to the word line '(WL') 1482, as shown by the word line '(WL') 1882 within a range (e.g., 4 to 0 volts).

[0262] The bit line voltages of the two regions indicate a mismatch between the search input and the stored data (as indicated by the tuned threshold voltage). The mismatch 1885 of the first of the two regions indicates that the floating gate device (FG) 1483 is turned on, thereby enabling a larger current. The mismatch 1887 of the second of the two regions indicates that the floating gate device '(FG') 1484 is turned on, thereby enabling a larger current. The single middle region indicates a match between the search input and the stored data. The match 1886 of the middle region indicates when both the floating gate device (FG) 1483 and the floating gate device '(FG') 1484 are turned off, resulting in a smaller current.

[0263] Thus, WL, WL' 1888 represents the combination of the voltages on word line (WL) 1481 and word line ' (WL') 1482, resulting in a smaller current from IMS cell 1480, indicating a match between the search input and the stored data. WL, WL' 1889 represents the combination of the voltages on word line (WL) 1481 and word line ' (WL') 1482, resulting in a larger current from IMS cell 1480, indicating a mismatch between the search input and the stored data.

[0264] Floating gate device (FG) 1483 is shown as having a tunable threshold voltage within the range shown as tunable Vt 1878. Similarly, floating gate device (FG′) 1484 is shown as having a tunable threshold voltage 1878 within the range shown as tunable Vt 1879. The tunable threshold voltage can adjust the width of mismatch 1885, match 1886, and mismatch 1887.

[0265] Searching for small mismatch current in 3D-NAND memory

[0266] Fig.19A and Fig.19B An example of an encoding technique using two threshold levels and providing a small current as an indication of a mismatch between search data and stored data is shown. This encoding technique is called a two-threshold small current mismatch encoding technique. These figures correspond to Fig.14 An implementation of a two-threshold small current mismatch of the IMS unit 1480.

[0267] Fig.19A Two threshold levels are shown, memory state LVT 1972 and memory state HVT 1973. This figure also shows a representation of the mismatch between the search input and the stored data (by ( Fig.14 ) each floating gate device (FG) 1483 and floating gate device '(FG′) 1484 causes a small current), and an indication of searching for a match between the input and stored data (causing a large current through at least one of the floating gate device (FG) 1483 and floating gate device '(FG′) 1484).

[0268] Fig.19B Search data encoding and storage data encoding according to the two-threshold small current mismatch encoding technique are shown.

[0269] Fig. 20A , Fig. 20B and Fig. 20C Together, an example of an encoding technique using eight threshold levels and providing a smaller current indication for a mismatch between search data and stored data is shown. This encoding is referred to as an eight-threshold smaller current mismatch encoding technique. These figures correspond to Fig.14 An implementation of the IMS unit 1480 with eight threshold smaller current mismatches.

[0270] Fig. 20A Eight threshold levels Vt 02070 ... Vt 72077 and corresponding encoding voltages V0 ... V7 are shown. This figure also shows a representation of the mismatch between the search input and the stored data (by ( Fig.14) each floating gate device (FG) 1483 and floating gate device '(FG′) 1484 causes a relatively small current), and an indication of searching for a match between input and stored data (through at least one of the floating gate device (FG) 1483 and floating gate device '(FG′) 1484 causes a relatively large current 1.

[0271] Fig. 20B Search data encoding and storage data encoding according to the eight-threshold small current mismatch encoding technique are shown.

[0272] Fig. 20C An example of the total current through floating gate device (FG) 1483 and floating gate device '(FG') 1484 together for various combinations of search input and stored data is shown. In general, darker boxes represent larger currents. For example, a match between the search input and stored data along the descending diagonal line will produce the maximum total current I7.

[0273] Fig.21A and Fig. 21B Together, an example of a p-level encoding technique using p threshold levels and providing a small current indication of a mismatch between search data and stored data is shown. This encoding is referred to as a p-threshold small current mismatch encoding technique. These figures correspond to Fig.14 1480 of the IMS unit 1480 with a smaller p-threshold current mismatch. Accordingly, these figures correspond to Fig. 20A , Fig. 20B and Fig. 20C A p-level summary of the 8-level technique.

[0274] Fig.21A There are shown p threshold levels as Vt 1 2171 ... Vt p 2176 and a zero threshold level as Vt 0 2170 and the corresponding encoding voltages as Vt 0 ... Vt p. This figure also shows a representation of the mismatch between the search input and the stored data (by ( Fig.14 ) each floating gate device (FG) 1483 and floating gate device '(FG′) 1484 causes a relatively small current), and an indication of searching for a match between input and stored data (causing a relatively large current through at least one of the floating gate device (FG) 1483 and floating gate device '(FG′) 1484).

[0275] Fig. 21B Search data encoding and storage data encoding according to the p-threshold smaller current mismatch encoding technique are shown.

[0276] Searching for additional information in 3D-NAND memory

[0277] Example memory technologies suitable for memory arrays of high-level architectures for searching within 3D-NAND-based memories disclosed herein include floating gate, split-gate, SONOS, floating dot, DRAM, DRAM-like (e.g., 2TOC), FeFET, and any memory technology compatible with searching through word lines and bit lines. Exemplary SONOS memory technology (sometimes referred to as charge trap memory) uses an insulating layer (e.g., a silicon nitride layer) with traps to capture and retain charge injected from a channel. Exemplary floating point memory technology conceptually replaces the floating gate with floating silicon nanodots or embeds the floating silicon nanodots in a polysilicon gate. Exemplary 2TOC memory technology uses the parasitic capacitance of a read transistor rather than an explicit storage capacitor to store charge. Exemplary FeFET memory technology uses permanent electric field polarization of a ferroelectric material embedded between the gate and the source-gate conduction region to store information. Example memory structures of high-level architecture suitable for 3D-NAND-based in-memory search include 2D structures (e.g., 2D flash structures) and 3D structures (e.g., 3D flash structures). Example array architectures of high-level architecture suitable for 3D-NAND-based in-memory search include NOR / OR type array architectures and AND / NAND type array architectures.

[0278] It should be understood that the foregoing disclosure presents implementations, variations, examples and exemplifications intended to be illustrative rather than restrictive. It is understood that discernible modifications and combinations will be within the spirit and scope of the invention.

Claims

1. An integrated circuit, comprising: A three-dimensional NAND memory array includes a plurality of bit lines coupled to a plurality of respective sense amplifiers; a data encoder capable of encoding data according to a specific code to be stored in the three-dimensional NAND gate memory array; a search encoder capable of encoding a first search word to generate an encoded first search word encoded according to the specific code, encoding a second search word to generate an encoded second search word encoded according to the specific code, and applying the encoded first search word and the encoded second search word to respective first and second portions of the three-dimensional NAND memory array; as well as a logic operation module capable of performing one of a plurality of selectable logic operations; wherein the first portion of the three-dimensional NAND memory array is responsive to a first portion of the data stored therein and further responsive to the encoded first search word to generate a plurality of first sensing results using a first portion of the respective sense amplifiers, wherein the second portion of the three-dimensional NAND memory array is responsive to a second portion of the data stored therein and further responsive to the encoded second search word to generate a plurality of second sensing results using a second portion of the respective sense amplifiers, and The logic operation module can process the first sensing results and the second sensing results according to a selected one of the selectable logic operations.

2. The integrated circuit of claim 1, wherein the selectable logic operations include a logical AND operation, a logical OR operation, a logical XOR operation, and a logical XOR operation.

3. The integrated circuit of claim 1 , wherein the specific code is based on using a pair of memory devices of the three-dimensional AND gate memory array to store a number of data values ​​of the first portion of data, and further based on using a pair of word lines to apply a number of the first search word to the pair of memory devices.

4. The integrated circuit of claim 3, wherein the specific code represents the states of 0, 1 and X according to the respective settings of the threshold voltage of the first memory device and the threshold voltage of the second memory device of the pair of memory devices.

5. The integrated circuit of claim 3, wherein the specific code represents states of 0, 1, 2, 3, 4, 5, 6 and 7 according to respective settings of a threshold voltage of a first memory device and a threshold voltage of a second memory device of the pair of memory devices.

6. The integrated circuit of claim 1, wherein the first search word comprises a plurality of digits, and the search encoder is further capable of encoding digits of the digits corresponding to a plurality of layers storing the first portion of data.

7. The integrated circuit of claim 6, wherein the layers correspond to one or more planar processing layers of the integrated circuit.

8. The integrated circuit of claim 1, wherein the word lines of the first portion of the three-dimensional NAND memory array are separated from the word lines of the second portion of the three-dimensional NAND memory array.

9. The integrated circuit of claim 1, wherein the first search word and the second search word vary according to the number of characters, the number of digits per character, or both.

10. A method for operating an integrated circuit, comprising: Receiving a first search word and a second search word in a three-dimensional NAND gate memory; Searching the first search word among a plurality of stored values ​​of the three-dimensional NAND gate memory to generate a plurality of first bit line sensing results; Searching the second search word among the stored values ​​of the three-dimensional NAND memory to generate a plurality of second bit line sensing results; as well as combining the first bit line sensing results with the second bit line sensing results according to a selected one of a plurality of selectable logical operations to generate an overall search result; and The combination is performed using a circuit on the same integrated circuit chip including the three-dimensional NAND gate memory.

11. The method according to claim 10, wherein the selectable logical operations include a logical AND operation, a logical OR operation, a logical XOR operation and a logical XOR operation.

12. The method of claim 10, wherein the stored values ​​are encoded according to a specific code, the search for the first search character comprises encoding the first search character according to the specific code, and the search for the second search character comprises encoding the second search character according to the specific code.

13. The method of claim 12, wherein the specific code is based on using a pair of memory devices of the three-dimensional AND gate memory to store a number of the stored values, and further based on using a pair of word lines to apply a number of the first search word to the pair of memory devices.

14. The method of claim 13, wherein the specific code is based on representing states of 0, 1, and X by respective settings of a threshold voltage of a first memory device and a threshold voltage of a second memory device of the pair of memory devices.

15. The method of claim 13, wherein the specific code represents states of 0, 1, 2, 3, 4, 5, 6 and 7 according to respective settings of a threshold voltage of a first memory device and a threshold voltage of a second memory device of the pair of memory devices.

16. The method of claim 10, wherein the first search word comprises a plurality of digits, and the search for the first search word comprises searching for each of the digits in layers corresponding to a plurality of layers in which the stored values ​​of the three-dimensional NAND gate memory are organized.

17. The method of claim 16, wherein the layers correspond to one or more planar processing layers of an integrated circuit including the three-dimensional NAND memory.

18. The method according to claim 10, wherein the search for the first search word element and the search for the second search word element are performed in parallel using a first portion of the three-dimensional NAND gate memory and a second portion of the three-dimensional NAND gate memory, respectively, the word lines of the first portion are separated from the word lines of the second portion, and the bit lines of the first portion are separated from the bit lines of the second portion.

19. The method of claim 18, wherein the first search character and the second search character vary according to the number of characters, the number of digits per character, or both.

20. An integrated circuit comprising: a first three-dimensional NAND memory array and a second three-dimensional NAND memory array, the first three-dimensional NAND memory array comprising first bit lines coupled to respective first sense amplifiers, the second three-dimensional NAND memory array comprising second bit lines coupled to respective second sense amplifiers; a data encoder capable of encoding data according to a specific code to store in the first three-dimensional NAND gate memory array and the second three-dimensional NAND gate memory array; a search encoder capable of encoding a first search word to generate an encoded first search word encoded according to the specific code, encoding a second search word to generate an encoded second search word encoded according to the specific code, and applying the encoded first search word and the encoded second search word to the first three-dimensional NAND memory array and the second three-dimensional NAND memory array, respectively; as well as a logic operation module capable of performing one of a plurality of selectable logic operations; wherein the first three-dimensional NAND gate memory array is responsive to a first portion of the data stored therein and further responsive to the encoded first search word to generate a first sensing result using the respective sense amplifiers, wherein the second three-dimensional NAND memory array is responsive to a second portion of the data stored therein and further responsive to the encoded second search word to generate a second sensing result using the respective second sensing amplifiers, and The logic operation module can process the first sensing results and the second sensing results according to a selected one of the selectable logic operations.

Images