A Method for Calculating Squared Euclidean Distance Based on Split-Gate Flash Memory

Abstract

The present invention discloses a method for calculating the squared Euclidean distance based on a split-gate flash memory, belonging to the technical field of microelectronics and integrated circuits. The present invention maps the squared Euclidean distance as a quadratic polynomial function of the feature vector coordinates into the split-gate flash memory weight array for calculation, and uses hardware implementation to accelerate the calculation of the squared Euclidean distance. The present invention realizes the calculation of the squared Euclidean distance based on the split-gate flash memory, which can effectively reduce the calculation time, improve the energy efficiency of the system, and enhance the operation efficiency of related algorithms.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronics and integrated circuits, and particularly relates to a method for calculating the squared Euclidean distance based on a split-gate flash memory. Background Art

[0002] The Euclidean distance is the most direct distance metric, which is mathematically represented as the straight-line distance between two points in space. The Euclidean distance has advantages such as being intuitive and easy to understand, and having strong interpretability. It is widely used in machine learning fields such as clustering analysis, anomaly detection, recommendation systems, and regression algorithms. The Euclidean distance can be used in the design of loss functions to measure the difference between predicted values and true values; it can be used to optimize the gradient descent algorithm by calculating the length of the gradient to control the learning rate; it can be used for feature extraction by calculating the distance between feature vectors to measure the similarity between samples. When executing algorithms involving the Euclidean distance, a common task is to calculate the Euclidean distance between a certain test point and all other data points in the dataset. Therefore, the calculation process of the Euclidean distance is a key factor affecting the algorithm performance. The calculation of the Euclidean distance involves summing the squares of the differences of each dimension of the feature vector and then taking the square root. In many cases, calculating the squared Euclidean distance can achieve the same effect as calculating the Euclidean distance for the algorithm.

[0003] The calculation of the squared Euclidean distance is relatively simple when the amount of data is small or the dimension is low. However, as the data dimension increases or the total amount of data expands, the complexity of the calculation will increase significantly, and the required calculation time will also increase substantially. In the case of a huge amount of data, higher requirements are also placed on the memory and processor required to complete the calculation of the squared Euclidean distance, and the calculation process is limited by bandwidth, which further increases the complexity of the calculation of the squared Euclidean distance. Summary of the Invention

[0004] The purpose of the present invention is to propose a method for calculating the squared Euclidean distance based on a split-gate flash memory array, which uses hardware to accelerate the calculation of the squared Euclidean distance, improve the running efficiency of related algorithms, and enhance the system energy efficiency.

[0005] The technical solution of the present invention is as follows:

[0006] A method for calculating the squared Euclidean distance based on a split-gate flash memory, characterized in that the squared Euclidean distance is mapped as a quadratic polynomial function of the feature vector coordinates into a split-gate flash memory weight array for calculation, including the following steps:

[0007] 1) Determine the array weights and the input voltage vector according to the function expression of the squared Euclidean distance;

[0008] 2) Write the weights into the split-gate flash memory weight array respectively;

[0009] 3) Apply an input voltage to the separated-gate flash memory weight array. The separated-gate flash memory weight array performs matrix-bivector multiplication calculation, and the output current of the separated-gate flash memory weight array is equivalent to the squared Euclidean distance between two points, completing the calculation of the squared Euclidean distance.

[0010] Furthermore, the separated-gate flash memory weight array is composed of arranged separated-gate flash memory devices. The separated-gate flash memory device includes a floating gate, a selection gate, a coupling gate, an erase gate, a source, and a drain. Among them, the selection gate is separated from the floating gate and is located between the drain and the source; the coupling gate is located above the floating gate to assist the source in regulating the floating gate; the erase gate is located above the source and is adjacent to the floating gate. The drains and erase gates of the separated-gate flash memory devices in the same column of the above-mentioned separated-gate flash memory array are connected by a bit line BL and an erase line EG respectively, and the above-mentioned bit line BL and erase line EG are parallel; the selection gates and coupling gates of the separated-gate flash memory devices in the same row are connected by a word line WL and a coupling line CG respectively; the sources of the separated-gate flash memory devices are connected by a source line SL, and the word line WL, the coupling line CG, and the source line SL are parallel.

[0011] Furthermore, if the functional expression of the squared Euclidean distance is the positive weight matrix W + and the negative weight matrix

[0012] where "1" and "0" in the matrix represent the high transconductance state and the low transconductance state of the separated-gate flash memory devices in the array respectively, then the specific steps include:

[0013] 1) Write the positive weight matrix W + into the separated-gate flash memory positive weight array, and write the negative weight matrix W - into the separated-gate flash memory negative weight array;

[0014] 2) The two separated-gate flash memory weight arrays share the same input voltage vector, that is, the bit line input voltage vector and the word line input voltage vector of the positive separated-gate flash memory weight array and the negative separated-gate flash memory weight array are the same;

[0015] 3) When calculating the squared Euclidean distance, all the source lines of the two separated-gate flash memory weight arrays are connected and their level is 0V, all the erase lines are grounded, and all the coupling lines are set to the same fixed value;

[0016] 4) Apply the bit line voltage input vector and the word line voltage input vector to the positive and negative separated-gate flash memory positive weight arrays for parallel read operation. The read current is the calculation result of the currents of the positive and negative separated-gate flash memory weight arrays, that is:

[0017]

[0018] 5) Subtract I p from I n to obtain the total output current I out , where I out represents the squared Euclidean distance between two points:

[0019]

[0020] Furthermore, if the functional expression of the squared Euclidean distance is a positive weight matrix

[0021] where the "1" and "0" in the matrix represent the high transconductance state and low transconductance state of the split-gate flash memory devices in the array respectively; the specific steps include:

[0022] 1) Write the positive weight matrix W + into the split-gate flash memory weight array;

[0023] 2) When calculating the squared Euclidean distance, all source lines of the split-gate flash memory weight array are connected and their levels are 0V, all erase lines are grounded, and all coupling lines are set to the same fixed value;

[0024] 3) Apply the bit line voltage input vector and the word line voltage input vector to the split-gate flash memory weight array for parallel read operation, and the read current is the calculation result of the positive array current, i.e.:

[0025] 4) Apply the bit line voltage input vector and the word line voltage input vector to the split-gate flash memory weight array for parallel read operation, and the read current is the calculation result of the negative array current, i.e.:

[0026] 5) Subtract I p from I n to obtain the total output current I out , where I out represents the squared Euclidean distance between two points:

[0027]

[0028] Furthermore, if the functional expression of the Euclidean distance is a positive weight matrix

[0029] where "1" represents the high transconductance state of the split-gate flash memory device; the specific steps include:

[0030] 1) Write the positive weight matrix into a single-column device of a split-gate flash memory array;

[0031] 2) When calculating the squared Euclidean distance, ground all source lines and all erase lines of this column of devices, and set the bit line level of this column to a fixed value;

[0032] 3) Apply the coupled gate voltage input vector and the word line voltage input vector to the single-column device for parallel read operation, and the read current is the calculation result of the positive current, that is:

[0033] 4) Apply the bit line voltage input vector and the word line voltage input vector to the single-column device for parallel read operation, and the read current is the calculation result of the negative current, that is:

[0034] 5) Subtract I p from I n to obtain the total output current I out , and I out represents the squared Euclidean distance between two points:

[0035]

[0036] The present invention has the following advantages:

[0037] The present invention realizes the calculation of the squared Euclidean distance based on a split-gate flash memory, which can effectively reduce the calculation time, improve the system energy efficiency, and enhance the operation efficiency of related algorithms. Description of the Drawings

[0038] Figure 1 is a schematic structural diagram of a split-gate flash memory device;

[0039] Figure 2 is a schematic structural diagram of a split-gate flash memory weight array;

[0040] Figure 3 is a schematic diagram for calculating the squared Euclidean distance using positive and negative split-gate flash memory weight arrays in Embodiment 1;

[0041] Figure 4 is a flowchart of the calculation method in Embodiment 1;

[0042] Figure 5 is a schematic diagram for calculating the squared Euclidean distance by multiplexing a split-gate flash memory weight array in Embodiment 2;

[0043] Figure 6 is a flowchart of the calculation method in Embodiment 2;

[0044] Figure 7 Schematic diagram of a single-column split-gate flash memory device in the split-gate flash memory weight array in Embodiment 3;

[0045] Figure 8 Flowchart of the calculation method in Embodiment 3. Specific Embodiments

[0046] The following further illustrates the embodiments of the present invention through specific examples in conjunction with the accompanying drawings.

[0047] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection claimed by the present invention is subject to the scope defined by the claims.

[0048] The structure of the split-gate flash memory device is as Figure 1 shown. This device has a total of five ports: a select gate, a coupling gate, an erase gate, a source, and a drain. Among them, the select gate is separated from the floating gate and is located between the drain and the source; the coupling gate is located above the floating gate to assist the source in regulating the floating gate; the erase gate is located above the source and is adjacent to the floating gate. When the erase gate and the source are grounded, the transconductance g of the coupling gate of the split-gate flash memory device m = W g × V BL . Among them, V BL is the drain voltage of the device; W g is the gate control factor of the select gate of the device, which reflects the control ability of the select gate over the channel. W g is determined by two factors: the floating gate charge state W and the coupling gate voltage V GG , that is, W g = W × V CG . Therefore, the expression for the transconductance of the coupling gate of the device is g m = W × V CG × V BL . The drain current of the device can be expressed as the product of the transconductance of the select gate and the select gate voltage, that is, I BL = g m × V WL = W × V CG × V BL × V WL .

[0049] The above split-gate flash memory devices are arranged to form a split-gate flash memory array, as Figure 2As shown. The drains and erase gates of the separated-gate flash transistors in the same column are connected by a bit line (BL) and an erase gate (EG) respectively, and the bit line and the erase line are parallel; the select gates and coupling gates of the separated-gate flash transistors in the same row are connected by a word line (WL) and a coupling gate (CG) respectively; the sources of the separated-gate flash transistors are connected by a source line (SL), and the word line, the coupling line and the source line are parallel. The separated-gate flash array can implement matrix-multi-vector multiplication operations. The stored matrix W first takes the inner product with the bit line input voltage vector and then takes the element product with the coupling line input voltage vector and the word line input voltage vector to finally obtain the source line output current vector That is:

[0050]

[0051] When one of the input vectors is fixed, the separated-gate flash weight array will perform matrix-two-vector multiplication calculation. If the coupling line input voltage vector is fixed to a specific value, the stored matrix W can be combined with to form the gate control factor matrix W g , and we can get:

[0052]

[0053] The source current vector represents the multiplication operation result of the gate control factor matrix with the bit line voltage vector and the word line voltage vector.

[0054] For two points P(p1,…,p n ) and Q(q1,…,q n ) in an n-dimensional space, the squared Euclidean distance is:

[0055]

[0056] According to the above calculation method, the total output current can be obtained as follows:

[0057]

[0058] The total output current is equivalent to the squared Euclidean distance between the two points, indicating that the separated-gate flash weight array can complete the calculation of the squared Euclidean distance.

[0059] Example 1:

[0060] Figure 3An array mapping method for calculating the squared Euclidean distance based on split-gate flash memory is presented. Two complementary split-gate flash memory weight arrays are used to implement the gate control factor matrix W g . The two split-gate flash memory weight arrays share the same input voltage vector, that is, the bit-line input voltage vectors of the positive split-gate flash memory weight array and the negative split-gate flash memory weight array and the word-line input voltage vectors are respectively the same.

[0061] For two points P(p1, …, p n ) and Q(q1, …, q n ) in an n-dimensional space, where the coordinate values of P and Q have been normalized according to the linear region voltage input range of the split-gate flash memory, set W g as follows:

[0062]

[0063]

[0064] where "1" and "0" in the matrix respectively represent the high transconductance state and the low transconductance state of the split-gate flash memory devices in the array. The scale of W g is 2n * 2n.

[0065] Define the source-line output current vector of the positive split-gate flash memory weight array as the positive array current and the source-line output current vector of the negative split-gate flash memory weight array as the negative array current When calculating the squared Euclidean distance, all the source lines of the two split-gate flash memory weight arrays are connected and their levels are 0V, all the erase lines are grounded, and all the coupling lines are set to the same fixed value.

[0066] The method for calculating the squared Euclidean distance based on the above split-gate flash memory weight array is as follows, and its flowchart is as Figure 4 shown:

[0067] 1) Write the positive weight matrix W + into the positive split-gate flash memory weight array; write the negative weight matrix W - into the negative split-gate flash memory weight array;

[0068] 2) The two split-gate flash memory weight arrays share the same input voltage vector, that is, the bit-line input voltage vectors of the positive split-gate flash memory weight array and the negative split-gate flash memory weight array and the word-line input voltage vectors are the same;

[0069] 3) When calculating the squared Euclidean distance, all the source lines of the two separated-gate flash memory weight arrays are connected and their levels are set to 0V, all the erase lines are grounded, and all the coupling lines are set to the same fixed value;

[0070] 4) Apply the bit-line voltage input vector and the word-line voltage input vector to the positive and negative weight arrays for parallel read operations, and the read currents are the calculation results of the positive and negative array currents respectively, that is:

[0071]

[0072] 5) Subtract I p from I n to obtain the total output current I out , and I out represents the squared Euclidean distance between two points:

[0073]

[0074] Embodiment 2:

[0075] Based on the same inventive concept as Embodiment 1, Figure 5 another array mapping method is given. That is, the separated-gate flash memory weight array is reused to complete the calculation of the source-line output current of the positive separated-gate flash memory weight array and the source-line output current of the negative separated-gate flash memory weight array.

[0076] When calculating the squared Euclidean distance, all the source lines of the separated-gate flash memory weight array are connected and their levels are set to 0V, all the erase lines are grounded, and all the coupling lines are set to the same fixed value.

[0077] For two points P(p1,…,p n ) and Q(q1,…,q n ) in an n-dimensional space, where the coordinate values of P and Q have been normalized according to the linear region voltage input range of the separated-gate flash memory, set the calculation of as follows:

[0078]

[0079] Set the calculation of as follows:

[0080]

[0081] Or:

[0082]

[0083] Set W + As follows:

[0084]

[0085] Wherein, "1" and "0" in the matrix respectively represent the high transconductance state and the low transconductance state of the isolated gate flash memory device in the array. W + has a scale of 2n * 2n.

[0086] The method for calculating the squared Euclidean distance based on the above isolated gate flash memory weight array is as follows, and its flowchart is as Figure 6 shown:

[0087] 1) Write the positive weight matrix W + into the isolated gate flash memory array;

[0088] 2) When calculating the squared Euclidean distance, all the source lines of the isolated gate flash memory weight array are connected and their level is 0V, all the erase lines are grounded, and all the coupling lines are set to the same fixed value;

[0089] 3) Apply the bit line voltage input vector and the word line voltage input vector to the array for parallel read operation, and the read current is the calculation result of the positive array current, that is:

[0090] 4) Apply the bit line voltage input vector and the word line voltage input vector to the array for parallel read operation, and the read current is the calculation result of the negative array current, that is:

[0091] 5) Subtract I p from I n to obtain the total output current I out , I out represents the squared Euclidean distance between two points:

[0092]

[0093] Embodiment 3:

[0094] Figure 7 is a schematic diagram of a single-column isolated gate flash memory device. Define the positive current negative current as the bit line output current of the single-column device. Reuse the single-column isolated gate flash memory positive weight device to complete and Calculation. When calculating the squared Euclidean distance, all source lines of the single-column device are grounded, all erase lines are grounded, and the bit line level of this column is set to a fixed value.

[0095] For two points P(p1,…,p n ) and Q(q1,…,q n ) in an n-dimensional space, where the coordinate values of P and Q have been normalized according to the linear region voltage input range of the split-gate flash memory, set the calculation when as follows:

[0096]

[0097] Set the calculation when as follows:

[0098]

[0099] Or:

[0100]

[0101] Set as follows, where "1" represents the high transconductance state of the split-gate flash memory device:

[0102]

[0103] The method for calculating the squared Euclidean distance based on a column of devices in the split-gate flash memory weight array is as follows, and its flowchart is as Figure 8 shown:

[0104] 1) Write the positive weight into the single-column device of the split-gate flash memory;

[0105] 2) When calculating the squared Euclidean distance, all source lines of this column of devices are grounded, all erase lines are grounded, and the bit line level of this column is set to a fixed value;

[0106] 3) Apply the coupling gate voltage input vector and the word line voltage input vector to the single-column device for parallel read operation, and the calculation result of the read current being a positive current is:

[0107] 4) Apply the bit line voltage input vector and the word line voltage input vector to the single-column device for parallel read operation, and the calculation result of the read current being a negative current is:

[0108] 5) Let I pSubtract from I n to obtain the total output current I out , I out represents the squared Euclidean distance between two points:

[0109]

[0110] Although the present invention has been disclosed above in preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for calculating the squared Euclidean distance based on a split-gate flash memory, characterized in that, The squared Euclidean distance is mapped into a split-gate flash memory weight array as a quadratic polynomial function of the feature vector coordinates for calculation, including the following steps: 1) Determine the array weights and the input voltage vector according to the function expression of the squared Euclidean distance; 2) Write the weights into the split-gate flash memory weight array respectively; 3) Apply the input voltage to the split-gate flash memory weight array, and the split-gate flash memory weight array performs matrix-two vector multiplication calculation. The output current of the split-gate flash memory weight array is equivalent to the squared Euclidean distance between two points, completing the calculation of the squared Euclidean distance.

2. The method for calculating the squared Euclidean distance based on a split-gate flash memory as claimed in claim 1, wherein The split-gate flash memory weight array is composed of arranged split-gate flash memory devices. The split-gate flash memory device includes a floating gate, a select gate, a coupling gate, an erase gate, a source and a drain. Among them, the select gate is separated from the floating gate and is located between the drain and the source; the coupling gate is located above the floating gate to assist the source in regulating the floating gate; the erase gate is located above the source and is adjacent to the floating gate. The drains and erase gates of the split-gate flash memory devices in the same column of the above split-gate flash memory weight array are connected by a bit line BL and an erase line EG respectively, and the above bit line BL and erase line EG are parallel; the select gates and coupling gates of the split-gate flash memory devices in the same row are connected by a word line WL and a coupling line CG respectively; the sources of the split-gate flash memory devices are connected by a source line SL, and the word line WL, the coupling line CG and the source line SL are parallel.

3. The method for calculating the squared Euclidean distance based on the split-gate flash memory according to claim 2, wherein If the functional expression of the squared Euclidean distance is the positive weight matrix W + and the negative weight matrix W - , Among them In the matrix, "1" and "0" respectively represent the high transconductance state and the low transconductance state of the isolated gate flash memory device in the array. The specific steps are as follows: 1) Write the positive weight matrix W + into the positive weight array of the split-gate flash memory, and write the negative weight matrix W - into the negative weight array of the split-gate flash memory; 2) The two split-gate flash memory weight arrays share the same input voltage vectors, i.e., the bit-line input voltage vectors of the split-gate flash memory positive weight array and the split-gate flash memory negative weight array and the word-line input voltage vectors are the same; 3) When calculating the squared Euclidean distance, all source lines of the two split-gate flash memory weight arrays are connected and their levels are 0V, all erase lines are grounded, and all coupling line levels are set to the same fixed value; 4) Apply a bit line voltage input vector to the separated gate flash positive weight array and the separated gate flash negative weight array and a word line voltage input vector to perform a parallel read operation, and the read current is the calculation result of the current of the separated gate flash positive weight array, that is: The read current is the calculation result of the current of the split-gate flash memory negative weight array, that is: 5) Subtract I p from I n to obtain the total output current I out , where I out represents the squared Euclidean distance between two points:

4. The method for calculating the squared Euclidean distance based on a split-gate flash memory according to claim 2, wherein If the functional expression of the squared Euclidean distance is the positive weight matrix W + , Among them, "1" and "0" in the matrix respectively represent the high transconductance state and the low transconductance state of the isolated gate flash memory device in the array; the specific steps include: 1) The positive weight matrix W + is written into a split-gate flash memory weight array; 2) When calculating the squared Euclidean distance, all source lines of the split-gate flash memory weight array are connected and their levels are 0V, all erase lines are grounded, and all coupling line levels are set to the same fixed value; 3) Apply a bit line voltage input vector to the separated gate flash memory weight array and a word line voltage input vector to perform a parallel read operation, and the read current is the calculation result of the positive array current, that is: 4) Apply a bit line voltage input vector to the separated gate flash memory weight array and a word line voltage input vector to perform a parallel read operation, and the read current is the calculation result of the negative array current, that is: 5) Subtract I p from I n to obtain the total output current I out , where I out represents the squared Euclidean distance between two points:

5. The method for calculating the squared Euclidean distance based on the split-gate flash memory according to claim 2, wherein If the functional expression of the Euclidean distance is a positive weight matrix where "1" represents the high transconductance state of the split-gate flash device; the specific steps include: 1) Write the positive weight matrix to a single-column device of a split-gate flash memory array; 2) When calculating the squared Euclidean distance, all source lines of the devices in this column are grounded, all erase lines are grounded, and the bit line level of this column is set to a fixed value; 3) Apply a coupled gate voltage input vector to the single-column device and a word line voltage input vector to perform a parallel read operation, and read out the calculation result with a positive current, that is: 4) Apply a bit line voltage input vector to the single-column device and a word line voltage input vector to perform a parallel read operation, and the calculation result of the read current being a negative current is: 5) Subtract I p from I n to obtain the total output current I out , where I out represents the squared Euclidean distance between two points:

Images