A high-performance in-memory search method and device for ultra-long dimension vector sorting

Abstract

The application provides a high-performance full-precision in-memory search method and device for super-long dimension vector sorting. First, a first search operation is performed on each segment of input feature data, and it is judged whether the Hamming distance with the corresponding segment of stored data is within a calculable range. When the second search operation is performed, if the Hamming distance is within the calculable range in the first search operation, the segment of input feature data is unchanged, otherwise, the segment of input feature data is inverted bit by bit, and then the Hamming distance between the current segment of input feature data and the segment of stored feature data is calculated. The Hamming distances of the segments of input feature data and the corresponding segments of stored feature data are fused, the matching number result between the super-long dimension input feature vector data and the stored category data is calculated, and the low-difference super-long dimension vector similarity sorting is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital integrated circuit design, in particular to a high-performance full-precision in-memory search method and device for ultra-long dimension vector sorting. BACKGROUND

[0002] The rapid development of big data-driven applications and the dramatic increase in data volume have brought about the storage wall problem for traditional computing architectures, i.e., the data transmission bottleneck between storage units and computing units. To overcome this problem, in-memory computing technology has emerged. In-memory computing eliminates the data transmission bottleneck by directly integrating computing operations into storage units, improving computing efficiency and system performance. This technology solves the storage wall problem under the von Neumann architecture, enabling storage and computation to be performed simultaneously, greatly improving data processing speed.

[0003] However, when applying in-memory computing design to perform classification tasks, precise matching or threshold matching of each vector may affect the inference accuracy of the entire circuit. Especially when the number of classifications increases, traditional in-memory search design methods may not be able to accurately distinguish between input data with very low Hamming distances. In traditional in-memory search design, there are problems with precise matching and threshold matching, especially in the case of numerous classifications, where small vector differences may be overlooked. This can result in classification errors or inaccurate recognition results.

[0004] These challenges indicate that in in-memory computing design, especially when dealing with large-scale data, it is necessary to consider how to effectively distinguish small differences between multi-class ultra-long dimension vectors to ensure accurate classification and inference results, which will have a significant impact on the performance and accuracy of the system. SUMMARY

[0005] The purpose of the present application is to provide a high-performance full-precision in-memory search method and device for ultra-long dimension vector sorting, which can calculate the number of matching results between ultra-long dimension input feature vector data and storage classification data, and realize low-difference ultra-long dimension vector similarity sorting.

[0006] To achieve the above technical purposes, the technical solution adopted by the present application is as follows:

[0007] In a first aspect, the present application discloses a high-performance full-precision in-memory search method for ultra-long dimension vector sorting, which comprises the following steps:

[0008] In the matching number statistics process of the ultra-long dimension vector, when the in-memory search is performed on M-bit input feature data, a first search operation is performed on each M-bit input feature data to determine whether the Hamming distance with the corresponding storage data is within a calculable range;

[0009] If the Hamming distance is within the distinguishable range, it is determined that the matching number is greater than The second search operation maintains the original input feature data; if the Hamming distance is not within the distinguishable range, it is determined that the matching number is less than or equal to The second search operation takes the original input feature data by bit inversion, and then calculates the Hamming distance between the current segment input feature data and the segment storage feature data;

[0010] The Hamming distances of each segment input feature data and the corresponding segment storage feature data are fused to calculate the matching number result compared between the super-long dimension input feature vector data and the storage category data; wherein, the maximum calculable Hamming distance of each segment input feature data compared with the corresponding segment storage data in any one search operation is

[0011] Further, the array circuit is used to store and search the input feature data, which specifically includes the following steps:

[0012] An array of N rows and M columns of storage units is constructed, the storage units in the same row are connected to the same word line, the storage units in the same column are connected to the same bit line, and each column of storage units is connected to the matching line through a search circuit;

[0013] When searching the input feature data in the storage, after each segment of input feature data performs a search operation, the matching line presents A case; if the input feature data is not inverted, the matching number value range corresponding to the voltage maintained by the matching line from high to low after discharge is M to If the input feature data is inverted, the matching number value range corresponding to the voltage maintained by the matching line from high to low after discharge is 0 to

[0014] After obtaining the result of the first search operation, if the voltage maintained by the matching line after discharge is not the lowest, the Hamming distance is within the distinguishable range; if the voltage maintained by the matching line after discharge is the lowest, the Hamming distance is not within the distinguishable range.

[0015] Further, the process of completing the matching number statistics of the input feature data compared with the corresponding segment storage data includes the following steps:

[0016] After the first search, the voltage value maintained by the matching line is sampled by A pre-charge read amplification circuit to generate Bit encoding signals;

[0017] According to The bit coding signal generates a control signal for logical operation with the current segment input feature data, and according to the judgment result of whether the Hamming distance is in the calculable range, the input feature data is inverted or unchanged;

[0018] The output is The matching number of the input feature data represented in the form of a bit binary digital signal is counted in the search result data valid period of each segment of the input feature data.

[0019] In a second aspect, the application discloses a high-performance full-precision in-memory search device for super-long-dimension vector sorting, and the high-performance full-precision in-memory search device comprises a register, an N-bit decoder, an array circuit module, an encoding control output module and a summary module.

[0020] The register and the input feature data are equal in length and are used for storing the input feature data with a length of M bits inputted from outside each time;

[0021] The N-bit decoder is used for generating a row selection signal;

[0022] The array circuit module stores the N*M-dimension storage long vector according to N rows and M columns;

[0023] The encoding control output module receives the M-bit input feature data outputted in series in N working periods, and the matching number of the input feature data is counted through two continuous search operation periods for each segment of the input feature data;

[0024] The summary module counts the matching number of the N*M-dimension input long vector after 2N search operation periods.

[0025] Further, the array circuit module comprises N rows of M column storage units; wherein the storage units in the same row are connected to the same word line, the storage units in the same column are connected to the same bit line, and each column of storage units is connected to a matching line through a search circuit;

[0026] When the in-memory search input feature data is inputted, the matching line presents a case after one search operation of each segment of the input feature data; if the input feature data is not inverted, the matching number corresponding to the voltage from high to low maintained after the discharge of the matching line is in the range of M to If the input feature data is inverted, the matching number corresponding to the voltage from high to low maintained after the discharge of the matching line is in the range of 0 to

[0027] After obtaining the results of the first search operation, if the sustaining voltage after the matched line discharges is not at its lowest, the Hamming distance is within the distinguishable range; if the sustaining voltage after the matched line discharges is at its lowest, the Hamming distance is outside the distinguishable range.

[0028] Furthermore, the encoding control output module includes an encoding module, a control module, and an output module.

[0029] The encoding module consists of A precharge read amplifier circuit and It consists of several D latches; in each search cycle, after the search is completed... Each precharge readout amplifier circuit samples the voltage value maintained by the matching line and generates... Bit-coded signal, after A D latch is sent to the control module; after the first search is completed, if the number of matches is... and below, The bit-coded signal is all 0s, otherwise The bit-coded signal contains a 1;

[0030] The control module outputs the results from the first search and subsequent encoding module. The bit-encoded signal generates a control signal, which is used to perform logical operations with the current input feature data. Based on the judgment result of whether the Hamming distance is within the computable range, the input feature data is either inverted bit by bit or left unchanged.

[0031] The output module receives the output from the encoding module. The bit-encoded signal and the control signal output by the control module are used to output the signal. The current segment length is M bits, represented by a binary digital signal, representing the number of matching input feature data.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] The high-performance, fully accurate in-memory search method and apparatus for sorting ultra-long dimension vectors of the present invention can calculate the number of matches between ultra-long dimension input feature vector data and stored category data, thereby achieving low-discrepancy ultra-long dimension vector similarity sorting. Attached Figure Description

[0034] Figure 1 A schematic diagram of a basic storage unit provided in an embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram of a search operation on a single storage unit provided in an embodiment of the present invention;

[0036] Figure 3The storage array architecture diagram with 8-bit word length provided for the embodiment of the present application is shown in the figure;

[0037] Figure 4 The encoding control output module schematic diagram provided for the embodiment of the present application is shown in the figure;

[0038] Figure 5 The memory timing definition diagram provided for the embodiment of the present application is shown in the figure;

[0039] Figure 6 The storage search architecture diagram with 8-bit word length and realizing matching number statistics for a type of input data provided for the embodiment of the present application is shown in the figure;

[0040] Figure 7 The high-performance full-precision storage search method flow chart for the super-long dimension vector sorting provided for the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0041] The embodiments of the present application are further described in detail below with reference to the accompanying drawings.

[0042] Referring to Figure 7 The present application discloses a high-performance full-precision storage search method for super-long dimension vector sorting, which comprises the following steps:

[0043] In the matching number statistics process of the super-long dimension vector, when searching the input feature data with M-bit length in the storage, the first search operation is performed on each M-bit input feature data to determine whether the Hamming distance with the corresponding storage data is within the calculable range;

[0044] If the Hamming distance is within the distinguishable range, it is determined that the matching number is greater than The second search operation maintains the original input feature data; if the Hamming distance is not within the distinguishable range, it is determined that the matching number is less than or equal to The second search operation inverts the original input feature data bit by bit, and then calculates the Hamming distance between the current input feature data and the storage feature data;

[0045] The Hamming distances of each input feature data and the corresponding storage feature data are fused to calculate the matching number result between the super-long dimension input feature vector data and the storage category data; wherein, the maximum calculable Hamming distance of each input feature data compared with the corresponding storage data in any search operation is

[0046] The method comprises:

[0047] Step S101, constructing the storage unit under the matching line.

[0048] In this step, the stored data is stored through the magnetic tunnel junction device, and 1 bit of data is stored by two magnetic tunnel junctions. This method not only effectively stores information, but also has high reliability and stability. By using the pre-charge search signal method, the magnetic tunnel junctions in different states can be effectively distinguished, thereby constructing a basic storage unit structure. See Figure 1 , Figure 1 is a schematic diagram of a basic storage unit.

[0049] Step S102, the search circuit of the storage unit is constructed.

[0050] In this step, the search operation of the storage unit is performed by using the latch structure composed of the pre-charged N-channel field effect tube, see Figure 2 , Figure 2 is a schematic diagram of a search operation of a single storage unit. The input data is a pair of complementary SL and SLB signals. When the PRE signal is low, VDD charges the Q and QB points. When the PRE signal is high, it indicates that the charging is complete. At this time, Q and QB start discharging through N1 and N2. Because the magnetic tunnel junctions of the two discharge paths are in different high and low resistance states, there will be a difference in discharge speed. The voltage on the branch with faster discharge will preferentially drop to '0', cutting off the discharge of the branch with slower discharge. In this process, one of Q and QB will be '0', and the other will maintain a certain voltage value.

[0051] The functions of N9 and N10 are to set appropriate VON voltage values, use the cutoff characteristics of field effect tubes, and make N9 or N10 on the branch where Q or QB maintains a higher voltage in a cutoff state, and N9 or N10 on the branch where the voltage is lower in a non-cutoff state. In this way, the control of the voltage difference between N9 and N10 can be achieved, and then the discharge speed and the final output state are affected.

[0052] After the above process is completed, the SAMPLE signal is set to high. If the matching line discharges, it is considered not to match, and if the matching line does not discharge, it is considered to match. The operation in this stage controls the behavior of the discharge path, combines the voltage and current changes between various components, and searches for and judges the state of the storage unit.

[0053] The implementation of this technology can improve the accuracy and efficiency of data search and writing, and this paper shows how to use this pre-charge technology to distinguish magnetic tunnel junctions in different states, thereby realizing reliable data storage and retrieval.

[0054] Step S103, the search process of an M-bit comparison word is completed.

[0055] In this step, taking M = 8 as an example, 1 row of 8 columns of storage unit structure and 8 search circuit structures corresponding to each are mounted on a match line to perform search search, see Figure 3 , Figure 3 is a storage array architecture diagram with a word length of 8 bits. The structure shows how to connect the storage units to the match line for search search.

[0056] The encoding control output module, see Figure 4 , Figure 4 is a schematic diagram of the encoding control output module. In this step, taking the comparison word length as 8 bits as an example, the encoding control output module takes the match line as input, the match number Q<0:3> of the current search data and a control signal ReInput as output.

[0057] The encoding control output module circuit compares the voltage value maintained by the match line at the end of each search period, encodes the comparison result D<0:3>, and generates a 4-bit encoding signal M<0:3>.

[0058] The control signal ReInput is used as an enable signal for bit-wise inversion of the input feature data in the second search operation. If the encoding signal M<0:3> is all 0 at the end of the first search period, it means that bit-wise inversion of the input feature data is needed in the second search operation; if the encoding signal M<0:3> is not all 0 at the end of the first search period, it means that bit-wise inversion of the input feature data is not needed in the second search operation, and the original input feature data is maintained.

[0059] The encoding control output module circuit generates the control signal ReInput according to the 4-bit encoding signal M<0:3> at the end of the first search period; the encoding control output module circuit generates a 4-bit binary signal Q<0:3> representing the match number of the current 8-bit comparison word according to the combination logic of the 4-bit encoding signal M<0:3> and the control signal ReInput at the end of the second search period.

[0060] In this step, the complete memory timing definition is shown in Figure 5 , Figure 5 is a memory timing definition diagram. Therefore, the search operation on a comparison word requires two search periods, and the search time in the second search period is the data valid period. The output Q<0:3> of the encoding control output module represents the match number of the current 8-bit comparison word.

[0061] Step S104, complete the match number statistics of N x M dimensional long vector in memory search architecture.

[0062] In this step, the principle of the in-memory search architecture for counting the number of matches of a class of super-long dimension vector is taken as an example with M = 8. Refer to Figure 6 , Figure 6 The in-memory search architecture diagram for counting the number of matches of a class of input data with a comparison word length of 8 bits is shown. It includes the complete search circuit part, the encoding control output module part MRPM, and part of the peripheral circuit decoder, I / O buffer, and match number Merge summary module.

[0063] The register and input feature data are equal in length and are used to store the M (here, 8) bit comparison word data input from the I / O port. In each clock cycle, the register gradually receives and stores 8-bit comparison word data from the I / O port.

[0064] The N-bit decoder is used to generate row selection signals for controlling 2 N rows in the array. This decoder is responsible for decoding the input address signal and generating the corresponding row selection signal for selecting the enable of a specific row in the array. The input of this N-bit decoder is an address signal, and the length of the address signal is N bits. According to different address signal combinations, the decoder will correspondingly activate the corresponding row selection signal. In the system, the address signal of this N-bit decoder is updated every two search cycles. This means that every two search cycles, the address signal will change, and the decoder will generate a new row selection signal accordingly. This update frequency ensures the synchronization of the address signal and the row selection signal, so that the data in the array can be selected and processed according to the correct address.

[0065] The input of the summary module (Merge module) is a (here, 4) bit binary signal, and the output is the final match number of the input data in binary form. This summary module is used to count the number of matches in a class of input data. In the form of a pipeline, the output of the MRPM encoding control output module is counted in N clock cycles in the form of a pipeline. This means that in each clock cycle, the match results of each input feature data are counted in the order of the pipeline. The output of the MRPM encoding control output module is added by a (here, 4) bit binary data full adder operation. Update and store the calculation results: according to the input order of the pipeline, in each data valid period, update and store the current calculation match result as the match number of a class of input vector. After N data valid periods, the match result is gradually calculated and updated, and finally the match number of a class of input data is obtained.

[0066] ​Those skilled in the art will appreciate that embodiments of the application can be readily used as software, hardware, or a combination of software and hardware. In one embodiment, the application can be implemented in software and / or firmware. In particular, the application forms computer software that is installed in or used by various apparatuses described herein and that is configured to implement the techniques disclosed herein. The software aspects of the application can be embodied

[0067] The present application is described in reference to the drawings using a flowchart and / or a block diagram of methods, apparatuses (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart and / or block diagram, and combinations of blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing system or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0068] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0069] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0070] While preferred embodiments of the application have been described, modifications and alterations thereto will occur to those skilled in the art upon reading the preceding description. In particular, it is apparent that those skilled in the art will be able to devise various embodiments that, although different in nature, possess the same technological characteristics and functional equivalent results as described herein. Accordingly, it is intended and submitted that the scope of the application be limited only by the appended claims and their equivalents.

[0071] Obviously, numerous modifications and variations of the present application are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A high-performance, fully accurate in-memory search method for ultra-long-dimensional vector sorting, characterized in that, The high-performance, fully accurate in-memory search method includes the following steps: In the process of matching the number of ultra-long dimension vectors, when searching for input feature data of length M bits in the memory, the first search operation is performed on each segment of M-bit input feature data to determine whether the Hamming distance with the corresponding segment of stored data is within the calculable range. If the Hamming distance is within the distinguishable range, the number of matches is greater than [a certain value]. The second search operation maintains the original input feature data; if the Hamming distance is not within the distinguishable range, it determines that the number of matches is less than or equal to... The second search operation inverts the original input feature data bit by bit, and then calculates the Hamming distance between the current segment input feature data and the segment stored feature data; By fusing the Hamming distances between the input feature data segments and the corresponding stored feature data segments, the number of matches between the ultra-long-dimensional input feature vector data and the stored category data is calculated. Specifically, the maximum computable Hamming distance between each input feature data segment and the corresponding stored data segment at any given search operation is [value missing]. The use of array circuits to store and search input feature data includes the following steps: Construct an N-row, M-column storage cell array, where storage cells in the same row are connected to the same word line, storage cells in the same column are connected to the same bit line, and storage cells in each column are connected to the matching line through a search circuit; When searching for input feature data within memory, the matching line appears after each segment of input feature data undergoes one search operation. In this case, if the input feature data is not inverted, the number of matching lines corresponding to the maintenance voltage decreasing from high to low after the matching line discharges ranges from M to... If the input feature data is inverted, the number of matched lines corresponding to the maintenance voltage after discharge, from high to low, will range from 0 to... After obtaining the result of the first search operation, if the maintenance voltage after the matching line discharges is not the lowest, the Hamming distance is within the distinguishable range; if the maintenance voltage after the matching line discharges is the lowest, the Hamming distance is not within the distinguishable range.

2. The high-performance, fully accurate in-memory search method for ultra-long dimension vector sorting according to claim 1, characterized in that, The process of counting the number of matches between the input feature data and the corresponding segment stored data includes the following steps: After the first search, via Each precharge readout amplifier circuit samples the voltage value maintained by the matching line and generates... Bit-coded signal; according to The bit-encoded signal generates a control signal, which is used to perform logical operations with the current segment input feature data. Based on the judgment result of whether the Hamming distance is within the computable range, the input feature data is either inverted bit by bit or left unchanged. Output with The number of matches of the input feature data is represented in the form of a bit binary digital signal. The number of matches of the input feature data segment is counted during the validity period of the search results data for each segment of input feature data.

3. A high-performance, fully precise in-memory search device for ultra-long-dimensional vector sorting, characterized in that, The high-performance, fully accurate in-memory search device includes a register, an N-bit decoder, an array circuit module, an encoding control output module, and a summarization module. The register and the input feature data are of equal length and are used to store input feature data with an external input segment length of M bits each time. The N-bit decoder is used to generate row selection signals; The array circuit module stores the N*M dimension long vector in N rows and M columns; The encoding control output module receives M bits of input feature data serially output in N working cycles. For each segment of input feature data, the method described in claim 1 is used to complete the matching count of the input feature data through two consecutive search operation cycles. The aggregation module performs a statistical analysis on the number of matches for the N*M dimension input long vector after 2N search operation cycles. The array circuit module includes N rows and M columns of storage units; wherein, each storage unit in the same row is connected to the same word line, each storage unit in the same column is connected to the same bit line, and each column of storage units is connected to the matching line through a search circuit. When searching for input feature data within memory, the matching line appears after each segment of input feature data undergoes one search operation. In this case, if the input feature data is not inverted, the number of matching lines corresponding to the maintenance voltage decreasing from high to low after the matching line discharges ranges from M to... If the input feature data is inverted, the number of matched lines corresponding to the maintenance voltage after discharge, from high to low, will range from 0 to... After obtaining the result of the first search operation, if the maintenance voltage after the matching line discharges is not the lowest, the Hamming distance is within the distinguishable range; if the maintenance voltage after the matching line discharges is the lowest, the Hamming distance is not within the distinguishable range.

4. The high-performance, fully accurate in-memory search device for ultra-long-dimensional vector sorting according to claim 3, characterized in that, The encoding control output module includes an encoding module, a control module, and an output module. The encoding module consists of A precharge read amplifier circuit and It consists of several D latches; in each search cycle, after the search is completed... Each precharge readout amplifier circuit samples the voltage value maintained by the matching line and generates... Bit-coded signal, after A D latch is sent to the control module; after the first search is completed, if the number of matches is... and below, The bit-coded signal is all 0s, otherwise The bit-coded signal contains a 1; The control module outputs the results from the first search and subsequent encoding module. The bit-encoded signal generates a control signal, which is used to perform logical operations with the current input feature data. Based on the judgment result of whether the Hamming distance is within the computable range, the input feature data is either inverted bit by bit or left unchanged. The output module receives the output from the encoding module. The bit-encoded signal and the control signal output by the control module are used to output the signal. The current segment length is M bits, represented by a binary digital signal, representing the number of matching input feature data.

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