Software security protection method and system of multi-core SOC and storage medium

Abstract

The invention discloses a software security protection method and system for a multi-core SOC and a storage medium, and belongs to the technical field of data security. The method comprises the steps that a layer of safety protection module is added outside a CPU and used for detecting the PC value range requested by all CPU cores, and meanwhile, a mem memory is matched to control the software operation boundary; when a certain CPU core initiates a memory access request, the memory management module queries and compares whether the memory access request is in a configured address space range, and if the memory access request is in the configured address space range, the CPU core is allowed to initiate a storage request bus access; if the address is not in the configured space address range, the CPU core is forbidden to request or return an invalid address; all requests for accessing the SRAM and the configuration space need to query security configuration items through the memory management module. According to the method, the software operation boundary can be effectively controlled, and illegal invasion of hackers and viruses can be prevented even if the software is abnormal or vulnerable.

Description

Technical Field

[0001] The present invention relates to the field of data security technology, and in particular to a software security protection method, system and storage medium for a multi-core SOC. Background Art

[0002] In theory, viruses or attack programs cannot be executed in the security software that has been verified during the CPU execution process. However, if there is an exception in the security software, causing the PC pointer to jump to an illegal address or entering the vector address range to fetch instructions for execution due to an exception (such as an exception), it will give hackers an opportunity to execute the program. The present invention is to solve the technical problem of using abnormal attacks on signature verification software. In the existing multi-core CPU environment, memory protection is only for a single core or a single CPU. There are many defects in actual application, and it is impossible to truly ensure the security of cross-core access control between multiple cores. Summary of the invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide a software security protection method, system and storage medium for a multi-core SOC.

[0004] The objective of the present invention is achieved through the following technical solutions: The first aspect of the present invention provides: a software security protection method for a multi-core SOC, comprising the following steps: Add a layer of security protection module outside the CPU to detect the PC value range of all CPU core requests and cooperate with the mem memory control software running boundary; When the chip is powered on, the ROM is initialized and the chip initialization security configuration is read; the CPU is initialized using this configuration; The security module is loaded and the ROM verifies the signature of the security module. If the signature verification passes, the ROM loads and runs the security module; if the signature verification fails, the bus access is disabled. After the security module is loaded and run, the security module initializes the security configuration register and configures the security configuration items of all CPU cores. After the configuration is completed, the security module sets the pmp init done register to 1 to make the security configuration items effective. The security configuration items are only allowed to be modified after the next power-on; When a CPU core initiates a memory access request, the memory management module queries and compares whether it is within the address space range configured by it. If it is within the address space range configured by it, the CPU core is allowed to initiate a storage request bus access; if it is not within the address space range configured by it, the CPU core request is prohibited or an invalid address is returned; all requests to access SRAM and configuration space need to query the security configuration items through the memory management module.

[0005] Preferably, the security module is security firmware or security software.

[0006] Preferably, the security configuration items include the access start address of each CPU core id, the access interval size, the read, write and execute permissions for the access start address interval, and the security enable item is set to 1.

[0007] The second aspect of the present invention provides: a software security protection system for a multi-core SOC, which is used to implement any of the above-mentioned software security protection methods for a multi-core SOC, comprising: The security protection module is set outside the CPU to detect the PC value range requested by all CPU cores and cooperate with the mem memory control software to run the boundary; The initialization module is used to initialize the ROM and read the chip initialization security configuration after the chip is powered on; and use the configuration to initialize the CPU; The signature verification module is used to load the security module and use the ROM to verify the signature of the security module. If the signature verification passes, the ROM loads and runs the security module; if the signature verification fails, the bus access is disabled; A configuration module is used to load and run the security module, use the security module to initialize the security configuration register, and configure the security configuration items of all CPU cores. After the configuration is completed, the security module sets the pmp init done register to 1 to make the security configuration items effective. The security configuration items are only allowed to be modified after the next power-on; The query module is used to query and compare whether a CPU core initiates a memory access request. If it is within the configured address space range, the CPU core is allowed to initiate a storage request bus access; if it is not within the configured address space range, the CPU core request is prohibited or an invalid address is returned; all requests to access SRAM and configuration space need to query the security configuration items through the memory management module.

[0008] The third aspect of the present invention provides: a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned software security protection methods for a multi-core SOC is implemented.

[0009] The beneficial effects of the present invention are: 1) Add a layer of CPU security protection module outside the CPU to detect the PC value range of all core requests. At the same time, cooperate with mem memory protection to effectively control the software operation boundary. Even if there are abnormalities or loopholes in the software, it can prevent illegal intrusion by hackers and viruses. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 The flowchart of the software security protection method for multi-core SOC is shown in FIG. DETAILED DESCRIPTION

[0011] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0012] See also Figure 1 The first aspect of the present invention provides: a software security protection method for a multi-core SOC, comprising the following steps: Add a layer of security protection module outside the CPU to detect the PC value range of all CPU core requests and cooperate with the mem memory control software running boundary; When the chip is powered on, the ROM is initialized and the chip initialization security configuration is read; the CPU is initialized using this configuration; The security module is loaded and the ROM verifies the signature of the security module. If the signature verification passes, the ROM loads and runs the security module; if the signature verification fails, the bus access is disabled. After the security module is loaded and run, the security module initializes the security configuration register and configures the security configuration items of all CPU cores. After the configuration is completed, the security module sets the pmp init done register to 1 to make the security configuration items effective. The security configuration items are only allowed to be modified after the next power-on; When a CPU core initiates a memory access request, the memory management module queries and compares whether it is within the address space range configured by it. If it is within the address space range configured by it, the CPU core is allowed to initiate a storage request bus access; if it is not within the address space range configured by it, the CPU core request is prohibited or an invalid address is returned; all requests to access SRAM and configuration space need to query the security configuration items through the memory management module.

[0013] In this embodiment, after the ROM signature verification security software (or firmware) passes, the security address range judgment module of the CPU WRAPPER is enabled. The security software (or firmware) configures the CPU WRAPPER security configuration register module during initialization. All CPU cores access the security configuration register module through the memory management module. This module uniformly manages the memory access of all CPU cores. Once the security enable bit in the configuration is set, all CPU cores need to access the memory after the query. That is, all CPU cores and other soc on-chip modules only accept access to this address range. After the configuration is completed, the pmpinit done register is configured to indicate that the configuration is effective, and the configuration is prohibited from being modified later to prevent non-security software from modifying the mem and hardware module registers in the soc chip. The security configuration register controls the memory management module. Each entry represents the access configuration of a single CPU core to the memory. The number of security configuration entries is greater than the number of CPU cores, thereby effectively controlling the access of each CPU core to the memory.

[0014] When each CPU core initiates a storage access request, it compares whether its request address is within the access range of the configuration space. Otherwise, the bus access request of the CPU core is prohibited or an invalid address is returned. If the configuration space comparison passes, the CPU core is allowed to access normally, and bus access and subsequent operations are initiated.

[0015] In some embodiments, the security module is security firmware or security software.

[0016] In some embodiments, the security configuration items include the access start address of each CPU core ID, the access interval size, the read, write and execute permissions for the access start address interval, and the security enable item is set to 1.

[0017] In this embodiment, after the signature verification is passed, the security software (or firmware) module is configured to control the access start address of each CPU core ID, the size of the access interval, the read, write and execute permissions of the address interval, the security enable item is set to 1, etc.

[0018] The second aspect of the present invention provides: a software security protection system for a multi-core SOC, which is used to implement any of the above-mentioned software security protection methods for a multi-core SOC, comprising: The security protection module is set outside the CPU to detect the PC value range requested by all CPU cores and cooperate with the mem memory control software to run the boundary; The initialization module is used to initialize the ROM and read the chip initialization security configuration after the chip is powered on; and use the configuration to initialize the CPU; The signature verification module is used to load the security module and use the ROM to verify the signature of the security module. If the signature verification passes, the ROM loads and runs the security module; if the signature verification fails, the bus access is disabled; A configuration module is used to load and run the security module, use the security module to initialize the security configuration register, and configure the security configuration items of all CPU cores. After the configuration is completed, the security module sets the pmp init done register to 1 to make the security configuration items effective. The security configuration items are only allowed to be modified after the next power-on; The query module is used to query and compare whether a CPU core initiates a memory access request. If it is within the configured address space range, the CPU core is allowed to initiate a storage request bus access; if it is not within the configured address space range, the CPU core request is prohibited or an invalid address is returned; all requests to access SRAM and configuration space need to query the security configuration items through the memory management module.

[0019] The third aspect of the present invention provides: a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by a processor, any of the above-mentioned software security protection methods for a multi-core SOC is implemented.

[0020] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A software security protection method for a multi-core SOC, characterized in that: The following steps are involved: Add a layer of security protection module outside the CPU to detect the PC value range of all CPU core requests and cooperate with the mem memory control software running boundary; When the chip is powered on, the ROM is initialized and the chip initialization security configuration is read; the CPU is initialized using this configuration; The security module is loaded and the ROM verifies the signature of the security module. If the signature verification passes, the ROM loads and runs the security module. If the signature verification fails, the bus access is disabled. After the security module is loaded and run, the security module initializes the security configuration register and configures the security configuration items of all CPU cores. After the configuration is completed, the security module sets the pmp init done register to 1 to make the security configuration items effective. The security configuration items are only allowed to be modified after the next power-on; When a CPU core initiates a memory access request, the memory management module queries and compares whether it is within the configured address space range. If it is within the configured space address range, the CPU core is allowed to initiate a storage request bus access; If it is not within the address range of its configured space, the CPU core request is prohibited or an invalid address is returned; all requests to access SRAM and configuration space need to query the security configuration items through the memory management module.

2. The software security protection method for a multi-core SOC according to claim 1, characterized in that: The security module is security firmware or security software.

3. The software security protection method for a multi-core SOC according to claim 1, characterized in that: The security configuration items include the access start address of each CPU core ID, the access interval size, the read, write and execute permissions for the access start address interval, and the security enable item is set to 1.

4. A software security protection system for a multi-core SOC, characterized in that: A method for implementing software security protection of a multi-core SOC as claimed in any one of claims 1 to 3, comprising: The security protection module is set outside the CPU to detect the PC value range requested by all CPU cores and cooperate with the mem memory control software to run the boundary; The initialization module is used to initialize the ROM and read the chip initialization security configuration after the chip is powered on; and use the configuration to initialize the CPU; The signature verification module is used to load the security module and use the ROM to verify the signature of the security module. If the signature verification passes, the ROM loads and runs the security module; if the signature verification fails, the bus access is disabled; A configuration module is used to load and run the security module, use the security module to initialize the security configuration register, and configure the security configuration items of all CPU cores. After the configuration is completed, the security module sets the pmp init done register to 1 to make the security configuration items effective. The security configuration items are only allowed to be modified after the next power-on; The query module is used to query and compare whether a CPU core initiates a memory access request. If it is within the configured address space range, the CPU core is allowed to initiate a storage request bus access; if it is not within the configured address space range, the CPU core request is prohibited or an invalid address is returned; all requests to access SRAM and configuration space need to query the security configuration items through the memory management module.

5. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are loaded and executed by the processor, the software security protection method for the multi-core SOC as described in any one of claims 1-3 is implemented.

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