A reliability evaluation method for internal interconnect solder joints in stacked package chips

Abstract

The present invention belongs to the technical field of solder joint reliability evaluation, and specifically relates to a reliability evaluation method for internal interconnect solder joints of stacked packaged chips. It includes the following: characterization of basic performance, extraction of structural and material parameters of interconnect solder joints of stacked packaged chips; reliability simulation analysis and simulation verification of internal interconnect solder joints of stacked packaged chips; reliability stress test assessment analysis of internal interconnect solder joints of stacked packaged chips; reliability performance degradation and defect characterization of internal interconnect solder joints of stacked packaged chips; and construction of reliability quantitative indicators of interconnect solder joints of stacked packaged chips. The present invention reveals the failure mechanism, microstructure evolution and performance degradation law of internal interconnect solder joints of stacked packaged chips, analyzes the key factors and structural parameters that affect the reliability level of internal interconnect solder joints, obtains the optimal structural combination parameters through reliability simulation analysis and simulation verification as well as reliability stress test assessment analysis, and forms reliability quantitative indicators.

Description

Technical Field

[0001] The present invention belongs to the technical field of solder joint reliability evaluation, and in particular relates to a reliability evaluation method for internal interconnect solder joints of a stacked package chip. Background Art

[0002] As electronic components continue to develop towards high density, miniaturization and integration, the packaging form is also constantly advancing from two-dimensional packaging to 3D stacked packaging chips. 3D stacked packaging chips are different from traditional packaging technology. This technology enables the component package to have an interconnected structure of multi-layer solder ball arrays inside.

[0003] When the external ambient temperature changes, the internal interconnect solder joints of the stacked packaged chip will be mismatched in thermal expansion coefficients between the chip, solder joints and PCB materials. Multiple reflow processes during the packaging process will cause the internal interconnect solder joints to remelt. Under the action of mechanical stress, the deformation of the upper and lower substrates will cause uneven stress on the solder joints, which will easily lead to solder joint reliability loss.

[0004] Internal solder joints, as key components of the stacked chip's mechanical connection and electrical signal transmission path, largely determine its reliability. However, the underlying mechanisms of defect formation and evolution at the interface of internal solder joints in stacked chips are unclear, and a lack of assessment and evaluation methods has significantly hindered the development of stacked chip packaging technology and its end-use applications.

[0005] Therefore, it is an indispensable technical reserve to establish a reliability evaluation method for the internal interconnect solder joints of stacked packaged chips, reveal the failure mechanism and microstructure evolution law of the internal interconnect solder joints of stacked packaged chips, establish quantitative reliability indicators for product quality control and screening assessment of the internal interconnect solder joints of stacked packaged chips, realize product reliability optimization, and ensure the final application of the product. Summary of the Invention

[0006] The purpose of the present invention is to provide a reliability evaluation method for internal interconnect solder joints of stacked packaged chips, which is used for reliability evaluation of internal interconnect solder joints of stacked packaged chips and for constructing reliability quantitative indicators for quality control and screening assessment.

[0007] To solve the above technical problems, the present invention provides a reliability evaluation method for internal interconnect solder joints of stacked package chips, comprising the following steps:

[0008] Step S1: characterization of basic performance of interconnect solder joints of stacked package chips, and extraction of structural and material parameters;

[0009] The basic performance parameter characterization includes but is not limited to the flatness, bonding strength and electrical properties of the internal interconnect solder joints; the structural parameters include the overall dimensions, upper and lower substrate dimensions, pad dimensions, solder ball diameter and spacing, interface morphology and IMC thickness, assembly process parameters and other structural parameters necessary for the establishment of the simulation model; the structural parameter extraction can be achieved through 3D-X-ray analysis, longitudinal section and scanning electron microscopy or transmission electron microscopy characterization structure analysis methods; the material parameters include the chip package cover, outer frame, upper and lower substrates, solder balls and package base structure, specifically including the density, Young's modulus, Poisson's ratio, specific heat capacity and thermal conductivity physical parameters of the materials involved in the structure;

[0010] Step S2: Simulation analysis and verification of the reliability of the internal interconnect solder joints of the stacked package chip; that is, based on the basic performance characterization, structural and material parameter results of the interconnect solder joints in step S1, an interconnect structure model for simulation analysis is established; by changing structural parameters that affect the reliability level of the internal interconnect solder joints, such as the thickness of the upper and lower substrates and the size of the solder ball pads, the reliability differences under corresponding different stress conditions are simulated and analyzed; the structural parameters that affect the reliability level of the internal interconnect solder joints can be determined based on the product's own structural characteristics, design evaluation, and engineering verification data;

[0011] Step S3: reliability stress test assessment and analysis of the internal interconnect solder joints of the stacked package chip; the stress test assessment and analysis object should be based on the simulation analysis and simulation verification results, and the top three structural parameter combinations ranked by reliability level should be selected, and the reliability stress test assessment and analysis should be carried out simultaneously;

[0012] Step S4: characterizing reliability performance degradation and defects of interconnect solder joints within the stacked package chip; the reliability performance degradation results can be extracted by using flatness testing, electrical performance testing, bonding strength testing, and shear strength testing methods during different reliability stress test assessment time periods, and further analyzing the data to obtain reliability performance degradation patterns;

[0013] Step S5: Constructing reliability quantitative indicators of the interconnect solder joints of the stacked package chip; based on the reliability simulation analysis and simulation verification and reliability test assessment analysis results, combined with the interconnect solder joint reliability performance degradation law and defect mechanism analysis, the optimal structural combination parameters are obtained as the reliability quantitative indicators.

[0014] Preferably, the simulation analysis of reliability under different stress conditions in step S2 includes combinations of all different structural parameters.

[0015] Preferably, the corresponding different stress conditions should be determined by the environmental profile during the manufacturing, assembly and application of the product or the sensitive stress existing in the product design itself.

[0016] Preferably, the object of the reliability stress test assessment analysis can be increased or selected according to actual application requirements or other requirements to conduct reliability stress test assessment analysis.

[0017] Preferably, the object of the reliability stress test assessment analysis can be designed and prepared by combining the extraction results of the structural parameters in step S1 with the simulation analysis and simulation verification results to conduct reliability stress test assessment analysis on engineering samples with consistent structure.

[0018] Preferably, the stress conditions for reliability test assessment analysis include stress conditions used in reliability simulation analysis and simulation verification.

[0019] Preferably, the stress test assessment analysis of the reliability of the internal interconnect solder joints of the stacked package chip is terminated based on the failure or obvious performance degradation of the object of the stress test assessment analysis.

[0020] Preferably, in step S4, the reliability performance degradation and defect characterization of the interconnect solder joints within the stacked package chip require monitoring of the growth thickness and micromorphology changes of the intermetallic compound IMC layer at the interconnect interface.

[0021] Preferably, in step S4, the reliability performance degradation and defect characterization of the internal interconnect solder joints of the stacked package chip are performed, and the interconnect solder joint defect characterization is performed by 3D-X-ray, red ink staining test, and SEM analysis after longitudinal sectioning.

[0022] Preferably, the reliability quantitative index of the interconnection solder joints of the stacked package chip can be used as a control index for quality control and screening assessment of mass-produced products.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] (1) In the present invention, a complete reliability evaluation process is established through parameter extraction, simulation analysis and simulation verification, stress test assessment analysis, reliability performance degradation and defect characterization, and the construction of reliability quantitative indicators, which helps to improve the accuracy of the reliability evaluation of the internal interconnect solder joints of the stacked package chip.

[0025] (2) In the present invention, with the help of reliability simulation analysis and simulation verification and reliability stress test assessment analysis, various structural parameters and combinations that affect the reliability level of internal interconnect solder joints are evaluated, which helps to comprehensively evaluate the reliability of internal interconnect solder joints of stacked package chips.

[0026] (3) In the present invention, the extraction results of structural parameters can be combined with simulation analysis and simulation verification results to design and prepare structurally consistent engineering samples for reliability stress test assessment and analysis, which is helpful for targeted verification of influencing factors and cost control during the implementation process.

[0027] (4) In the present invention, the reliability stress test conditions are determined by the environmental profile during the manufacturing, assembly and application of the product or the sensitive stress existing in the product design itself, taking into account the actual application environment, and the evaluation results are more accurate and reliable.

[0028] (5) In the present invention, it is proposed to establish a product quality control and screening assessment reliability quantitative index based on reliability simulation analysis and simulation verification as well as reliability test assessment analysis results, which is beneficial to the long-term stability monitoring of product quality and reliability improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 The figure is a flow chart of the reliability evaluation method of the internal interconnect solder joints of a typical stacked package chip according to the present invention.

[0030] Figure 2 Schematic diagram of the typical stacked package chip interconnection structure of the present invention.

[0031] Figure 3 The figure is a schematic diagram of the cross-sectional microstructure of the internal interconnection solder joints of a typical stacked package chip of the present invention.

[0032] Figure 4 The figure is a schematic diagram of the typical reliability stress test assessment, reliability performance degradation monitoring and defect characterization process of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0034] like Figures 1 to 4As shown, an embodiment of the present invention specifically provides a reliability evaluation method for internal interconnect solder joints of stacked packaged chips, the method comprising: characterizing and extracting basic performance, structure and material parameters of interconnect solder joints of a specific stacked packaged chip; establishing an interconnect structure model for simulation analysis based on the results of the characterization of basic performance, structure and material parameters of the interconnect solder joints; using the simulation structure model, changing the structural parameters that affect the reliability level of the internal interconnect solder joints, and simulating and analyzing the differences in reliability under corresponding different stress conditions when different structural parameter combinations are used; selecting the top three structural parameter combinations with the highest reliability level after simulation analysis and simulation verification, and simultaneously conducting reliability stress test assessment analysis; further analyzing the interconnect solder joint reliability performance degradation law and defect mechanism during the stress test assessment process to obtain the optimal structural combination parameters; obtaining and establishing product quality control and screening assessment reliability quantitative indicators based on the reliability simulation analysis and simulation verification as well as the reliability test assessment analysis results.

[0035] The technical solution of the embodiment of the present invention specifically includes the following steps:

[0036] Step 1: Characterization of basic performance, structure and material parameter extraction of interconnect solder joints of stacked package chips;

[0037] Step 2: Simulation analysis and verification of reliability of internal interconnect solder joints of stacked package chips;

[0038] Step 3: Reliability stress test and analysis of the internal interconnect solder joints of the stacked package chip;

[0039] Step 4: Reliability performance degradation and defect characterization of internal interconnect solder joints of stacked package chips;

[0040] Step 5: Construction of quantitative indicators of reliability of interconnect solder joints of stacked package chips.

[0041] like Figure 2 As shown in the figure, the typical stacked package chip interconnection structure mainly includes a cover plate, an outer frame, an inner chip, an upper organic substrate, internal interconnection solder joints, a lower organic substrate, a package base plate, and external interconnection solder joints;

[0042] The present invention is mainly used for reliability evaluation of internal interconnection solder joints in a stacked package chip interconnection structure.

[0043] Specifically, in step 1, structural parameters can be extracted by optical microscopy, X-ray, 3D-X-ray, visual inspection inside the package, cross-sectional analysis, SEM / EDS analysis, TEM analysis and other technical means;

[0044] like Figure 3As shown, the thickness of the upper and lower organic substrates, the diameter of the upper and lower pads of the internal solder joints, the coating material and thickness, the diameter and spacing of the internal and external solder balls, the material composition, the IMC interface morphology and thickness and other parameters can be obtained.

[0045] The extraction of basic performance parameters can be achieved through test methods such as flatness test, bonding strength test and electrical performance test.

[0046] Physical material parameters such as density, Young's modulus, Poisson's ratio, specific heat capacity and thermal conductivity can be extracted by consulting formal literature or conducting material performance analysis.

[0047] In step 2, the establishment of the reliability simulation analysis model should be based on the basic performance characterization, structure and material parameter extraction results of the stacked package chip interconnect solder joints to ensure the accuracy of the model establishment;

[0048] Reliability simulation analysis and simulation verification: Before implementation, the structural parameters that affect the reliability level of internal interconnect solder joints should be fully analyzed;

[0049] Reliability simulation analysis and verification: Before implementation, research and analysis should be conducted on the environmental profile during product manufacturing, assembly, and application, or the sensitive stresses inherent in the product design itself;

[0050] Based on the research and analysis results, determine the stress type and conditions to be applied in simulation analysis and verification;

[0051] In step 2, simulation analysis and simulation verification should be carried out to simulate the reliability of all combinations of different structural parameters under different stress conditions;

[0052] Evaluate the top three structural parameter combinations in terms of reliability level, or the structural parameter combinations that meet specific application requirements.

[0053] like Figure 4 As shown, the object of reliability stress test assessment and analysis can be the top three structural parameter combinations, or a special product with structural parameter combinations that meet specific application requirements, or a design and preparation of engineering samples with the same structure for reliability stress testing;

[0054] The assessment and analysis are mainly carried out through tests such as reflow soldering, temperature cycling, random vibration and other stress tests, and should include the stress conditions used in reliability simulation analysis and simulation verification.

[0055] In step 4, reliability performance degradation and defect characterization are performed using 3D X-ray characterization, flatness testing, electrical performance testing, IMC micro-analysis, bonding strength, and other test characterization methods during different reliability stress test assessment time periods.

[0056] Through further data analysis, the quantitative correspondence between different structural parameter combinations and solder joint reliability is analyzed, and the reliability performance degradation law is obtained.

[0057] In step 5, based on the reliability simulation analysis and verification, as well as the reliability test and analysis results, combined with the interconnect solder joint reliability performance degradation law and defect mechanism analysis, the optimal structural combination parameters are obtained to form a reliability quantitative index;

[0058] A quantitative indicator of the reliability of the interconnect solder joints of stacked package chips, used as a control indicator for quality control and screening assessment of mass-produced products.

[0059] In summary, the evaluation method of the present invention includes the steps of basic performance testing and structural parameter extraction of interconnect solder joints, reliability index simulation analysis and simulation verification, reliability stress test assessment analysis, reliability performance degradation and defect characterization, and construction of reliability quantitative indicators. This method extracts the basic performance and structural parameters of the interconnect solder joints of the stacked package chip, establishes a simulation analysis model, simulates stress fields such as reflow soldering, random vibration, and temperature cycling to simulate and verify the reliability of the internal interconnect solder joints of the stacked package chip, and screens the structural parameter combinations with the highest reliability level. Based on the simulation analysis results, a sensitive stress reliability test assessment is further designed and implemented, and with the help of 3D-X-ray non-destructive defect positioning; dye microcrack defect characterization; bond strength mechanical measurement and intermetallic compound (IMC) microscopic characterization technologies, the reliability degradation evaluation and defect characterization of the internal interconnect solder joints of the stacked package chip are realized, the failure mechanism, microstructure evolution and performance degradation law of the internal interconnect solder joints of the stacked package chip are revealed, and the optimal structural combination parameters are obtained to form a reliability quantitative indicator; providing support for the reliability evaluation of the internal interconnect solder joints of the stacked package chip and the control of product quality control and screening assessment.

[0060] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A reliability evaluation method for internal interconnect solder joints of stacked package chips, characterized in that: The steps include: Step S1: characterization of basic performance of interconnect solder joints of stacked package chips, and extraction of structural and material parameters; The basic performance parameter characterization includes but is not limited to the flatness, bonding strength and electrical properties of the internal interconnect solder joints; the structural parameters include the overall dimensions, upper and lower substrate dimensions, pad dimensions, solder ball diameter and spacing, interface morphology and IMC thickness, assembly process parameters and other structural parameters necessary for the establishment of simulation models; structural parameter extraction can be achieved through 3D-X-ray analysis, longitudinal sectioning and scanning electron microscopy or transmission electron microscopy characterization structural analysis methods; the material parameter extraction objects include the chip package cover, outer frame, upper and lower substrates, solder balls and package base, specifically including the density, Young's modulus, Poisson's ratio, specific heat capacity and thermal conductivity physical properties of the structural materials; Step S2: Simulation analysis and verification of the reliability of the internal interconnect solder joints of the stacked package chip; that is, based on the basic performance characterization, structural and material parameter results of the interconnect solder joints in step S1, an interconnect structure model for simulation analysis is established; by changing the thickness of the upper and lower substrates and the solder ball-to-pad size ratio, the structural parameters that affect the reliability level of the internal interconnect solder joints are simulated and analyzed, and the differences in reliability under corresponding different stress conditions are simulated; the structural parameters that affect the reliability level of the internal interconnect solder joints can be determined based on the product's own structural characteristics, design evaluation, and engineering verification data; Step S3: reliability stress test assessment and analysis of the internal interconnect solder joints of the stacked package chip; the stress test assessment and analysis object should be based on the simulation analysis and simulation verification results, and the structural parameter combinations ranked in the top three in reliability level according to the simulation verification results should be selected for reliability stress test assessment and analysis; Step S4: characterizing reliability performance degradation and defects of interconnect solder joints within the stacked package chip; the reliability performance degradation results can be extracted by using flatness testing, electrical performance testing, bonding strength testing, and shear strength testing methods during different reliability stress test assessment time periods, and further analyzing the data to obtain reliability performance degradation patterns; Step S5: Constructing reliability quantitative indicators of the interconnect solder joints of the stacked package chip; based on the reliability simulation analysis and simulation verification and reliability test assessment analysis results, combined with the interconnect solder joint reliability performance degradation law and defect mechanism analysis, the optimal structural combination parameters are obtained as the reliability quantitative indicators.

2. A reliability evaluation method for internal interconnect solder joints of a stacked package chip according to claim 1, characterized in that: The simulation analysis of reliability under different stress conditions in step S2 includes all combinations of different structural parameters.

3. A reliability evaluation method for internal interconnect solder joints of a stacked package chip according to claim 2, characterized in that: Different stress conditions should be determined by the environmental profiles during the product's manufacturing, assembly and application processes or the sensitive stresses inherent in the product design.

4. The reliability evaluation method for internal interconnect solder joints of a stacked package chip according to claim 1, wherein: The object of reliability stress test assessment analysis can be increased or selected according to actual application requirements or other requirements, and a specific structural parameter combination can be added to conduct reliability stress test assessment analysis.

5. The reliability evaluation method for internal interconnect solder joints of a stacked package chip according to claim 4, wherein: The object of the reliability stress test assessment analysis can be designed and prepared by combining the extraction results of the structural parameters in step S1 with the simulation analysis and simulation verification results to conduct reliability stress test assessment analysis on engineering samples with consistent structure.

6. The reliability evaluation method for internal interconnect solder joints of a stacked package chip according to claim 4, wherein: The stress conditions for reliability test assessment and analysis include the stress conditions used in reliability simulation analysis and simulation verification.

7. The reliability evaluation method for internal interconnect solder joints of a stacked package chip according to claim 4, wherein: The stress test assessment and analysis of the reliability of the internal interconnect solder joints of the stacked package chip has a deadline based on the occurrence of failure or obvious performance degradation of the object of the stress test assessment and analysis.

8. The reliability evaluation method for internal interconnect solder joints of a stacked package chip according to claim 1, wherein: In step S4, the reliability performance degradation and defect characterization of the interconnect solder joints within the stacked package chip require monitoring of the growth thickness and micromorphology changes of the intermetallic compound IMC layer at the interconnect interface.

9. The reliability evaluation method for internal interconnect solder joints of a stacked package chip according to claim 1, wherein: In the step S4, the reliability performance degradation and defect characterization of the interconnection solder joints within the stacked package chip are performed, and the interconnection solder joint defect characterization is performed by 3D-X-ray, red ink staining test, and SEM analysis after longitudinal sectioning.

10. The reliability evaluation method for internal interconnect solder joints of a stacked package chip according to claim 1, wherein: The reliability quantitative index of the interconnect solder joints of the stacked package chip can be used as a control index for quality control and screening assessment of mass-produced products.

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