Combinational logic loop detection and optimization method and system based on register insertion

Abstract

The present invention discloses a combinational logic loop detection and optimization method and system based on register insertion, which identifies strongly connected components and all loops therein in a directed graph model of a combinational logic circuit, then performs oscillation characteristic analysis on each loop, identifies oscillating strongly connected components, and then optimizes by inserting registers and disconnecting the loop; each iteration preferentially selects the loop with the least number of adjacent loops, selects the edge with the most occurrences in the loop and inserts the register; finally outputs the optimized circuit design information. The present invention can quickly and accurately detect and optimize combinational logic loops that may cause oscillations, significantly improves the reliability and efficiency of digital circuit design, and achieves global minimization of the number of register insertions.

Description

Technical Field

[0001] The invention relates to digital circuit simulation and optimization technology, in particular to a combinational logic loop detection and optimization method and system based on register insertion. Background Art

[0002] As the complexity of integrated circuit design continues to increase, the number of logic cells and signal connections contained in digital circuits increases year by year, making simulation and verification face huge challenges. Digital circuit simulation is an indispensable and important part of circuit design, and its purpose is to verify the correctness of logical functions through simulators. However, in actual design, complex combinational logic circuits may accidentally introduce combinational logic loops, especially in top-level interconnection and module optimization, which may cause simulation errors or circuit function failure.

[0003] Combinational logic loops are divided into two types: positive feedback and negative feedback. Positive feedback loops are stable in some specific circuits (such as latches and memory cells), while negative feedback loops may cause the signal to continuously flip, which in turn causes oscillation. This oscillation will not only cause the simulator to enter an infinite loop, causing a sharp increase in running time, but also significantly increase circuit power consumption and even lead to the ultimate failure of the chip design. This problem is particularly serious in very large-scale integrated circuit (VLSI) design, especially in multiple module nesting and hierarchical design, where complex loop nesting is more likely to introduce difficult-to-detect oscillation paths.

[0004] These potentially oscillating combinational logic loops can be interrupted by inserting registers. However, existing register insertion algorithms are usually based on global cut points and do not fully consider the local characteristics in the nested structure of the loop, resulting in an excessive number of register insertions, increased design costs, and potential interference with the original circuit functions. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a combinational logic loop detection and optimization method and system based on register insertion, so as to solve the technical problem that traditional loop detection methods cannot efficiently handle loop oscillation and register insertion redundancy in complex circuits.

[0006] Technical solution: The combinational logic loop detection and optimization method based on register insertion described in the present invention comprises the following steps:

[0007] (1) Read the Verilog netlist file of the combinational logic circuit and extract the logic gate and signal topology information of the combinational logic circuit;

[0008] (2) establishing a directed graph model of the combinational logic circuit based on the logic gate and signal topology information, and identifying strongly connected components and all loops therein;

[0009] (3) Identify the oscillation characteristics of each loop based on the number of inverting gates in the loop, and obtain the strongly connected components that may oscillate, called oscillating strongly connected components; the inverting gate is a logic gate that has the function of inverting the input;

[0010] (4) For the strongly connected component of the oscillation, calculate the number of times each edge appears in all loops; for any loop in the strongly connected component of the oscillation, calculate the number of adjacent loops;

[0011] For any loop in the strongly connected component of the oscillation, the optimization is performed by inserting a register and disconnecting the loop; in each iteration, the loop with the least number of adjacent loops is preferentially selected, and the edge with the most occurrences in the loop is selected to be inserted into the register;

[0012] (5) Output optimized circuit design information, including the oscillating strongly connected component, the input conditions that make the oscillating strongly connected component oscillate, and the register insertion position.

[0013] Furthermore, in step (3), the oscillation characteristics of each loop are identified according to the number of inverting operation gates in the loop, and the strongly connected components that may oscillate are obtained, which are called oscillation strongly connected components, including:

[0014] If all loops in a strongly connected component are odd loops, then the strongly connected component is an oscillating strongly connected component;

[0015] If all loops in a strongly connected component are even loops, then the strongly connected component is a stable strongly connected component;

[0016] If the strongly connected component contains odd loops and even loops, the input conditions of the traversal circuit are used to determine whether there is an odd loop that oscillates. If there is at least one odd loop oscillating, the strongly connected component is an oscillating strongly connected component; an odd loop refers to a loop containing an odd number of reverse operation gates, and an even loop refers to a loop containing an even number or zero reverse operation gates.

[0017] Furthermore, if the strongly connected component includes an odd ring and an even ring, it is determined whether there is an odd ring that oscillates by traversing the input conditions of the circuit. If there is at least one odd ring oscillating, the strongly connected component is an oscillating strongly connected component including:

[0018] Identify the common nodes of all loops in the strongly connected component of the oscillation and the connection relationship between the common nodes and the odd and even loops;

[0019] Starting from the common node, traverse each node. If the node belongs to an even ring, mark it as non-oscillating. If the node belongs to an odd ring, recursively search the signal input condition of its parent node until the input condition that makes all odd rings oscillate is found, and the strongly connected component is the oscillating strongly connected component. If all odd rings cannot be satisfied, the strongly connected component is the oscillating strongly connected component until the input condition that makes at least one odd ring oscillate and has the largest number of oscillation gates is found. If at least one odd ring cannot be satisfied, the strongly connected component is the stable strongly connected component.

[0020] Furthermore, in step (2), establishing a directed graph model of a combinational logic circuit according to the logic gate and signal topology information includes:

[0021] Each logic gate is regarded as a node of a directed graph, and the connection relationship of the signal is regarded as a directed edge, so as to establish a directed graph model of the logic circuit.

[0022] Furthermore, in step (2), the Tarjan algorithm is used to identify strongly connected components in the directed graph model, and the Johnson algorithm is used to identify all loops in the strongly connected components.

[0023] Furthermore, in step (1), the logic gate and signal topology information of the combinational logic circuit includes: the type of logic gate, the name of the input and output ports, and the signal flow relationship.

[0024] The combinational logic loop detection and optimization system based on register insertion of the present invention comprises:

[0025] A circuit information extraction unit, used for reading the Verilog netlist file of the combinational logic circuit and extracting the logic gate and signal topology information of the combinational logic circuit;

[0026] A loop identification unit, used to establish a directed graph model of the combinational logic circuit according to the logic gate and signal topology information, and identify strongly connected components and all loops therein;

[0027] The oscillation characteristic analysis unit is used to identify the oscillation characteristics of each loop according to the number of inverting operation gates in the loop, and obtain the strongly connected components that may oscillate, called the oscillation strongly connected components; the inverting operation gate is a logic gate with an input inverting operation;

[0028] The register insertion unit is used to calculate the number of occurrences of each edge in all loops of the oscillating strongly connected component; and for any loop in the oscillating strongly connected component, calculate the number of its adjacent loops;

[0029] For any loop in the strongly connected component of the oscillation, the optimization is performed by inserting a register and disconnecting the loop; in each iteration, the loop with the least number of adjacent loops is preferentially selected, and the edge with the most occurrences in the loop is selected to be inserted into the register;

[0030] The optimized circuit design information output unit is used to output the optimized circuit design information, including the strongly connected components that may oscillate, the input conditions that make the strongly connected components that may oscillate oscillate, and the register insertion positions.

[0031] Furthermore, in the oscillation characteristic analysis unit, if all loops in the strongly connected component are odd loops, then the strongly connected component is an oscillating strongly connected component;

[0032] If all loops in a strongly connected component are even loops, then the strongly connected component is a stable strongly connected component;

[0033] If the strongly connected component contains odd loops and even loops, then the input conditions of the traversal circuit are used to determine whether there is an odd loop that oscillates. If at least one odd loop oscillates, then the strongly connected component is an oscillating strongly connected component; wherein an odd loop refers to an odd number of reverse operation gates in the loop, and an even loop refers to an even number or zero reverse operation gates in the loop;

[0034] If the strongly connected component includes an odd ring and an even ring, then judging whether there is an odd ring that oscillates by traversing the input conditions of the circuit, and if there is at least one odd ring oscillating, then the strongly connected component is an oscillating strongly connected component including:

[0035] Identify the common nodes of all loops in the strongly connected component of the oscillation and the connection relationship between the common nodes and the odd and even loops;

[0036] Starting from the common node, traverse each node. If the node belongs to an even ring, mark it as non-oscillating. If the node belongs to an odd ring, recursively search the signal input condition of its parent node until the input condition that makes all odd rings oscillate is found, and the strongly connected component is the oscillating strongly connected component. If all odd rings cannot be satisfied, the strongly connected component is the oscillating strongly connected component until the input condition that makes at least one odd ring oscillate and has the largest number of oscillation gates is found. If at least one odd ring cannot be satisfied, the strongly connected component is the stable strongly connected component.

[0037] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the combinational logic loop detection and optimization method based on register insertion is implemented.

[0038] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the register-insertion-based combinational logic loop detection and optimization method is implemented.

[0039] Beneficial effects: Compared with the prior art, the advantages of the present invention are: based on strongly connected component analysis and recursive register insertion, the present invention can efficiently identify the oscillation conditions in the loop, preferentially disconnect the key path, gradually reduce the number of registers used, significantly reduce the complexity and resource consumption of circuit design, and thus significantly improve the reliability and simulation efficiency of circuit design. Specifically:

[0040] (1) The present invention converts the circuit structure into a directed graph, combines the Tarjan algorithm and the Johnson algorithm to realize the search for strongly connected components and loops, and can quickly identify the loop structure in complex circuits, especially the decomposition and classification of nested loops with high efficiency;

[0041] (2) The present invention adopts a method combining an improved greedy strategy with recursive optimization, preferentially disconnecting the critical path and disconnecting the loop in ascending order of the number of adjacent rings. It can cope with extremely complex topologies and still ensure the minimum number of insertions.

[0042] (3) The present invention combines the characteristics of the oscillation of the combinational logic circuit and uses a conditional search algorithm to find the conditions for the oscillation of the most gates in the nested ring, and adopts a recursive implementation, which has low time complexity;

[0043] (4) The optimization results output by the present invention include register insertion positions, loop classification information, and oscillation conditions for subsequent design verification and application, which significantly improves the efficiency and stability of circuit simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a flow chart of the combinational logic loop detection and optimization method of the present invention.

[0045] Figure 2 Schematic diagram of the circuit structure in an embodiment of the present invention.

[0046] Figure 3 It is a directed graph in the embodiment of the present invention.

[0047] Figure 4 Schematic diagram of a strongly connected component structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0049] like Figure 1 As shown, the combinational logic loop detection and optimization method based on register insertion includes the following steps.

[0050] S1: Read circuit information through the VPI interface.

[0051] The Verilog simulator's VPI (Verilog Procedural Interface) programming language interface interacts with the C language program, reads the input Verilog netlist file, and extracts the circuit's logic gate connection information and signal topology. Circuit information includes the type of logic gate (such as AND gate, OR gate, NOT gate, etc.), input and output port names and their signal connection relationships, etc. During the simulation phase, signal values ​​are accessed and modified to build a preliminary data model and directed graph structure for the circuit, providing basic data for loop detection and optimization. The reference schematic generated based on the circuit information is shown in Figure 2 shown.

[0052] S2: Construct a circuit directed graph and extract loops.

[0053] According to the logic gate and signal information extracted in step S1, the signal name and logic gate name are used as the nodes of the graph, and directed edges are constructed according to the signal flow direction to form a directed graph model of the circuit, such as Figure 3 As shown, by analyzing the input-output relationship of the logic gate, it is ensured that the directed graph can accurately reflect the topological structure of the circuit.

[0054] The Tarjan algorithm is used to perform a depth-first search on the graph. By tracking the access time and backtracking path of the nodes, all strongly connected components (SCCs) in the circuit are identified, and the node set, signal name and logic gate type of each strongly connected component are recorded in detail, thus providing a basis for modular processing of complex circuits. Each strongly connected component represents a circuit structure that may have a closed loop.

[0055] For each strongly connected component, the Johnson algorithm is further used to traverse its internal structure one by one, extract all loops, and record in detail the logic gates, signal names and connection relationships involved in each loop. This loop information provides a key basis for oscillation characteristic analysis and loop optimization.

[0056] S3: Analyze the oscillation characteristics and classification of the loop.

[0057] According to the characteristics of the combinational logic gate, if all the loops in the strongly connected component are odd loops, then the strongly connected component is judged to be likely to oscillate; if all the loops are even loops, then the strongly connected component is judged to be unable to oscillate and is directly marked as a stable loop; for strongly connected components that contain both odd and even loops, a conditional search algorithm is further executed to perform oscillation analysis. Among them, an odd loop refers to an odd number of reverse operation gates in the loop, and an even loop refers to an even number or zero reverse operation gates in the loop; an inverting operation gate refers to a logic gate that has an input inverting operation, such as a NOT gate, or for a two-input NAND gate, when one of the inputs is fixed to 1, the other end input and output must be in opposite phases.

[0058] like Figure 4 As shown, the strongly connected component structure in this circuit shows multiple logic gates and signal paths. This strongly connected component contains three loops in total. The loop composed of U1, U2, U3, and U4 does not contain logic gates that cause logic inversion (such as NOT gates and NAND gates), forming a loop called an even loop, while the two loops composed of U1, U4, U5, U6, U7, and U10 and U4, U5, U6, U7, U8, U9, and U11 contain an odd number of logic gates that cause logic inversion, forming two loops called odd loops. Therefore, the conditional search algorithm is used for oscillation analysis.

[0059] The conditional search algorithm uses recursive search logic to quickly find the input conditions that can cause the most gates to continuously reverse. This method aims to ensure that more odd rings oscillate synchronously while ensuring that at least one odd ring maintains oscillation.

[0060] Specifically, the conditional search algorithm first identifies the common gates between the loops. U7 and U4 are the common gates of the two odd loops and the even loop. The algorithm starts with U7 first and tries to make the odd loop and the even loop compatible by setting the input signal (such as the control value condition of pin10). If pin10=1 is set, the odd loop can be oscillated. At this time, the remaining external inputs only need to be assigned non-control values ​​to achieve synchronous oscillation of the two odd loops. At this time, if the even loop contains other paths (such as the logic gates on w1), these gates can also be affected by the oscillation, thereby further increasing the number of oscillating gates. During the search process, if the current condition (such as pin10=1) cannot keep all odd loops (U1, U4, U5, U6, U7, U10 and the two odd loops composed of U4, U5, U6, U7, U8, U9, U11 in this embodiment) oscillating, the algorithm will recursively process the remaining signal paths and try other input condition combinations until the optimal input condition that can make the most gates oscillate is found. The number of oscillating gates under each input condition is recorded to compare the effects of different conditions. If the odd ring cannot oscillate, the algorithm will automatically jump to the next common gate (such as U4) to continue searching and repeat the above process. Finally, for each input condition, the algorithm records and outputs the combination of conditions that maintain the oscillation of the odd ring and has the largest number of oscillation gates to the oscillation circuit file for subsequent verification; if all possible input conditions cannot meet the oscillation requirements of at least one odd ring, the SCC is classified as a non-oscillating component and recorded in the stable circuit file.

[0061] By starting with the common gates first, recursively analyzing the compatibility of the signal path, and recording the input conditions of the maximum number of oscillating gates, this method achieves efficient classification of complex nested loops. At the same time, for the components that cannot form oscillations, the classification results provide a clear basis for further optimization design.

[0062] S4: Register insertion optimization based on the improved greedy strategy.

[0063] As the scale of digital circuit design expands, the loop structure in the strongly connected components becomes more complex, and the oscillation condition of a single loop may be closely related to multiple signal inputs. Although the simple greedy algorithm can quickly destroy the loop, it is easy to miss the global optimal register insertion strategy. The recursive search algorithm is less efficient when dealing with complex nested loops and is difficult to meet actual design requirements.

[0064] For the classified oscillating strongly connected components, the present invention proposes a register insertion algorithm based on an improved greedy strategy. First, the number of adjacent rings of each loop is counted, and the number of times each edge appears in each loop in the oscillating strongly connected component is counted. The loop with the least number of adjacent rings is preferentially selected as the disconnection target, and the register is preferentially inserted on the edge with the highest frequency in the loop to minimize the number of registers that need to be inserted. After each register is inserted, the adjacency information of all rings is updated, the disconnected rings are deleted, and the attributes of the nodes involved are adjusted. At the same time, for complex nested strongly connected components, a recursive optimization strategy is used to gradually decompose the nested structure. The process will continue to iterate until all rings are disconnected, and ultimately ensure that the number of inserted registers is minimized. It can effectively handle complex nested loop situations, thereby achieving global minimization of the number of register insertions.

[0065] Adjacent rings refer to two rings in a directed graph that have shared logic gates or common edges between them. In other words, if two rings have one or more identical logic gates or edges between them, then the two rings are adjacent.

[0066] against Figure 4 The oscillating strongly connected component can be easily obtained according to the improved greedy algorithm. Just insert a register at w4 to solve the problem that the oscillating strongly connected component will oscillate.

[0067] S5: Output optimized circuit design information.

[0068] After the optimization is completed, the optimized circuit design information is output to the file, including the register insertion position, the classification results of the oscillation loop, and the optimized signal topology structure. The output information is convenient for subsequent circuit verification and iterative design.

[0069] In order to verify the method of the present invention, the present invention and three scales of circuits were tested, wherein the 60-point test score consisted of whether the SCC loop could be correctly identified (15 points), whether the SCC was oscillating (15 points), the conditions under which the oscillating SCC could cause the most logic gates to oscillate (15 points), and the number of inserted logic gates (15 points). The results are shown in Table 1.

[0070] Table 1: Operation results of the combinational logic loop detection and optimization method of the present invention

[0071]

[0072] The results show that the combinational logic loop detection and optimization method based on strongly connected component analysis and register insertion effectively solves the oscillating loop problem within a reasonable algorithm running time, while significantly reducing the number of register insertions.

[0073] The combinational logic loop detection and optimization system based on register insertion of the present invention comprises:

[0074] A circuit information extraction unit, used for reading the Verilog netlist file of the combinational logic circuit and extracting the logic gate and signal topology information of the combinational logic circuit;

[0075] A loop identification unit, used to establish a directed graph model of the combinational logic circuit according to the logic gate and signal topology information, and identify strongly connected components and all loops therein;

[0076] The oscillation characteristic analysis unit is used to identify the oscillation characteristics of each loop according to the number of inverting operation gates in the loop, and obtain the strongly connected components that may oscillate, called the oscillation strongly connected components; the inverting operation gate is a logic gate with an input inverting operation;

[0077] The register insertion unit is used to calculate the number of occurrences of each edge in all loops of the oscillating strongly connected component; and for any loop in the oscillating strongly connected component, calculate the number of its adjacent loops;

[0078] For any loop in the strongly connected component of the oscillation, the optimization is performed by inserting a register and disconnecting the loop; in each iteration, the loop with the least number of adjacent loops is preferentially selected, and the edge with the most occurrences in the loop is selected to be inserted into the register;

[0079] The optimized circuit design information output unit is used to output the optimized circuit design information, including the strongly connected components that may oscillate, the input conditions that make the strongly connected components that may oscillate oscillate, and the register insertion position.

[0080] The electronic device described in the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, the combinational logic loop detection and optimization method based on register insertion is implemented.

[0081] The computer-readable storage medium of the present invention stores a computer program, and when the computer program is executed by a processor, the register-insertion-based combinational logic loop detection and optimization method is implemented.

[0082] The computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other media that can be used to store program code in the form of instructions or data structures and that can be accessed by a computer.

[0083] The processor is used to execute the computer program stored in the memory to implement each step of the method involved in the above embodiment.

Claims

1. A combinational logic loop detection and optimization method based on register insertion, characterized in that: The steps include: (1) Read the Verilog netlist file of the combinational logic circuit and extract the logic gate and signal topology information of the combinational logic circuit; (2) establishing a directed graph model of the combinational logic circuit based on the logic gate and signal topology information, and identifying strongly connected components and all loops therein; (3) Identify the oscillation characteristics of each loop based on the number of inverting gates in the loop, and obtain the strongly connected components that may oscillate, called oscillating strongly connected components; the inverting gate is a logic gate that has the function of inverting the input; (4) For the strongly connected component of the oscillation, calculate the number of times each edge appears in all loops; for any loop in the strongly connected component of the oscillation, calculate the number of adjacent loops; For any loop in the strongly connected component of the oscillation, the optimization is performed by inserting a register and disconnecting the loop; in each iteration, the loop with the least number of adjacent loops is preferentially selected, and the edge with the most occurrences in the loop is selected to be inserted into the register; (5) Output optimized circuit design information, including the oscillating strongly connected component, the input conditions that make the oscillating strongly connected component oscillate, and the register insertion position.

2. The combinational logic loop detection and optimization method based on register insertion according to claim 1, characterized in that: In step (3), the oscillation characteristics of each loop are identified according to the number of inverting operation gates in the loop, and the strongly connected components that may oscillate are obtained, which are called oscillation strongly connected components, including: If all loops in a strongly connected component are odd loops, then the strongly connected component is an oscillating strongly connected component; If all loops in a strongly connected component are even loops, then the strongly connected component is a stable strongly connected component; If the strongly connected component contains odd loops and even loops, the input conditions of the traversal circuit are used to determine whether there is an odd loop that oscillates. If there is at least one odd loop oscillating, the strongly connected component is an oscillating strongly connected component; an odd loop refers to a loop containing an odd number of reverse operation gates, and an even loop refers to a loop containing an even number or zero reverse operation gates.

3. The combinational logic loop detection and optimization method based on register insertion according to claim 2 is characterized in that: If the strongly connected component includes an odd ring and an even ring, then judging whether there is an odd ring that oscillates by traversing the input conditions of the circuit, and if there is at least one odd ring oscillating, then the strongly connected component is an oscillating strongly connected component including: Identify the common nodes of all loops in the strongly connected component of the oscillation and the connection relationship between the common nodes and the odd and even loops; Starting from the common node, traverse each node. If the node belongs to an even ring, mark it as non-oscillating. If the node belongs to an odd ring, recursively search the signal input condition of its parent node until the input condition that makes all odd rings oscillate is found, and the strongly connected component is the oscillating strongly connected component. If all odd rings cannot be satisfied, the strongly connected component is the oscillating strongly connected component until the input condition that makes at least one odd ring oscillate and has the largest number of oscillation gates is found. If at least one odd ring cannot be satisfied, the strongly connected component is the stable strongly connected component.

4. The combinational logic loop detection and optimization method based on register insertion according to claim 1, characterized in that: In step (2), establishing a directed graph model of a combinational logic circuit according to the logic gate and signal topology information includes: Each logic gate is regarded as a node of a directed graph, and the connection relationship of the signal is regarded as a directed edge, so as to establish a directed graph model of the logic circuit.

5. The combinational logic loop detection and optimization method based on register insertion according to claim 1, characterized in that: In step (2), the Tarjan algorithm is used to identify strongly connected components in the directed graph model, and the Johnson algorithm is used to identify all loops in the strongly connected components.

6. The combinational logic loop detection and optimization method based on register insertion according to claim 1, characterized in that: In step (1), the logic gate and signal topology information of the combinational logic circuit includes: the type of logic gate, the name of the input and output ports, and the signal flow relationship.

7. A combinational logic loop detection and optimization system based on register insertion, characterized in that: include: A circuit information extraction unit, used for reading the Verilog netlist file of the combinational logic circuit and extracting the logic gate and signal topology information of the combinational logic circuit; A loop identification unit, used to establish a directed graph model of the combinational logic circuit according to the logic gate and signal topology information, and identify strongly connected components and all loops therein; The oscillation characteristic analysis unit is used to identify the oscillation characteristics of each loop according to the number of inverting operation gates in the loop, and obtain the strongly connected components that may oscillate, called the oscillation strongly connected components; the inverting operation gate is a logic gate with an input inverting operation; The register insertion unit is used to calculate the number of occurrences of each edge in all loops of the oscillating strongly connected component; and for any loop in the oscillating strongly connected component, calculate the number of its adjacent loops; For any loop in the strongly connected component of the oscillation, the optimization is performed by inserting a register and disconnecting the loop; in each iteration, the loop with the least number of adjacent loops is preferentially selected, and the edge with the most occurrences in the loop is selected to be inserted into the register; The optimized circuit design information output unit is used to output the optimized circuit design information, including the strongly connected components that may oscillate, the input conditions that make the strongly connected components that may oscillate oscillate, and the register insertion positions.

8. The combinational logic loop detection and optimization system based on register insertion according to claim 7, characterized in that: In the oscillation characteristic analysis unit, if all loops in a strongly connected component are odd loops, then the strongly connected component is an oscillating strongly connected component; If all loops in a strongly connected component are even loops, then the strongly connected component is a stable strongly connected component; If the strongly connected component contains odd loops and even loops, then the input conditions of the traversal circuit are used to determine whether there is an odd loop that oscillates. If at least one odd loop oscillates, then the strongly connected component is an oscillating strongly connected component; wherein an odd loop refers to an odd number of reverse operation gates in the loop, and an even loop refers to an even number or zero reverse operation gates in the loop; If the strongly connected component includes an odd ring and an even ring, then judging whether there is an odd ring that oscillates by traversing the input conditions of the circuit, and if there is at least one odd ring oscillating, then the strongly connected component is an oscillating strongly connected component including: Identify the common nodes of all loops in the strongly connected component of the oscillation and the connection relationship between the common nodes and the odd and even loops; Starting from the common node, traverse each node. If the node belongs to an even ring, mark it as non-oscillating. If the node belongs to an odd ring, recursively search the signal input condition of its parent node until the input condition that makes all odd rings oscillate is found, and the strongly connected component is the oscillating strongly connected component. If all odd rings cannot be satisfied, the strongly connected component is the oscillating strongly connected component until the input condition that makes at least one odd ring oscillate and has the largest number of oscillation gates is found. If at least one odd ring cannot be satisfied, the strongly connected component is the stable strongly connected component.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the register insertion-based combinational logic loop detection and optimization method according to any one of claims 1 to 6 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the register insertion-based combinational logic loop detection and optimization method according to any one of claims 1 to 6 is implemented.

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