A mixed digital-analog simulation method and system for decoding modules based on V-ams language

Abstract

The present invention discloses a mixed digital-analog simulation method and system for a decoding module based on the V‑ams language. The simulation method includes the following steps: powering on an analog circuit and performing signal initialization on a decoding circuit of a chip under test; driving an advanced peripheral bus to configure registers; using a data file for stimulation and extracting data; performing data conversion on each channel signal to convert it into two differential signals with a phase difference of 180°; inputting the differential signal into a register transfer stage of an analog circuit for processing; the register transfer stage of the analog circuit processes the data and then outputs it to a register transfer stage of a digital circuit for decoding; collecting and transmitting data to a system control module; performing data comparison and displaying the results. The present invention realizes the joint simulation of digital and analog circuits, ensuring the consistency of the working timing of the analog and digital circuits.

Description

Technical Field

[0001] The present invention relates to a V-ams language-based digital-analog hybrid simulation method for a decoding module, and also relates to a corresponding digital-analog hybrid simulation system for a decoding module, belonging to the technical field of integrated circuit testing. Background Art

[0002] SoC (System on Chip) chip design integrates digital circuits, analog circuits, and microprocessors on a single silicon chip, building a complex system to achieve advanced functionality. With the widespread adoption of SoC chips, the interaction between digital and analog components has become increasingly prominent. Verification of this digital-analog interaction has become a critical and underresolved area in SoC chip verification, particularly during the simulation verification phase. This poses a challenge to the chip's overall performance and reliability.

[0003] With the increasing complexity of chip designs, hardware verification has become increasingly challenging, and verification time has also increased. An authoritative industry research report shows that only 39% of designs pass flawless silicon verification on the first try, while 60% contain logical or functional defects, and over 20% require three or more silicon verifications. Furthermore, verification accounts for approximately 50% of the total engineering time. Therefore, when evaluating and verifying mixed-signal SoCs, traditional standalone digital and analog simulators are no longer sufficient. Hybrid analog and digital simulation technology must be employed to address the challenges of synchronized mixed-signal simulation. To this end, many EDA vendors offer a co-simulation approach, linking an analog simulator and a digital simulator via a "platform." The digital portion is simulated using the digital simulator, while the analog portion is simulated using the analog simulator. The interface signals between the digital and analog portions are synchronized via the "platform." This verification approach improves simulation efficiency and enables simulation of the entire SoC system.

[0004] On the other hand, the single digital simulator is generally Synopsys's VCS, while the analog circuit is generally used by Cadence's XRun (or FinSim). The two are incompatible and cannot achieve simultaneous simulation of digital and analog circuits. However, simulating any independent circuit alone cannot check whether the logical relationship and timing of the two are correct. Figure 1 In a typical mixed-analog simulation system shown in the figure, the digital circuit simulator uses ncsim and the analog circuit uses xrun. Both tools belong to Cadence to solve compatibility issues. Summary of the Invention

[0005] The primary technical problem to be solved by the present invention is to provide a mixed digital-analog simulation method for a decoding module based on the V-ams language.

[0006] Another technical problem to be solved by the present invention is to provide a mixed digital-analog simulation system of a decoding module based on the V-ams language.

[0007] In order to achieve the above technical objectives, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, a method for mixed analog-digital simulation of a decoding module based on the V-ams language is provided, comprising the following steps:

[0009] Step 1: Power on the analog circuit and initialize the signal of the decoding circuit of the chip under test;

[0010] Step 2: Drive the high-level peripheral bus to configure registers;

[0011] Step 3: Use the data file for stimulation and extract data;

[0012] Step 4: Perform data conversion on the signals of each channel to convert them into two differential signals with a phase difference of 180°;

[0013] Step 5: Input the differential signal to the register transfer stage of the analog circuit for processing. After the register transfer stage of the analog circuit processes the data, it is output to the register transfer stage of the digital circuit for decoding operation.

[0014] Step 6: Data collection and transmission to the system control module;

[0015] Step 7: Compare data and display the results.

[0016] Preferably, the stimulus is a hexadecimal or decimal data file, which is shared by the register transfer stage of the digital circuit and the register transfer stage of the analog circuit.

[0017] Preferably, the signal initialization operation generates a stimulus input timing of a control signal required by an analog circuit, and controls data extraction to drive a register transfer stage of a digital circuit and a register transfer stage of an analog circuit using the same test vector.

[0018] Preferably, the register transfer stage of the analog circuit is implemented through an operational amplifier based on a Verilog-A model.

[0019] Preferably, the operation of performing data conversion on the signals of each channel includes offsetting the common-mode signal in the signal to serve as the first differential signal in the channel; then flipping the first differential signal with the common-mode signal as the center axis to serve as the second differential signal in the channel, so as to convert the signal of the same channel into two differential signals as a set of differential signals of the channel.

[0020] Preferably, each group of differential signals of each channel is de-jittered and DC is blocked, and then input into the register transfer stage of the analog circuit.

[0021] According to a second aspect of an embodiment of the present invention, a decoding module digital-analog hybrid simulation system based on the V-ams language is provided, comprising:

[0022] A system control module is communicatively connected with the adapter;

[0023] The adapter is communicatively connected to the bus function module and the test agent module respectively;

[0024] The bus function module is connected to the register transfer stage of the analog circuit, and the test agent module is connected to the register transfer stage of the digital circuit;

[0025] The register transfer stage of the digital circuit receives a signal of a test case, and the register transfer stage of the analog circuit receives a data signal of a data extraction circuit.

[0026] The data extraction circuit includes a data extraction module including a channel data processing module, a signal conversion module and a common-mode signal adjustment module, wherein the channel data processing module collects the aforementioned multi-channel analog signals and splits them into signals of each channel, and the signal conversion module converts the signals of each channel into digital signals; the common-mode signal adjustment module offsets the common-mode signal of the signal as the first differential signal in the channel; and then flips the first differential signal with the common-mode signal as the central axis as the second differential signal in the channel, so as to convert the signal of the same channel into two differential signals, which are output as a group of differential signals of the channel to the register transfer stage of the analog circuit.

[0027] Preferably, the register transfer stage of the analog circuit is responsible for processing analog signals; the register transfer stage of the digital circuit is responsible for processing digital signals;

[0028] During the simulation process, the register transfer stage of the analog circuit receives a control signal from the register transfer stage of the digital circuit to ensure that the behavior of the analog part meets the requirements of the digital control logic.

[0029] Preferably, the data extraction module extracts data from multiple channels by putting a hexadecimal or decimal data file into the simulation environment;

[0030] The data conversion module converts the extracted data of multiple channels into two differential signals with a phase difference of 180 degrees, and sends the differential signals to the register transfer stage of the analog circuit.

[0031] Preferably, in the register transfer stage of the analog circuit, each set of differential signal inputs of each channel is used as the control timing, the bus driver generates an excitation signal according to the test case for processing, and outputs it to the register transfer stage of the digital circuit for decoding.

[0032] Compared with the prior art, the present invention has significant advantages in the simulation of digital plus analog logic functions of differential signal type encrypted data. By using Cadence's ncsim and xrun tools, the present invention realizes the joint simulation of digital circuits and analog circuits, ensuring the consistency of the working timing of analog circuits and digital circuits. In addition, the present invention can convert multi-bit data into two differential signals for input, and collect the data of the analog circuit through the digital circuit to evaluate the analog parameter indicators such as the working power consumption and performance of the analog circuit, thereby ensuring the correctness and performance matching of the two-end interaction. At the same time, the present invention also provides a joint simulation environment of digital Verilog and analog nc_verilog, which supports the simulation of various ideal waveform files, randomly generated waveform files, and real card waveform files, etc., thereby enhancing the flexibility and practicality of the simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the logical structure of an analog and digital hybrid simulation platform in the first embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of real data collected in an embodiment of the present invention;

[0035] Figure 3 Schematic diagram of a differential signal obtained by data conversion in an embodiment of the present invention;

[0036] Figure 4 FIG. 1 is a schematic diagram of a data extraction circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] The technical concept of the present invention is to co-simulate digital modules and analog circuits to ensure consistency in interface definitions, operating timing, and state transitions between the two ends. The analog circuit's operating performance indicators are then verified to ensure correct interaction and performance matching between the analog and digital circuits. Furthermore, differential signaling is used to ensure the security of confidential data.

[0039] First embodiment

[0040] Figure 1This is a schematic diagram of the logical structure of a V-ams-based decoding module mixed analog-digital simulation system (hereinafter referred to as the "simulation system") provided by the first embodiment of the present invention. The simulation system is used to perform mixed analog and digital simulation on differential signal input decoding SoC chips.

[0041] The ports of this type of SoC chip are capable of receiving differential input signals. Differential signaling is a common signal transmission method, in which the two signals are the same but have opposite polarities. In the SoC chip, these differential input signals are first received and processed by the analog circuit part. Then, the received analog signal is converted into a digital signal after preliminary processing by the analog circuit inside the SoC chip. These digital signals are then digitally decoded by the digital logic circuit to extract useful information or perform specific digital processing tasks. For example, digital logic decoding may include signal amplification, filtering, comparison, counting and other operations. The information decoded by the digital logic may need to be fed back to the analog circuit to control the behavior of the analog circuit, such as adjusting the amplitude, frequency or other characteristics of the analog signal to meet specific application requirements.

[0042] Common-mode feedback (CMFB) is crucial in SoCs that decode differential signal inputs. This mechanism stabilizes the output common-mode level, ensuring the chip is unaffected by device characteristics and mismatches, thereby guaranteeing signal integrity and circuit performance. Therefore, simulating common-mode feedback becomes a key feature of these SoCs, and accordingly, differential signal processing becomes a key focus.

[0043] Combine Figure 1 and Figure 4 The simulation system includes a system control module (SCB) and an adapter in communication connection; the adapter is respectively in communication connection with a bus function module (bus) and a test agent module (agent); the bus function module is connected to the register transfer level (Register Transfer Level) of the analog circuit, and the test agent module is connected to the register transfer level (Register Transfer Level) of the digital circuit; the register transfer level of the digital circuit receives the signal of the test case (test-case), and the register transfer level of the analog circuit receives the data signal of the data extraction circuit.

[0044] The register transfer stage of the analog circuit processes analog signals, such as voltage and current, which are typically generated by the analog circuits. The register transfer stage of the digital circuit processes digital signals, such as logic levels and clock signals, which are generated by the digital circuits. During simulation, the register transfer stage of the analog circuit receives control signals from the register transfer stage of the digital circuit to ensure that the analog part behaves in accordance with the requirements of the digital control logic.

[0045] The register transfer level of the digital circuit collects chip signals generated by test cases. These signals simulate various input conditions that the actual chip may encounter during operation and are used to verify the correctness and robustness of the chip design.

[0046] The analog circuit's register transfer stage receives data signals from the data extraction circuit. The data extraction circuit comprises a data extraction module and a data conversion module. The data extraction module extracts data from three channels from a hexadecimal or decimal data file placed in the simulation environment. The data conversion module converts the extracted data from the three channels into two differential signals with a 180° phase difference, which are then sent to the analog circuit's register transfer stage.

[0047] In mixed-analog simulation, the coordination of the bus function module (BFM) and the register transfer level (RTL) of the digital circuit is crucial. The RTL handles the digital logic, while the BFM provides the interface between analog and digital logic. This coordination ensures that analog signals are correctly converted to digital signals.

[0048] BFM includes bus driver (bus-drv) and bus monitor (bus-monitor), which are used to encapsulate the timing of the low-level bus and provide a calling interface for the high-level bus.

[0049] The bus driver (bus-drv) is responsible for generating stimulus signals based on the test case and sending them to the register transfer stage of the analog circuit. It simulates the external signals that the chip may receive during actual operation, such as input data and control signals. By accurately simulating these signals, the bus driver ensures that the register transfer stage of the analog circuit responds to the expected stimulus, thereby verifying its functionality and performance.

[0050] The bus monitor is responsible for monitoring the output signals of the register transfer level of the analog circuit. It captures the responses generated by the RTL and compares them with the expected results. If any inconsistencies are found, the bus monitor records these differences for subsequent analysis and debugging. This real-time monitoring helps to promptly identify and locate problems, thereby improving the accuracy and reliability of the simulation. The bus monitor monitors data from multiple (for example, three) channels and packages and organizes the collected information and transmits it to the adapter, which then transmits it to the system control module. The data of the three channels corresponds to three channel monitors, and each channel monitor is only responsible for monitoring one set of buses.

[0051] The test agent module (Agent) includes an agent driver (Agent-drv) and an agent monitor (Agent-monitor). The agent driver is responsible for generating stimuli, while the agent monitor is responsible for monitoring the action of the digital circuit and collecting the data decoded by the digital decoding circuit.

[0052] In conventional digital verification platforms, an agent driver (Agent-DRV) is required to generate stimulus signals based on test cases and transparently transmit signals generated by the analog circuit's register transfer stage to the digital circuit's register transfer stage. In a simulation platform (Testbench), analog circuit output signals are directly connected to digital circuit input ports, and vice versa. This defines the connection between analog and digital circuits, achieving transparent signal transmission and thus omitting the agent driver (Agent-DRV).

[0053] During simulation, the agent monitor is responsible for monitoring the output signals and decoded data of the digital circuit's register transfer stage. The agent monitor captures the responses generated by the digital circuit's register transfer stage and collects the decoded data into a data queue. The data packets are then piped to the system control module, where they are compared with expected results. The agent monitor also performs real-time timing checks on some control signals. If any inconsistencies are detected, the agent monitor records these discrepancies for subsequent analysis and debugging. This real-time monitoring helps promptly identify and locate problems, thereby improving simulation accuracy and reliability.

[0054] Therefore, the test agent module (Agent) simulates a specific communication protocol to ensure that signals strictly adhere to the protocol when transmitted between the register transfer level of the analog circuit and the register transfer level of the digital circuit. This means that whether it is data format, timing requirements, or error handling mechanisms, the agent can ensure that the behavior of the register transfer level of the digital circuit meets the predetermined protocol standards. This strict protocol compliance check helps prevent problems caused by protocol misunderstandings or errors, ensuring the accuracy of simulation results.

[0055] The bus monitor and proxy monitor transmit signals to the system control module through the adapter. The system control module compares the data of multiple (for example, three) channels (from the bus monitor) with the decoded data (from the proxy monitor) and displays the comparison results.

[0056] The system control module manages and controls various operations during the simulation process. It communicates with the adapter, passing simulation control signals or test vectors to the adapter. The adapter acts as a bridge between the simulation platform and the device under test (DUT), ensuring that signals are correctly converted between different interfaces and protocols.

[0057] Second embodiment

[0058] Next, in conjunction with the above-mentioned V-ams language-based decoding module digital-analog mixed simulation system, a V-ams language-based decoding module digital-analog mixed simulation method provided by the second embodiment of the present invention is introduced.

[0059] As mentioned previously, this V-ams-based decoding module mixed-analog simulation system uses nc_verilog as a platform, enabling interactive simulation of digital and analog nc_verilog. nc_verilog compilers, such as ncvlog, are used to compile Verilog source files, generating intermediate files required for simulation. The compiled design is described using the ncelab tool, generating simulation snapshots. These snapshots are then simulated using ncsim. During the simulation process, waveforms can be viewed and debugged using tools such as SimVision.

[0060] The present invention uses Cadence VAMS and Verilog-A to create a hybrid analog and digital simulation environment capable of processing both digital and analog circuits. This allows verification of the interaction between digital and analog circuits on the same simulation platform, eliminating the need for separate test platforms for each.

[0061] In Cadence, create Verilog-A models for analog circuits and Verilog code for digital circuits. Define the electrical characteristics and behavior of the circuit for the analog circuit model, describe the behavioral model of the analog circuit, and define input / output ports for the digital circuit code.

[0062] The simulation platform (Testbench) serves as the top-level module for the interaction between analog and digital circuits. Verilog modules for digital circuits and Verilog-A models for analog circuits are instantiated within the Testbench. The aforementioned simulation system is used to generate test stimulus signals, drive the DUT, and collect response data. The Testbench provides code for signal initialization, test sequencing, and monitoring and analyzing circuit responses.

[0063] Mixed-analog simulation requires defining the interface between digital and analog circuits. This involves creating Connect Modules, which define the correspondence between digital logic levels and analog voltage levels. Defining interfaces and connection rules involves converting voltages and logic levels. In Cadence, you can use Connect Rules to define these conversions.

[0064] refer to Figure 2 To accurately simulate a voltage-source-controlled SoC chip, this embodiment of the present invention uses the Verilog-A language and Cadence software coding to create a simulation environment. The VAMS tool enables seamless integration between analog and digital circuits, and transmits key interface signals to the testbench layer for effective signal driving and data acquisition. For power consumption and performance analysis, the $cgav function in Verilog-A is used to collect current values ​​from the power supply VDD interface, from which the module's power consumption and performance parameters are calculated. Furthermore, other analog parameters, such as voltage and flip-flop time, can be acquired through monitoring.

[0065] To ensure the accuracy of the simulation data, the actual waveform files were specially processed: using a conversion model written in VAMS, these waveform files were converted into ADC differential signals for simulation. This ensured consistency between the simulation results and the actual chip test results. In pursuit of simulation efficiency, the clock module was also optimized by replacing it with an ideal source using the VAMS model, simplifying the simulation process and improving efficiency.

[0066] More importantly, embodiments of the present invention convert encrypted multi-bit data into differential signals, improving the signal's anti-interference capabilities and, to a certain extent, minimizing the risk of encrypted data being eavesdropped or leaked. A differential signal is a signal transmitted on two transmission lines with the same amplitude but opposite phase. When external interference affects these two lines, since the interference is typically the same on both lines, the receiving end determines the logical state of the transmission by comparing the voltage difference between the two lines. This effectively offsets the effects of the external interference and maintains signal integrity and accuracy. In encrypted data transmission scenarios, using differential signaling ensures that even if data is intercepted during transmission, the anti-interference properties of differential signals make it difficult for unauthorized recipients to recover valid data from the interference, thereby protecting data security. Furthermore, the physical properties of differential signals also help prevent signal leakage. Because the voltage difference of differential signals is small, their electromagnetic radiation in space is also relatively low, making contactless signal interception more difficult. Therefore, the present invention is particularly suitable for applications requiring high security, such as the military and financial sectors. In these fields, the security performance of chips is of vital importance. The present invention can ensure the security and reliability of chips used in these security-sensitive applications during the design and verification stages.

[0067] The second embodiment of the present invention provides a mixed digital-analog simulation method for a decoding module based on the V-ams language, which includes at least the following steps.

[0068] Step 1: Power on the analog circuit and initialize the signal of the decoding circuit of the chip under test.

[0069] In this step, the analog circuit is powered on, and the signal initialization operation is completed for the digital DUT (ie, the SoC chip model under test) through the driver in the digital environment.

[0070] By completing the signal initialization operation on the digital decoding circuit controller, the stimulus input timing of the control signal required for the register transfer level of the analog circuit is generated to control the extraction of data (such as the signal generated by the bus driver according to the test case). Therefore, the same test vector can be used to drive the digital circuit and the analog circuit to ensure that the interface definition, working timing, state jump, etc. at both ends are consistent, thereby ensuring the consistency of the test.

[0071] Table 1: Test function point decomposition table (test vector example)

[0072]

[0073] Step 2: Drive the high-level peripheral bus to configure registers.

[0074] TEST_CASE uses the bus driver (bus_drv) to drive the Advanced Peripheral Bus (APB) to read and write registers, configure the digital circuit controller, initialize parameters, and generate analog circuit control signal input stimuli. This can be achieved by adding corresponding control logic in the testbench.

[0075] Step 3: Use the data file for stimulation and extract data.

[0076] A data file (txt format) containing hexadecimal or decimal data as stimulus is placed in the simulation environment to drive analog and digital logic circuits. This hexadecimal or decimal data file can be shared by both the register transfer level (RTL) of the digital circuit and the register transfer level of the analog circuit. This data file reuse reduces the need for duplicate test vector development and ensures test data consistency.

[0077] In the Testbench, read the data of the hexadecimal or decimal data file into the fscanf function (a function in C language used to format and read data from the file and store the data in appropriate variables), then convert it into an analog signal through a DAC and give it to the differential signal (see Figure 3 ) and uses it as test stimulus. This allows the data extraction circuit to extract the required data from the file during simulation and provide it to the digital DUT. Here, the data extraction circuit extracts data from multiple (e.g., three) channels to prevent data serialization. Figure 2 An example of actually extracting data is provided in .

[0078] Specifically, if Figure 4 As shown, the data extraction module includes a channel data processing module, a signal conversion module, and a common-mode signal adjustment module, which are connected in sequence. The channel data processing module collects the aforementioned multi-channel analog signals and splits them into data to obtain individual channel signals (channel 1 split data, channel 2 split data, and channel 3 split data). This splits the multi-channel signals into individual channel signals for separate processing.

[0079] Step 4: Perform data conversion on the signals of each channel to convert them into two differential signals with a phase difference of 180°.

[0080] like Figure 3As shown, the signal conversion module includes analog-to-digital conversion channel 1, analog-to-digital conversion channel 2, and analog-to-digital conversion channel 3. Based on connection rules (connrules), the signal conversion module converts the signals in each channel into digital signals. Select the most appropriate connrule mode based on the specific simulation requirements and circuit characteristics. For example, if the circuit is very sensitive to analog load effects, you may need to select full mode for more accurate simulation. If you have high requirements for simulation speed but the circuit is not sensitive to load effects, you can choose basic mode to speed up the simulation process.

[0081] In the common mode signal adjustment module, the common mode part of the signal (common mode signal) is offset to serve as the first differential signal in the channel; the first differential signal is then flipped around the common mode signal as the center axis to serve as the second differential signal in the channel. Therefore, after the common mode signal adjustment, the signal in the same channel is converted into two differential signals (see Figure 3 ), meaning each channel has a set of differential signals. Common-mode signals are the signal components present in both channels of a differential signal. Adjusting the common-mode signal can improve the signal's ability to resist interference.

[0082] More preferably, each set of differential signals of each channel is de-jittered and DC is blocked before being input into the register transfer stage of the analog circuit.

[0083] Through the above steps, the present invention can convert the analog signals of each channel into differential signals for simulation. In this way, the signal processing process is not affected by the quantization range or interference, so the accuracy of the simulation results is guaranteed.

[0084] Step 5: Input the differential signal to the register transfer stage of the analog circuit for processing. After the register transfer stage of the analog circuit processes the data, it is output to the register transfer stage of the digital circuit for decoding operation.

[0085] In the analog circuit's register transfer stage, each set of differential signals from each channel is input into the register transfer stage of the circuit to be simulated as control timing. This generates stimulus signals for the bus driver based on the test case and processes them. After the register transfer stage of the circuit to be simulated completes processing, the register transfer stage of the digital circuit is activated. The register transfer stage of the digital circuit collects the data output by the register transfer stage of the analog circuit and performs subsequent decoding processing.

[0086] Usually, when performing analog simulation, it can only be performed according to the quantization range of the internal analog-to-digital converter (ADC). Therefore, due to this limitation, it is impossible to input actual encrypted data. However, in the embodiment of the present invention, the operational amplifier is used to realize the splitting, conversion and amplitude adjustment of the collected multi-channel data based on the Verilog-A model (see Figure 4 ), is not affected by the quantization range and can convert encrypted data into differential signals for simulation, thus ensuring the correctness of the simulation results.

[0087] Step 6: Data collection and transmission to the system control module.

[0088] Use Agent-monitor to monitor the digital demodulated data and transmit the collected data to the system control module. In Testbench, you can write code to write the processed data to the monitoring tool.

[0089] The digital circuit's register transfer stage collects the analog circuit's register transfer stage output data and decodes it for testing and verification. This acquisition mechanism ensures that the analog circuit output can be analyzed on the digital test platform, thus ensuring the consistency of test indicators.

[0090] Step 7: Compare data and display the results.

[0091] Use tools provided by Cadence (such as SimVision) to view and analyze simulation results and check whether the interaction between digital and analog circuits is as expected.

[0092] Specifically, the system control module compares the known decoded data (provided by the algorithm model) with the decoded data received from the Agent-Monitor test. If they match, the comparison is considered passed and a "pass" message is displayed on the simulation screen. If they differ, a "pass" message is displayed. This can be achieved by adding appropriate checking logic to the Testbench.

[0093] In summary, the above steps create a mixed-signal simulation environment using Cadence's VAMS and Verilog-A. This simulation environment is capable of processing both digital and analog circuits. Because VAMS is an extension of Verilog, it allows simulation of continuous-time physical systems, such as analog circuits and mixed-signal systems, supporting the modeling and simulation of analog circuits. It can also co-simulate with digital logic circuits, allowing the simultaneous processing of analog and digital signals within the same simulation environment.

[0094] These steps achieve consistent test metrics by integrating digital and analog circuit testing on the same simulation platform, allowing the use of the same test vectors and test tools. This approach not only improves test efficiency but also reduces design issues caused by inconsistent test environments.

[0095] Moreover, the present invention can compile analog schematics and digital verliog simultaneously, and perform interactive simulation of both at the digital-analog level to obtain real simulation data. It can also reuse the verification platform of the digital module, reduce the amount of code writing, be compatible with analog design test vectors, ensure the consistency of test indicators and the graphical interface simulation parameters of the Cadence tool, and facilitate problem reproduction.

[0096] It should be noted that Figure 1 The Bus_monitor and Agent_drv are used during digital circuit verification and are not required during the simulation process of the various embodiments of the present invention, so they can be omitted. However, because the digital platform is directly reused in each embodiment, the digital platform can have the same structure as the digital-analog hybrid simulation system in each embodiment of the present invention, which can reduce costs (compared to the case of using a structure different from the digital platform).

[0097] This invention targets the simulation of specific SoC chips, specifically, hybrid digital-analog simulation of SoC chips with analog differential inputs, digital logic decoding, and analog feedback. Preliminary data processing includes differential signal processing, enabling simulation of actual card waveform data. Test vectors can be shared with digital simulation platforms, enabling simulation and re-enactment of product issues.

[0098] It should be noted that the above embodiments are merely examples. The technical solutions of the various embodiments can be combined, and the order of the steps can be changed, all within the scope of protection of this patent.

[0099] The above describes in detail the V-ams language-based mixed analog-digital simulation method and system for a decoding module provided by the present invention. For those skilled in the art, any obvious modifications made thereto without departing from the essence of the present invention will constitute an infringement of the present invention's patent rights and will result in corresponding legal liability.

Claims

1. A mixed analog-digital simulation method for a decoding module based on V-ams language, characterized in that The following steps are involved: Step 1: Power on the analog circuit and initialize the signal of the decoding circuit of the chip under test; Step 2: Drive the high-level peripheral bus to configure registers; Step 3: Use the data file for stimulation and extract data; Step 4: Perform data conversion on the signals of each channel to convert them into two differential signals with a phase difference of 180°; Step 5: Input the differential signal to the register transfer stage of the analog circuit for processing. After the analog circuit register transfer stage processes the data, it outputs it to the register transfer stage of the digital circuit for decoding. The response generated by the register transfer stage of the digital circuit is captured and the decoded data is collected and placed in the data queue. The data packet is then transmitted to the system control module through the pipeline and compared with the expected result. Step 6: Based on the Verilog-A model, the collected multi-channel data is split, converted, and amplitude adjusted to realize data collection and transmit it to the system control module; Step 7: The system control module compares the data from multiple channels with the decoded data and displays the results. The stimulus is a hexadecimal or decimal data file, which is shared by the register transfer stage of the digital circuit and the register transfer stage of the analog circuit; The data extraction module extracts data from multiple channels from a hexadecimal or decimal data file placed in the simulation environment. The data conversion module converts the extracted data from multiple channels into two differential signals with a phase difference of 180°, and sends them to the register transfer stage of the analog circuit. The signal initialization operation generates a stimulus input timing of a control signal required by the analog circuit and controls data extraction to drive the register transfer stage of the digital circuit and the register transfer stage of the analog circuit using the same test vector; Each group of differential signals of each channel is debounced and DC is blocked before being input into the register transfer stage of the analog circuit.

2. The V-ams language-based mixed digital-analog simulation method for a decoding module according to claim 1, characterized in that: The register transfer stage of the analog circuit is implemented through an operational amplifier based on a Verilog-A model.

3. The V-ams language-based decoding module digital-analog hybrid simulation method according to claim 2, characterized in that The operations for data conversion of each channel signal include: The common-mode signal in the signal is offset to serve as the first differential signal in the channel; the first differential signal is then flipped around the common-mode signal as the center axis to serve as the second differential signal in the channel, thereby converting the signal of the same channel into two differential signals as a set of differential signals for the channel.

4. A hybrid digital-analog simulation system for decoding modules based on V-ams language, characterized in that include: A system control module is communicatively connected with the adapter; The adapter is communicatively connected to the bus function module and the test agent module respectively; The bus function module is connected to the register transfer stage of the analog circuit, and the test agent module is connected to the register transfer stage of the digital circuit; The register transfer stage of the digital circuit receives a signal of a test case, and the register transfer stage of the analog circuit receives a data signal of a data extraction circuit. The data extraction circuit includes a data extraction module including a channel data processing module, a signal conversion module and a common-mode signal adjustment module, wherein the channel data processing module collects multi-channel analog signals and splits them into signals of each channel, and the signal conversion module converts the signals of each channel into digital signals; the common-mode signal adjustment module offsets the common-mode signal of the signal as the first differential signal in the channel; and then flips the first differential signal with the common-mode signal as the central axis as the second differential signal in the channel, so as to convert the signal of the same channel into two differential signals, which are output as a group of differential signals of the channel to the register transfer stage of the analog circuit. The V-ams language-based decoding module digital-analog mixed simulation system is used to implement the V-ams language-based decoding module digital-analog mixed simulation method as described in any one of claims 1 to 3.

5. The V-ams language-based decoding module digital-analog hybrid simulation system according to claim 4, characterized in that: The register transfer stage of the analog circuit is responsible for processing analog signals; the register transfer stage of the digital circuit is responsible for processing digital signals; During the simulation process, the register transfer stage of the analog circuit receives a control signal from the register transfer stage of the digital circuit to ensure that the behavior of the analog part meets the requirements of the digital control logic.

6. The V-ams language-based decoding module digital-analog hybrid simulation system according to claim 5, characterized in that: The data extraction module extracts data from multiple channels using a hexadecimal or decimal data file placed in the simulation environment; The data conversion module converts the extracted data of multiple channels into two differential signals with a phase difference of 180 degrees, and sends the differential signals to the register transfer stage of the analog circuit.

7. The V-ams language-based decoding module digital-analog hybrid simulation system according to claim 6, characterized in that: In the register transfer stage of the analog circuit, each set of differential signal inputs of each channel is used as the control timing, and the bus driver generates stimulus signals according to the test case for processing and output to the register transfer stage of the digital circuit for decoding.

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