Display system and operating method for display system

Abstract

The invention provides a display system and an operation method for the display system. The display system comprises a first display and a second display; the first display comprises a first input port and a first output port; the second display comprises a second output port, a detection circuit, a processor and a connection prompt circuit; the detection circuit responds to the driving signal to drive the second output port; the processor receives a detection signal located at the second output port and judges the connection state of the second output port according to the level of the detection signal; the connection prompting circuit controls the second display to output a connection prompting picture according to the connection state. According to the display system and the operation method for the display system provided by the invention, the second display can detect the connection state between the first display and the second display and provide the connection prompt picture according to the connection state, so that the connection prompt picture can be provided under the condition of wrong connection. The second display can provide a connection prompt picture to guide the user to perform correct connection.

Description

Technical Field

[0001] The present invention relates to an electronic system and an operating method for the electronic system, and in particular to a display system and an operating method for the display system. Background Art

[0002] With the development of display technology, there are more usage scenarios. The multi-screen connection of multiple displays can bring a wide viewing angle, better immersion, and multi-window display and processing. The multi-screen connection of multiple displays has become a necessary requirement for multi-business operations in industries such as office, games, and film and television. However, with the high complexity of multiple displays, multiple interfaces, and multiple connections, it is difficult for users to identify multiple input and output interfaces of multiple displays. Therefore, the probability of connection errors will increase. In the case of a connection error, the display can only display abnormal images such as a black screen or a black screen. Users can only keep groping or trying different connection methods until the multi-screen connection of multiple displays is correct and displayed normally. Therefore, the multi-screen connection of multiple displays reduces the user's experience. It can be seen that how to provide a display system that can detect the connection status between multiple displays and provide a connection prompt screen based on the connection status is one of the research focuses of technicians in this field.

[0003] Therefore, it is necessary to provide a display system and an operating method for the display system to solve the above problems. Summary of the invention

[0004] The invention provides a display system and an operating method for the display system, which can detect the connection status between multiple displays and provide a connection prompt screen according to the connection status.

[0005] A display system according to an embodiment of the present invention includes a first display and a second display. The first display includes a first input port and a first output port. The second display includes a second output port, a detection circuit, a processor, and a connection prompt circuit. The detection circuit is coupled to the second output port. The detection circuit drives the second output port in response to a drive signal. The processor is coupled to the second output port. The processor receives a detection signal at the second output port and determines the connection status of the second output port according to the level of the detection signal. The connection prompt circuit is coupled to the processor. The connection prompt circuit controls the second display to output a connection prompt screen according to the connection status. The level of the detection signal changes according to one of the second output port being idling, the second output port being connected to the first input port, and the second output port being connected to the first output port.

[0006] An operating method according to an embodiment of the present invention is used for a display system. The display system includes a first display and a second display. The first display includes a first input port and a first output port. The second display includes a second output port. The operating method includes: driving the second output port in response to a driving signal; receiving a detection signal at the second output port, and determining the connection state of the second output port according to the level of the detection signal, wherein the level of the detection signal changes according to one of the second output port being vacant, the second output port being connected to the first input port, and the second output port being connected to the first output port; and controlling the second display to output a connection prompt screen according to the connection state.

[0007] Based on the above, the processor of the second display determines the connection status of the second output port according to the level of the detection signal. The connection prompt circuit of the second display controls the second display to output a connection prompt screen according to the connection status. Therefore, the second display can detect the connection status between the first display and the second display, and provide a connection prompt screen according to the connection status. In this way, in the case of a connection error, the second display can provide a connection prompt screen to guide the user to make a correct connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of a display system according to an embodiment of the present invention.

[0009] Figure 2 is a flow chart of an operating method according to an embodiment of the present invention.

[0010] Figure 3 It is a schematic diagram of a first output port, a first input port, a detection circuit and a second output port according to an embodiment of the present invention.

[0011] Figure 4 is a waveform diagram drawn according to an embodiment of the present invention.

[0012] Figure 5 is a schematic diagram illustrating a correct connection according to an embodiment of the present invention.

[0013] Figure 6 is based on Figure 5 The waveform diagram is shown.

[0014] Figure 7 FIG. 4 is a schematic diagram of an incorrect connection according to an embodiment of the present invention.

[0015] Figure 8 is based on Figure 7 The waveform diagram is shown.

[0016] Fig. 9It is a schematic diagram of a detection circuit, a first output port and a second output port according to an embodiment of the present invention.

[0017] Fig.10 is a state diagram according to an embodiment of the present invention.

[0018] Fig.11 is a flow chart of an operating method according to an embodiment of the present invention.

[0019] Fig.12 It is a schematic diagram of a connection prompt screen according to an embodiment of the present invention.

[0020] Main component symbols:

[0021] 100 Display System

[0022] 110 First Display

[0023] 120 Second Display

[0024] 111, 121 detection circuit

[0025] 1111, 1211 pull-up circuit

[0026] 1112, 1212 pull-down circuit

[0027] 122 processors

[0028] 123 Connection reminder circuit

[0029] IMGP connection prompt screen

[0030] P1~P5 Tips

[0031] PIN_1 First input port

[0032] POUT_1 First output port

[0033] POUT_2 Second output port

[0034] R_1 Output resistor

[0035] R_2 Input resistor

[0036] R_3, R_5 pull-up resistors

[0037] R_4, R_6 pull-down resistors

[0038] S100, S200 operation method

[0039] S110, S120, S130 steps

[0040] Steps S210 to S290

[0041] SDR, SDR' drive signal

[0042] SDT Heartbeat

[0043] SST connection status signal

[0044] ST Connection Status

[0045] ST0 Start connection state

[0046] ST1 First connection state

[0047] ST2 Second connection status

[0048] T1 output

[0049] T2 Input

[0050] TC Connector

[0051] VH1, VH2 reference high voltage

[0052] VL1, VL2 reference low voltage DETAILED DESCRIPTION

[0053] Some embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. The referenced element symbols in the following description will be regarded as the same or similar elements when the same element symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More specifically, these embodiments are only examples within the scope of the patent application of the present invention.

[0054] Please refer to Figure 1 , Figure 1 is a schematic diagram of a display system according to an embodiment of the present invention. In this embodiment, the display system 100 includes a first display 110 and a second display 120. The first display 110 can be a sink display. The second display 120 can be a source display. The first display 110 can receive a signal from the second display 120 to provide audio and video services. The first display 110 includes a first input port PIN_1 and a first output port POUT_1.

[0055] In this embodiment, the second display 120 includes a second output port POUT_2, a detection circuit 121, a processor 122, and a connection prompt circuit 123. The detection circuit 121 is coupled to the second output port POUT_2. The detection circuit 121 drives the second output port POUT_2 in response to the driving signal SDR. The processor 122 is coupled to the second output port POUT_2. In this embodiment, the level of the detection signal SDT changes according to one of the second output port POUT_2 being floating, the second output port POUT_2 being connected to the first input port PIN_1, and the second output port POUT_2 being connected to the first output port POUT_1. The processor 122 receives the detection signal SDT at the second output port POUT_2. The processor 122 determines the connection state ST of the second output port POUT_2 according to the level of the detection signal SDT. The connection prompt circuit 123 is coupled to the processor 122. The connection prompt circuit 123 controls the second display 120 to output the connection prompt screen IMGP according to the connection state ST.

[0056] It is worth mentioning here that the processor 122 determines the connection state ST of the second output port POUT_2 according to the level of the detection signal SDT. The connection prompt circuit 123 controls the second display 120 to output the connection prompt screen IMGP according to the connection state ST of the second output port POUT_2. Therefore, the second display 120 can detect the connection state ST between the first display 110 and the second display 120, and provide the connection prompt screen IMGP according to the connection state ST. In this way, in the case of a connection error, the second display 120 can provide the connection prompt screen IMGP to guide the user to make a correct connection.

[0057] The first display 110 and the second display 120 can be any type of display or a display unit disposed in an electronic device. The first input port PIN_1, the first output port POUT_1 and the second output port POUT_2 are, for example, display ports (DP), but the invention is not limited thereto.

[0058] In this embodiment, the driving signal SDR may be provided by the processor 122 (however, the present invention is not limited thereto). The driving signal SDR is, for example, a signal having a duty cycle. The processor 122 is, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor (Microprocessor), digital signal processor (Digital Signal Processor, DSP), programmable controller, application specific integrated circuits (Application Specific Integrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD) or other similar devices or a combination of these devices, which can load and execute computer programs.

[0059] For example, when the second output port POUT_2 is idling, the detection signal SDT has a first high level and a first low level. When the second output port POUT_2 is connected to the first input port PIN_1, the detection signal SDT has a second high level and a second low level. When the second output port POUT_2 is connected to the first output port POUT_1, the detection signal SDT has a third high level and a third low level. The first high level, the second high level, and the third high level are not exactly the same. The first low level, the second low level, and the third low level are not exactly the same. Therefore, the processor 122 can know the connection state ST of the second output port POUT_2 based on the high level of the detection signal SDT and the low level of the detection signal SDT. The processor 122 provides a connection state signal SST corresponding to the connection state ST of the second output port POUT_2.

[0060] In this embodiment, the connection prompt circuit 123 receives the connection status signal SST and controls the second display 120 according to the connection status signal SST.

[0061] For example, when the connection status signal SST corresponds to the first connection state where the second output port POUT_2 is connected to the first input port PIN_1, this indicates that the connection of the second output port POUT_2 is correct. The connection prompt circuit 123 can control the second display 120 to provide a connection prompt screen IMGP indicating that the second output port POUT_2 is correctly connected to the first input port PIN_1, or not to provide the connection prompt screen IMGP.

[0062] For another example, when the connection status signal SST corresponds to the second output port POUT_2 being unconnected, the connection prompt circuit 123 may control the second display 120 to provide a connection prompt screen IMGP indicating that the second output port POUT_2 is unconnected, or not provide the connection prompt screen IMGP.

[0063] For another example, when the connection status signal SST corresponds to the second connection state in which the second output port POUT_2 is connected to the first output port POUT_1, this indicates that the connection of the second output port POUT_2 is incorrect. Therefore, the connection prompt circuit 123 controls the second display 120 according to the connection status signal SST, so that the second display 120 provides a connection prompt screen IMGP to guide the user to make a correct connection. In this example, the connection prompt screen IMGP is, for example, a pop-up prompt screen for connecting the second output port POUT_2 to the first input port PIN_1 in a "pop-up" manner (however, the present invention is not limited thereto). In this way, when an incorrect connection occurs, the second display 120 can instantly "pop up" the connection prompt screen IMGP. The user can view the connection prompt screen IMGP and correctly connect the second output port POUT_2 to the first input port PIN_1.

[0064] Please also refer to Figure 1 as well as Figure 2 , Figure 2 It is a flow chart of an operation method illustrated according to an embodiment of the present invention. The operation method S100 is applicable to the display system 100. The operation method S100 includes steps S110, S120, and S130. In step S110, the detection circuit 121 drives the second output port POUT_2 in response to the drive signal SDR. In step S120, the processor 122 receives the detection signal SDT located at the second output port POUT_2, and determines the connection status ST of the second output port POUT_2 according to the level of the detection signal SDT. In step S130, the connection prompt circuit 123 controls the second display 120 to output the connection prompt screen IMGP according to the connection status ST of the second output port POUT_2. The implementation examples of steps S110, S120, and S130 have been described in detail. Figure 1 This is clearly described in the embodiments, so it will not be repeated here.

[0065] Please also refer to Figure 1 as well as Figure 3 , Figure 3 It is a schematic diagram of a first output port, a first input port, a detection circuit and a second output port according to an embodiment of the present invention. Figure 3A schematic diagram of the first input port PIN_1 and the first output port POUT_1 of the first display 110 and the detection circuit 121 and the second output port POUT_2 of the second display 120 is shown.

[0066] In this embodiment, the first output port POUT_1 includes an output terminal T1 and an output resistor R_1. The output resistor R_1 is coupled between the output terminal T1 and a reference high voltage VH1 of the first display 110. The first input port PIN_1 includes an input terminal T2 and an input resistor R_2. The input resistor R_2 is coupled between the input terminal T2 and a reference low voltage VL1 of the first display 110.

[0067] In the present embodiment, the detection circuit 121 includes a pull-up circuit 1211, a pull-up resistor R_3, a pull-down resistor R_4, and a pull-down circuit 1212. The first end of the pull-up circuit 1211 is coupled to the reference high voltage VH2 of the second display 120. The control end of the pull-up circuit 1211 receives the driving signal SDR. The pull-up resistor R_3 is coupled between the second output port POUT_2 and the second end of the pull-up circuit 1211. The first end of the pull-down resistor R_4 is coupled to the second output port POUT_2. The first end of the pull-down circuit 1212 is coupled to the second end of the pull-down resistor R_4. The second end of the pull-down circuit 1212 is coupled to the reference low voltage VL2 of the second display 120. The control end of the pull-down circuit 1212 receives the driving signal SDR.

[0068] In the present embodiment, the voltage value of the reference high voltage VH2 is equal to the voltage value of the reference high voltage VH1. The voltage values ​​of the reference high voltages VH1 and VH2 are, for example, 3.3 volts (V), respectively, but the present invention is not limited thereto. The voltage value of the reference low voltage VL2 is equal to the voltage value of the reference low voltage VL1. The voltage values ​​of the reference low voltages VL1 and VL2 are, for example, 0V, respectively, but the present invention is not limited thereto.

[0069] In this embodiment, the pull-up circuit 1211 can be implemented by a P-type transistor. For example, the pull-up circuit 1211 can be implemented by a P-type MOS, but the present invention is not limited thereto. The pull-down circuit 1212 can be implemented by an N-type transistor. For example, the pull-down circuit 1212 can be implemented by an N-type MOS, but the present invention is not limited thereto.

[0070] In the present embodiment, the resistance value of the output resistor R_1, the resistance value of the pull-up resistor R_3, and the resistance value of the pull-down resistor R_4 are the same as each other. In addition, the resistance value of the input resistor R_2 is different from the resistance value of the output resistor R_1, the resistance value of the pull-up resistor R_3, and the resistance value of the pull-down resistor R_4. In the present embodiment, the resistance value of the input resistor R_2 is greater than the resistance value of the output resistor R_1, the resistance value of the pull-up resistor R_3, and the resistance value of the pull-down resistor R_4. For example, the resistance value of the input resistor R_2 is equal to 10 times the resistance value of the output resistor R_1, the resistance value of the pull-up resistor R_3, and the resistance value of the pull-down resistor R_4, but the present invention is not limited thereto. In one embodiment, the resistance value of the input resistor R_2 is less than the resistance value of the output resistor R_1, the resistance value of the pull-up resistor R_3, and the resistance value of the pull-down resistor R_4.

[0071] In this embodiment, the processor 122 receives a detection signal SDT at the connection terminal TC of the second output port POUT_2. When the detection signal SDT is inverted to the driving signal SDR, it means that the connection terminal TC of the second output port POUT_2 is not connected to the output terminal T1 of the first output port POUT_1 and the input terminal T2 of the first input port PIN_1. Therefore, the processor 122 provides a connection status signal SST corresponding to the second output port POUT_2 being idling.

[0072] Please also refer to Figure 1 , Figure 3 as well as Figure 4 , Figure 4 is a waveform diagram according to an embodiment of the present invention. In this embodiment, when the second output port POUT_2 is unconnected, the detection circuit 121 can be regarded as an inverter. Therefore, when the second output port POUT_2 is unconnected, the detection signal SDT has a low level (i.e., 0V) when the drive signal SDR is at a high level (i.e., 3.3V) and has a high level (i.e., 3.3V) when the drive signal SDR is at a low level (i.e., 0V). The processor 122 determines whether the second output port POUT_2 is unconnected based on the above waveform of the detection signal SDT.

[0073] Please also refer to Figure 1 , Figure 5 as well as Figure 6 , Figure 5 is a schematic diagram illustrating a correct connection according to an embodiment of the present invention. Figure 6 is based on Figure 5The waveform diagram depicted. In the present embodiment, when the second output port POUT_2 is connected to the first connection state of the first input port PIN_1, this indicates that the connection of the second output port POUT_2 is correct. It should be noted that when the second output port POUT_2 is connected to the first connection state of the first input port PIN_1, the pull-up resistor R_3 and the pull-down resistor R_4 are respectively connected to the input resistor R_2. The resistance value of the input resistor R_2 is greater than the resistance value of the pull-up resistor R_3 and the resistance value of the pull-down resistor R_4. Therefore, the voltage value of the low level of the detection signal SDT is equal to the voltage value of the reference low voltage VL. The voltage value of the high level of the detection signal SDT is divided based on the resistance value of the pull-up resistor R_3 and the resistance value of the input resistor R_2. Therefore, the voltage value of the high level of the detection signal SDT is between the voltage value of the intermediate voltage value and the voltage value of the reference high voltage VH. The intermediate voltage value is the intermediate value (ie, 1.65V) of the voltage value of the reference low voltage VL (ie, 0V) and the voltage value of the reference high voltage VH (ie, 3.3V). The processor 122 will Figure 6 The waveform of the detection signal SDT is used to provide a connection status signal SST corresponding to that the second output port POUT_2 is correctly connected to the first input port PIN_1.

[0074] For example, the resistance value of the input resistor R_2 is designed to be 10 times the resistance value of the pull-up resistor R_3 (but the present invention is not limited thereto). Therefore, the voltage value of the high level of the detection signal SDT is, for example, 3V.

[0075] In other words, when the driving signal SDR is at a low level, the voltage value of the high level of the detection signal SDT is 3 V. When the driving signal SDR is at a high level, the voltage value of the low level of the detection signal SDT is 0 V. Based on the waveform of the detection signal SDT, the processor 122 can determine that the connection of the second output port POUT_2 is correct.

[0076] Please also refer to Figure 1 , Figure 7 as well as Figure 8 , Figure 7 FIG. 4 is a schematic diagram of an incorrect connection according to an embodiment of the present invention. Figure 8 is based on Figure 7 In the present embodiment, when the second output port POUT_2 is connected to the second connection state of the first output port POUT_1, it means that the connection of the second output port POUT_2 is wrong.

[0077] It should be noted that when the second output port POUT_2 is connected to the second connection state of the first output port POUT_1, the pull-up resistor R_3 and the pull-down resistor R_4 are respectively connected to the output resistor R_1. The resistance value of the output resistor R_1, the resistance value of the pull-up resistor R_3, and the resistance value of the pull-down resistor R_4 are the same as each other. Therefore, the voltage value of the low level of the detection signal SDT is equal to the intermediate voltage value of the drive signal SDR (i.e., 1.65V). The voltage value of the high level of the detection signal SDT is equal to the voltage value of the reference high voltage VH (i.e., 3.3V). The processor 122 will Figure 8 The waveform of the detection signal SDT is used to provide a connection status signal SST corresponding to that the second output port POUT_2 is correctly connected to the first input port PIN_1.

[0078] In other words, when the driving signal SDR is at a low level, the voltage value of the high level of the detection signal SDT is 3.3 V. When the driving signal SDR is at a high level, the voltage value of the low level of the detection signal SDT is 1.65 V. Based on the waveform of the detection signal SDT, the processor 122 can determine that the connection of the second output port POUT_2 is wrong.

[0079] In this embodiment, the connection prompt circuit 123 controls the second display 120 to display an error connection prompt image according to the connection status signal SST.

[0080] based on Figure 4 , Figure 6 as well as Figure 8 The connection states corresponding to the detection signal SDT and the driving signal SDR are shown in Table 1.

[0081] Table 1:

[0082]

[0083] Please also refer to Figure 1 as well as Fig. 9 , Fig. 91 is a schematic diagram of a detection circuit, a first output port, and a second output port according to an embodiment of the present invention. In this embodiment, the first display 110 further includes a detection circuit 111. The detection circuit 111 includes a pull-up circuit 1111, a pull-up resistor R_5, a pull-down resistor R_6, and a pull-down circuit 1112. The first end of the pull-up circuit 1111 is coupled to the reference high voltage VH1 of the first display 110. The control end of the pull-up circuit 1111 receives the driving signal SDR' inside the first display 110. The pull-up resistor R_5 is coupled between the first output port POUT_1 and the second end of the pull-up circuit 1111. The first end of the pull-down resistor R_6 is coupled to the first output port POUT_1. The first end of the pull-down circuit 1112 is coupled to the second end of the pull-down resistor R_6. The second end of the pull-down circuit 1112 is coupled to the reference low voltage VL1 of the first display 110. The control end of the pull-down circuit 1112 receives the driving signal SDR'.

[0084] In this embodiment, the detection circuit 121 includes a pull-up circuit 1211, a pull-up resistor R_3, a pull-down resistor R_4, and a pull-down circuit 1212. The implementation of the pull-up circuit 1211, the pull-up resistor R_3, the pull-down resistor R_4, and the pull-down circuit 1212 has been described in detail in the prior art. Figure 3 This is clearly described in the embodiments, so it will not be repeated here.

[0085] In the present embodiment, the pull-up circuit 1111 can be implemented by a P-type transistor. For example, the pull-up circuit 1111 can be implemented by a P-type MOS, but the present invention is not limited thereto. The pull-down circuit 1112 can be implemented by an N-type transistor. For example, the pull-down circuit 1112 can be implemented by an N-type MOS, but the present invention is not limited thereto. In other words, in the present embodiment, the first display 110 and the second display 120 have the same design. The resistance value of the pull-up resistor R_5 is the same as the resistance value of the pull-up resistor R_3. The resistance value of the pull-down resistor R_6 is the same as the resistance value of the pull-down resistor R_4.

[0086] Fig. 9 The second connection state in which the second output port POUT_2 is connected to the first output port POUT_1 is shown. Such a connection state is wrong. However, it should be noted that since the drive signals SDR and SDR' are generated by different devices, the timing of the drive signals SDR and SDR' cannot be synchronized. This makes the waveform of the detection signal SDT more complicated. Fig. 9 The waveform of the detection signal SDT is shown in Table 2.

[0087] Table 2:

[0088]

[0089]

[0090] In case D, when the driving signals SDR and SDR' are both high level at the same time, the voltage value of the detection signal SDT is 0V. In case B, when the driving signals SDR and SDR' are both low level at the same time, the voltage value of the detection signal SDT is 3.3V. This causes the processor 122 to misjudge the connection state of the second output port POUT_2 as the second output port POUT_2 being unconnected based on cases B and D. The occurrence of case D must be excluded.

[0091] In this embodiment, in order to reduce the probability of misjudgment, the duty cycle of the high level (i.e., 3.3V) of the driving signals SDR and SDR' is designed to be less than 10%. Therefore, the probability of occurrence of situation D is greatly reduced. The probability of the connection state of the second output port POUT_2 being misjudged as the second output port POUT_2 being unconnected is greatly reduced.

[0092] In one embodiment, the duty cycle of the high level (i.e., 3.3V) of the driving signals SDR and SDR' is designed to be less than 5%. In one embodiment, the duty cycle of the high level (i.e., 3.3V) of the driving signals SDR and SDR' is designed to be less than 2%. (However, the present invention is not limited thereto)

[0093] Please also refer to Figure 1 as well as Fig.10 , Fig.10 is a state diagram according to an embodiment of the present invention. Fig.10 1 and 2 show the initial connection state ST0, the first connection state ST1 and the second connection state ST2. The initial connection state ST0, the first connection state ST1 and the second connection state ST2 can be converted by different conditions. In this embodiment, the processor 122 uses the connection state of the second output port POUT_2 being unconnected as the initial connection state ST0. The processor 122 determines the connection state of the second output port POUT_2 in the high level mode and the low level mode of the initial connection state ST0. In this embodiment, the high level mode is a judgment mode in which the drive signal SDR is at a high level. The low level mode is a judgment mode in which the drive signal SDR is at a low level.

[0094] In the initial connection state ST0, when the waveform of the detection signal SDT satisfies the first condition, the processor 122 determines that the second output port POUT_2 remains idle (i.e., remains in the initial connection state ST0). The first condition is that the voltage value of the detection signal SDT in the low level mode is equal to the voltage value of the reference high voltage VH (i.e., 3.3V), and the voltage value of the detection signal SDT in the high level mode is not equal to the intermediate voltage value (i.e., 1.65V). In other words, when the voltage value of the detection signal SDT in the low level mode is 3.3V and the voltage value in the high level mode is not equal to 1.65V, the processor 122 determines that the second output port POUT_2 remains idle.

[0095] In the initial connection state ST0, when the waveform of the detection signal SDT satisfies the second condition, the processor 122 determines that the connection state of the second output port POUT_2 is changed from the initial connection state ST0 to the first connection state ST1 (i.e., the correct connection state). The second condition is that the voltage value of the detection signal SDT in the low level mode is not equal to the voltage value of the reference high voltage VH, and the voltage value of the detection signal SDT in the high level mode is not equal to the intermediate voltage value. In other words, when the voltage value of the detection signal SDT in the low level mode is not equal to 3.3V and the voltage value in the high level mode is not equal to 1.65V, the processor 122 determines that the second output port POUT_2 is connected to the first input port PIN_1. Therefore, the connection state of the second output port POUT_2 is changed from the initial connection state ST0 to the first connection state ST1.

[0096] In the initial connection state ST0, when the waveform of the detection signal SDT satisfies the third condition, the processor 122 determines that the connection state of the second output port POUT_2 is changed from the initial connection state ST0 to the second connection state ST2 (i.e., an incorrect connection state). The third condition is that the voltage value of the detection signal SDT in the high level mode is equal to the intermediate voltage value. In other words, when the voltage value of the detection signal SDT in the high level mode is equal to 1.65V, the processor 122 determines that the second output port POUT_2 is connected to the first output port POUT_1. Therefore, the connection state of the second output port POUT_2 is changed from the initial connection state ST0 to the second connection state ST2.

[0097] In the first connection state ST1, the processor 122 reduces the duty cycle of the high level (i.e., 3.3V) of the driving signal SDR to 0%. In other words, the level of the driving signal SDR in the first connection state ST1 is maintained at a low level. In this way, in the first connection state ST1, the detection signal SDT is maintained at 3V, for example. In addition, interference in signal transmission can be avoided.

[0098] In the first connection state ST1, when the waveform of the detection signal SDT satisfies the fourth condition, the processor 122 determines that the connection state of the second output port POUT_2 changes from the first connection state ST1 to the starting connection state ST0. The fourth condition is that the voltage value of the detection signal SDT in the low level mode is equal to the voltage value of the reference high voltage VH (i.e., 3.3V). In other words, when the voltage value of the detection signal SDT in the low level mode changes from 3V to 3.3V, the processor 122 determines that the second output port POUT_2 is idle (e.g., the correct connection between the second output port POUT_2 and the first input port PIN_1 is unplugged). Therefore, the connection state of the second output port POUT_2 returns from the first connection state ST1 to the starting connection state ST0.

[0099] In the second connection state ST2, when the waveform of the detection signal SDT satisfies the fifth condition for a predetermined number of consecutive times, the processor 122 determines that the connection state of the second output port POUT_2 is changed from the second connection state ST2 to the initial connection state ST0. The fifth condition is that the voltage value of the detection signal SDT is equal to the voltage value of the reference high voltage VH (i.e., 3.3V) in the low level mode, and the voltage value of the detection signal SDT is equal to the voltage value of the reference low voltage VL (i.e., 0V) in the high level mode.

[0100] For example, the predetermined number of consecutive times can be set to 5. When the voltage value of the detection signal SDT in the low level mode is 3.3V and the voltage value in the high level mode is equal to 0V, and when the fifth condition occurs 5 times in a row, the processor 122 determines that the second output port POUT_2 is unconnected (e.g., the wrong connection between the second output port POUT_2 and the first output port POUT_1 is removed).

[0101] Please also refer to Figure 1 , Fig.10 as well as Fig.11 , Fig.11is a flow chart of an operation method according to an embodiment of the present invention. In this embodiment, the operation method S200 includes steps S210 to S290. In step S210, the processor 122 receives the detection signal SDT in the initial connection state ST0 and determines whether the voltage value of the detection signal SDT in the high level mode is equal to the intermediate voltage value (i.e., 1.65V). When the voltage value of the detection signal SDT in the high level mode is not equal to the intermediate voltage value, the processor 122 determines the voltage value of the detection signal SDT in the low level mode in step S220. In the initial connection state ST0, the processor 122 determines whether the voltage value of the detection signal SDT in the low level mode is equal to the voltage value of the reference high voltage VH (i.e., 3.3V). When the voltage value of the detection signal SDT in the high level mode is equal to the voltage value of the reference high voltage VH, the processor 122 determines that the second output port POUT_2 remains idle (i.e., maintained in the initial connection state ST0). Next, the processor 122 returns to the operation of step S210.

[0102] In this embodiment, steps S210 and S220 are determination operations in the initial connection state ST0.

[0103] Please go back to step S220. When the voltage value of the detection signal SDT is not equal to the voltage value of the reference high voltage VH in the high level mode, the processor 122 determines in step S240 that the second output port POUT_2 is correctly connected to the first input port PIN_1 (i.e., the first connection state ST1). In addition, in step S240, the processor 122 reduces the duty cycle of the high level (i.e., 3.3V) of the drive signal SDR to 0%. Next, the processor 122 determines in step S250 whether the voltage value of the detection signal SDT is equal to the voltage value of the reference high voltage VH (i.e., 3.3V) in the low level mode. When the voltage value of the detection signal SDT is not equal to the voltage value of the reference high voltage VH in the low level mode, the processor 122 determines that the second output port POUT_2 maintains the correct connection (i.e., maintained in the first connection state ST1). Next, the processor 122 returns to the operation of step S240.

[0104] On the other hand, when the voltage value of the detection signal SDT is equal to the voltage value of the reference high voltage VH in the low level mode in step S250, the processor 122 determines that the second output port POUT_2 is idle. Next, the processor 122 returns to the operation of step S210. In other words, the connection state of the second output port POUT_2 returns from the first connection state ST1 to the initial connection state ST0.

[0105] In this embodiment, step S250 is a determination operation in the first connection state ST1.

[0106] Please go back to step S210. In the initial connection state ST0, when the voltage value of the detection signal SDT in the high level mode is equal to the intermediate voltage value, the processor 122 determines in step S260 that the second output port POUT_2 is incorrectly connected to the first output port POUT_1. Therefore, the connection state of the second output port POUT_2 enters the second connection state ST2 from the initial connection state ST0. Next, the processor 122 determines in step S270 whether the voltage value of the detection signal SDT in the low level mode is equal to the voltage value of the reference high voltage VH. When the voltage value of the detection signal SDT is not equal to the voltage value of the reference high voltage VH, the processor 122 returns to the operation of step S260. On the other hand, when the voltage value of the detection signal SDT is equal to the voltage value of the reference high voltage VH, the processor 122 determines the voltage value of the detection signal SDT in the high level mode in step S280.

[0107] In the second connection state ST2, in step S280, the processor 122 determines whether the voltage value of the detection signal SDT in the high level mode is equal to the voltage value of the reference low voltage VL. When the voltage value of the detection signal SDT in the high level mode is not equal to the voltage value of the reference low voltage VL, the processor 122 returns to the operation of step S260. On the other hand, when the voltage value of the detection signal SDT in the high level mode is equal to the voltage value of the reference low voltage VL, the processor 122 determines in step S290 whether the number of judgments reaches a predetermined number of consecutive times. When the number of judgments has not reached the predetermined number of consecutive times, the processor 122 increments the number of judgments and returns to the operation of step S260. On the other hand, when the number of judgments reaches the predetermined number of consecutive times, the processor 122 resets the number of judgments (e.g., resets the number of judgments to zero) and returns to the operation of step S210. In other words, the connection state of the second output port POUT_2 returns from the second connection state ST2 to the initial connection state ST0.

[0108] In this embodiment, steps S270 to S290 are determination operations in the second connection state ST2.

[0109] Please also refer to Figure 1 as well as Fig.12 , Fig.12is a schematic diagram of a connection prompt screen according to an embodiment of the present invention. In this embodiment, when the connection status signal SST corresponds to the second connection state in which the second output port POUT_2 is connected to the first output port POUT_1, this indicates that the connection of the second output port POUT_2 is incorrect. Therefore, the connection prompt circuit 123 controls the second display 120 according to the connection status signal SST, so that the second display 120 provides a connection prompt screen IMGP to guide the user to make a correct connection. In this embodiment, the connection prompt screen IMGP includes 5 prompt parts P1 to P5. The prompt part P1 displays the description of the incorrect connection of the second output port POUT_2. For example, the prompt part P1 displays text about the incorrect connection of the second output port POUT_2. The prompt part P2 displays the incorrect connection of the current second output port POUT_2. For example, the prompt part P2 displays the incorrect connection of the second output port POUT_2 in a graphical manner. For another example, the prompt part P2 displays the incorrect connection of the second output port POUT_2 in a textual manner or in a manner in which an LED light circuit turns on and off.

[0110] The prompt part P3 displays the correct connection method of the second output port POUT_2. For example, the prompt part P3 displays the correct connection method of the second output port POUT_2 in a graphical manner. For another example, the prompt part P3 displays the correct connection method of the second output port POUT_2 in a text manner or in a LED light circuit on and off manner.

[0111] The prompt part P4 displays a diagram of the switching direction. The switching direction in the prompt part P4 is from the prompt part P2 to the prompt part P3. For another example, the prompt part P4 displays the correct connection method for the switching direction in the form of an LED light circuit on and off. Therefore, the user can intuitively know that the incorrect connection of the prompt part P2 must be changed to the correct connection of the prompt part P3.

[0112] The prompt portion P5 displays the position information of the first input port PIN_1. For example, the prompt portion P5 displays information about the front of the first display 110. With respect to the front of the first display 110, the first input port PIN_1 is located on the right side of the first display 110. The first output port POUT_1 is located on the left side of the first display 110. Therefore, the position of the prompt portion P2 located on the left side corresponds to the position of the first output port POUT_1. The position of the prompt portion P3 located on the right side corresponds to the position of the first input port PIN_1. Therefore, the user can clearly know the position of the first input port PIN_1 according to the connection prompt screen IMGP.

[0113] In summary, the second display includes a second output port, a processor, and a connection prompt circuit. The processor determines the connection status of the second output port according to the level of the detection signal. The connection prompt circuit controls the second display to output a connection prompt screen according to the connection status. The second display can provide a connection prompt screen according to the connection status between the first display and the second display. In this way, in the case of a connection error, the second display can provide a connection prompt screen to guide the user to make a correct connection.

[0114] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art should be able to make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the attached claims.

Claims

1. A display system, comprising: A first display, the first display comprising: a first input port; and a first output port; and a second display, the second display comprising: a second output port; a detection circuit coupled to the second output port and configured to drive the second output port in response to a driving signal; a processor coupled to the second output port and configured to receive a detection signal at the second output port and determine a connection state of the second output port according to a level of the detection signal; and a connection prompt circuit, the connection prompt circuit is coupled to the processor and is configured to control the second display to output a connection prompt screen according to the connection status, The level of the detection signal changes according to one of the second output port being idling, the second output port being connected to the first input port, and the second output port being connected to the first output port.

2. The display system as claimed in claim 1, wherein the processor provides the driving signal. 3 . The display system as claimed in claim 1 , wherein a duty cycle of the high level of the driving signal is lower than 10%. 4 . The display system of claim 3 , wherein in response to the second output port being determined to be connected to the first input port, the processor reduces the duty cycle to 0%.

5. The display system as claimed in claim 1, wherein the detection circuit comprises: a pull-up circuit, wherein a first terminal of the pull-up circuit is coupled to a reference high voltage of the second display, and a control terminal of the pull-up circuit receives the driving signal; a pull-up resistor coupled between the second output port and the second end of the pull-up circuit; a pull-down resistor, a first end of the pull-down resistor being coupled to the second output port; as well as A pull-down circuit is provided, wherein a first end of the pull-down circuit is coupled to a second end of the pull-down resistor, a second end of the pull-down circuit is coupled to a reference low voltage of the second display, and a control end of the pull-down circuit receives the driving signal.

6. The display system of claim 5, wherein: The first input port comprises: an input terminal; and an input resistor coupled between the input terminal and a reference low voltage of the first display, The first output port comprises: an output terminal; and An output resistor is coupled between the output terminal and a reference high voltage of the first display.

7. The display system of claim 6, wherein: In response to the detection signal being inverted to the drive signal, the processor provides a connection status signal corresponding to the second output port being unconnected, and The connection prompt circuit controls the second display to display an idle connection prompt picture according to a connection status signal corresponding to the idle connection of the second output port.

8. The display system of claim 6, wherein: The resistance value of the pull-up resistor, the resistance value of the pull-down resistor, and the resistance value of the output resistor are the same as each other, and The resistance value of the input resistor is greater than the resistance values ​​of the pull-up resistor, the pull-down resistor, and the output resistor.

9. The display system of claim 8, wherein: In response to the voltage value of the low level of the detection signal being equal to the voltage value of the reference low voltage and the voltage value of the high level of the detection signal being between an intermediate voltage value and the voltage value of the reference high voltage, the processor provides a connection status signal corresponding to the second output port being connected to the first input port, and The intermediate voltage value is an intermediate value between the voltage value of the reference low voltage and the voltage value of the reference high voltage.

10. The display system of claim 8, wherein: In response to the voltage value of the low level of the detection signal being equal to an intermediate voltage value of the reference high and low voltages and the voltage value of the high level of the detection signal being equal to the voltage value of the reference high voltage, the processor provides a connection status signal corresponding to the second output port being connected to the first output port, The connection prompt circuit controls the second display to display an error connection prompt screen according to a connection status signal corresponding to the second output port being connected to the first output port, and The intermediate voltage value is an intermediate value between the voltage value of the reference low voltage and the voltage value of the reference high voltage.

11. The display system of claim 8, wherein: The processor uses the idle connection state of the second output port as the initial connection state, and determines the connection state of the second output port in a high level mode and a low level mode of the initial connection state. The high level mode is a judgment mode in which the drive signal is at a high level, and The low level mode is a determination mode in which the driving signal is at a low level.

12. The display system as claimed in claim 11, wherein in the initial connection state: In response to the voltage value of the detection signal being equal to the voltage value of the reference high voltage in the low level mode, and in response to the voltage value of the detection signal being not equal to an intermediate voltage value in the high level mode, the processor determines that the second output port is unconnected. The intermediate voltage value is an intermediate value between the voltage value of the reference low voltage and the voltage value of the reference high voltage.

13. The display system as claimed in claim 12, wherein in the initial connection state: In response to the voltage value of the detection signal being equal to the intermediate voltage value in the high level mode, the processor determines that the second output port is connected to the first output port.

14. The display system as claimed in claim 12, wherein in the initial connection state: In response to the voltage value of the detection signal being not equal to the voltage value of the reference high voltage in the low level mode and the voltage value of the detection signal being not equal to the intermediate voltage value in the high level mode, the processor determines that the second output port is connected to the first input port.

15. An operating method for a display system, wherein the display system comprises a first display and a second display, wherein the first display comprises a first input port and a first output port, wherein the second display comprises a second output port, wherein the operating method comprises: driving the second output port in response to a driving signal; receiving a detection signal at the second output port, and determining a connection state of the second output port according to a level of the detection signal, wherein the level of the detection signal changes according to one of the second output port being unconnected, the second output port being connected to the first input port, and the second output port being connected to the first output port; as well as The second display is controlled to output a connection prompting screen according to the connection status.

16. The operating method of claim 15, wherein determining the connection status of the second output port according to the level of the detection signal comprises: The connection state of the second output port being unconnected is used as the initial connection state; as well as The connection state of the second output port is determined in a high level mode and a low level mode of the initial connection state. The high level mode is a judgment mode in which the driving signal is at a high level, and The low level mode is a judgment mode in which the driving signal is at a low level.

17. The operating method of claim 16, wherein determining the connection status of the second output port according to the level of the detection signal further comprises: In the initial connection state, in response to the voltage value of the detection signal being equal to the voltage value of the reference high voltage in the low level mode, and the voltage value of the detection signal being not equal to an intermediate voltage value in the high level mode, it is determined that the second output port is unconnected, The intermediate voltage value is an intermediate value between the voltage value of the reference low voltage and the voltage value of the reference high voltage.

18. The operating method of claim 17, wherein determining the connection status of the second output port according to the level of the detection signal further comprises: In the initial connection state, in response to the voltage value of the detection signal being equal to the intermediate voltage value in the high level mode, it is determined that the second output port is connected to the first output port.

19. The operating method of claim 17, wherein determining the connection status of the second output port according to the level of the detection signal further comprises: In the initial connection state, in response to the voltage value of the detection signal being not equal to the voltage value of the reference high voltage in the low level mode, and the voltage value of the detection signal being not equal to the intermediate voltage value in the high level mode, it is determined that the second output port is connected to the first input port.

20. The operating method according to claim 15, further comprising: In response to the second output port being determined to be connected to the first input port, the duty cycle of the high level of the driving signal is reduced to 0%.

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