Display device

Abstract

The invention relates to a display device. The display device includes: pixel circuit groups disposed in a matrix form along a first direction and a second direction intersecting the first direction in a display area, each pixel circuit group including a pixel circuit; a first driver disposed in a non-display area on one side of the display area, and providing a data voltage to the pixel circuit; a second driver disposed in a non-display area on the other side opposite the one side of the display area, and providing a driving signal to the pixel circuit; a first connection line connected to the second driver and extending in a first direction; a second connection line connected to the first connection line in a separation space between adjacent pixel circuit groups and extending in a second direction; and a signal line connected to the second connection line and transmitting the driving signal to the pixel circuit.

Description

Technical Field

[0001] The present disclosure generally relates to a display device and more particularly to a display device that provides visual information. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has been highlighted. For example, the use of display devices such as liquid crystal display (LCD) devices, organic light emitting display (OLED) devices, plasma display panel (PDP) devices, quantum dot display devices, etc. is increasing.

[0003] A display device may include a display area that displays an image and a non-display area that does not display the image. In order to expand the display area in a display device, research is being conducted to reduce the area occupied by the non-display area. Summary of the invention

[0004] Embodiments provide a display device having a relatively small non-display area and suppressing display defects.

[0005] A display device according to an embodiment of the present disclosure includes: a substrate including a display area and a non-display area surrounding the display area; pixel circuit groups, which are arranged in a matrix form along a first direction and a second direction intersecting the first direction in the display area on the substrate, each of the pixel circuit groups including a pixel circuit; a first driver, which is arranged in the non-display area on one side of the display area on the substrate, and provides a data voltage to the pixel circuit; a second driver, which is arranged in the non-display area on the other side of the display area opposite to the one side on the substrate, and provides a driving signal to the pixel circuit; a first connecting line, which is connected to the second driver and extends in the first direction; a second connecting line, which is connected to the first connecting line in a separation space between adjacent pixel circuit groups and extends in the second direction; and a signal line, which is connected to the second connecting line and transmits the driving signal provided from the second driver to the pixel circuit.

[0006] In an embodiment, the second connection line and the signal line may be connected at the first contact point in the non-display area. The first connection line and the second connection line may be connected at the second contact point in the display area.

[0007] In an embodiment, the second driver may be positioned to be spaced apart from the display area in the first direction, and the first contact point may be positioned to be spaced apart from the display area in the second direction.

[0008] In an embodiment, the second contact point may be located in a first separation space between adjacent pixel circuit groups arranged along the first direction.

[0009] In an embodiment, the display device may further include a light emitting element located in a separation space between adjacent pixel circuit groups. At least a portion of the second connection line may overlap the light emitting element in a plan view.

[0010] In an embodiment, the second contact point may be located in a second separation space between adjacent pixel circuit groups arranged along the second direction.

[0011] In an embodiment, the second driver may include a gate driver that provides a gate signal to the pixel circuit. The first connection line may include a first gate connection line connected to the gate driver. The second connection line may include a second gate connection line connected to the first gate connection line. The signal line may include a gate signal line that is connected to the second gate connection line and transmits a gate signal provided from the gate driver.

[0012] In an embodiment, the second driver may include an emission driver that provides an emission control signal to the pixel circuit. The first connection line may include a first emission connection line connected to the emission driver. The second connection line may include a second emission connection line connected to the first emission connection line. The signal line may include an emission signal line that is connected to the second emission connection line and transmits the emission control signal provided from the emission driver.

[0013] In an embodiment, the display device may further include a constant voltage line that provides a constant voltage to the pixel circuit. The constant voltage line may include a first constant voltage line connected to the second driver and extending in the first direction and a second constant voltage line connected to the first constant voltage line and extending in the second direction. The first constant voltage line and the second constant voltage line may be connected at a third contact point in the display area.

[0014] In an implementation, the third contact point may overlap each of the pixel circuits in a plan view.

[0015] In an implementation, the third contact point may be located in a separation space between adjacent pixel circuit groups.

[0016] In an embodiment, the non-display area may include: a first driver area located on one side of the display area and provided with a first driver; a second driver area located on the other side of the display area and provided with a second driver; and a bending area located between the display area and the first driver area and between the display area and the second driver area in a plan view, respectively. The substrate may be bendable around a reference axis parallel to the second direction in the bending area.

[0017] In an implementation, the second connection line may include at least one selected from the group consisting of aluminum, copper, silver, molybdenum, and titanium.

[0018] A display device according to another embodiment of the present disclosure includes: a substrate including a display area and a non-display area surrounding the display area; pixel circuit groups, which are arranged in a matrix form along a first direction and a second direction intersecting the first direction in the display area on the substrate, each of the pixel circuit groups including a pixel circuit; a first driver, which is arranged in the non-display area on one side of the display area on the substrate, and provides a data voltage to the pixel circuit; a second driver, which is arranged in the non-display area on one side of the display area on the substrate, and provides a driving signal to the pixel circuit; a first connecting line, which is connected to the second driver and extends in the first direction; a second connecting line, which is connected to the first connecting line in a separation space between adjacent pixel circuit groups and extends in the second direction; and a signal line, which is connected to the second connecting line and transmits the driving signal provided from the second driver to the pixel circuit.

[0019] In an embodiment, the second connection line and the signal line may be connected at the first contact point in the non-display area. The second driver may be positioned to be spaced apart from the display area in the first direction, and the first contact point may be positioned to be spaced apart from the display area in the second direction.

[0020] In an embodiment, the first connection line and the second connection line may be connected at a second contact point in the display area. The second contact point may be located in a first separation space between adjacent pixel circuit groups arranged along the first direction.

[0021] In an embodiment, the first connection line and the second connection line may be connected at a second contact point in the display area. The second contact point may be located in a second separation space between adjacent pixel circuit groups arranged along the second direction.

[0022] In an embodiment, the second driver may include a gate driver that provides a gate signal to the pixel circuit. The first connection line may include a first gate connection line connected to the gate driver. The second connection line may include a second gate connection line connected to the first gate connection line. The signal line may include a gate signal line that is connected to the second gate connection line and transmits a gate signal provided from the gate driver.

[0023] In an embodiment, the second driver may include an emission driver that provides an emission control signal to the pixel circuit. The first connection line may include a first emission connection line connected to the emission driver. The second connection line may include a second emission connection line connected to the first emission connection line. The signal line may include an emission signal line that is connected to the second emission connection line and transmits the emission control signal provided from the emission driver.

[0024] In an embodiment, the non-display area may include: a driver area located on one side of the display area and provided with each of the first driver and the second driver; and a bending area located between the display area and the driver area in a plan view. The substrate may be able to bend around a reference axis parallel to the second direction in the bending area.

[0025] A display device according to an embodiment of the present disclosure may include: a substrate including a display area and a non-display area surrounding the display area; a pixel circuit group arranged in the display area on the substrate, each of the pixel circuit groups including a pixel circuit; a second driver arranged in the non-display area on the substrate, positioned to be spaced apart from the display area in a first direction, and providing a driving signal to the pixel circuit; a first connecting line connected to the second driver and extending in the first direction; a second connecting line connected to the first connecting line and extending in a second direction intersecting the first direction; and a signal line connected to the second connecting line and transmitting the driving signal to the pixel circuit.

[0026] When the substrate is bent, the second driver may be located on the lower surface of the display device. Therefore, the dead zone of the display device may be reduced compared to a case where the second driver is located in the second direction from the display area.

[0027] The second connection line can be connected to the first connection line at the second contact point in the separation space between the adjacent pixel circuit groups. In addition, the signal line can be connected to the second connection line at the first contact point in the non-display area. That is, each of the first contact point and the second contact point can be spaced apart from the pixel circuit in a plan view. Therefore, the display defect in which spots are visible in the display device can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a plan view showing a display device according to a first embodiment of the present disclosure.

[0030] Figure 2 It is shown Figure 1 A side view of a display device showing a curved shape.

[0031] Figure 3 yes Figure 1 An enlarged plan view of area "A".

[0032] Figure 4 It is shown Figure 1 A cross-sectional view of a display device.

[0033] Figure 5 It is shown Figure 1A block diagram of a display device.

[0034] Figure 6 It is shown that the Figure 1 A circuit diagram of a pixel in a display device.

[0035] Figure 7 , Figure 8 , Fig. 9 and Fig.10 It is shown Figure 1 A plan view of a display device.

[0036] Fig.11 is a plan view showing a display device according to a second embodiment of the present disclosure.

[0037] Fig.12 is a plan view showing a display device according to a third embodiment of the present disclosure.

[0038] Fig.13 is a plan view showing a display device according to a fourth embodiment of the present disclosure.

[0039] Fig.14 is a plan view showing a display device according to a fifth embodiment of the present disclosure.

[0040] Fig.15 is a plan view showing a display device according to a sixth embodiment of the present disclosure.

[0041] Fig.16 It is shown Fig.15 A side view of a display device showing a curved shape.

[0042] Fig.17 and Fig.18 It is shown Fig.15 A plan view of a display device.

[0043] Fig.19 is a plan view showing a display device according to a seventh embodiment of the present disclosure.

[0044] Fig. 20 is a plan view showing a display device according to an eighth embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0046] Figure 1 is a plan view showing a display device according to a first embodiment of the present disclosure. Figure 2 It is shown Figure 1 A side view of a display device showing a curved shape.

[0047] In the present specification, a plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. The first direction DR1 may represent an up-down direction (or a vertical direction) in a plan view. That is, one side of the first direction DR1 may represent an upward direction in a plan view, and the other side of the first direction DR1 may represent a downward direction in a plan view. The second direction DR2 may represent a left-right direction (or a horizontal direction) in a plan view. That is, one side of the second direction DR2 may represent a left direction in a plan view, and the other side of the second direction DR2 may represent a right direction in a plan view. A direction perpendicular to a plane formed by the first direction DR1 and the second direction DR2 (i.e., a thickness direction of the display device DD1) may be a third direction DR3. In other words, the third direction DR3 may be perpendicular to each of the first direction DR1 and the second direction DR2.

[0048] refer to Figure 1 and Figure 2 , the display device DD1 according to the first embodiment of the present disclosure may include a substrate SUB, a first driver D-IC, a pad portion PD, a second driver GDV, and a data line DL.

[0049] The substrate SUB may include a display area DA and a non-display area NDA. The display area DA may be defined as an area that displays an image by generating light or adjusting the transmittance of light provided from an external light source. Figure 3 The pixels PX) may be disposed in the display area DA. The pixels may generate light according to the driving signal. The pixels may be arranged in a matrix along the first direction DR1 and the second direction DR2. A detailed description thereof will be referred to below. Figure 3 supply.

[0050] The data lines DL connected to the pixels may be disposed in the display area DA on the substrate SUB. The data lines DL may extend in the first direction DR1 and be disposed along the second direction DR2. Each of the data lines DL may be electrically connected to the first driver D-IC. Each of the data lines DL may receive a data voltage (e.g., Figure 6 DATA).

[0051] A gate signal line connected to a pixel (eg, Figure 7 The gate signal line GL) and the emission signal line (eg, Figure 8 The emission signal line EML) may be disposed in the display area DA on the substrate SUB. A detailed description thereof will be referred to below. Figure 7 and Figure 8 supply.

[0052] The non-display area NDA may be defined as an area where no image is displayed. The non-display area NDA may surround the display area DA. The non-display area NDA may include a peripheral area PA, a bending area BA, a first driver area DRA1, and a second driver area DRA2.

[0053] The peripheral area PA may be located around the display area DA. For example, the peripheral area PA may completely surround the display area DA.

[0054] The bending area BA may include a first bending area BA1 and a second bending area BA2. The first bending area BA1 may extend from one side of the peripheral area PA. For example, the first bending area BA1 may be as shown in FIG. Figure 1 The second bending area BA2 may extend from the other side of the peripheral area PA that is arranged opposite to the one side. For example, the second bending area BA2 may be as shown in FIG. Figure 1 As shown in the plan view, it is located above the peripheral area PA. In the plan view, the first driver area DRA1 may extend from the first bending area BA1 and be located below the display area DA or the peripheral area PA. In the plan view, the second driver area DRA2 may extend from the second bending area BA2 and be located above the display area DA or the peripheral area PA.

[0055] The substrate SUB may be bent in the bending area BA about a reference axis parallel to the second direction DR2. Figure 2 As shown, each of the first driver area DRA1 and the second driver area DRA2 may be located on a lower surface of the display device DD1.

[0056] like Figure 1 As shown, when the display device DD1 is unfolded (i.e., when the substrate SUB is unfolded), the first bending area BA1 may be located between the display area DA and the first driver area DRA1, and the second bending area BA2 may be located between the display area DA and the second driver area DRA2. Specifically, when the display device DD1 is unfolded, the first bending area BA1 may be located between the peripheral area PA and the first driver area DRA1, and the second bending area BA2 may be located between the peripheral area PA and the second driver area DRA2.

[0057] The first driver D-IC may be disposed in the non-display area NDA on the substrate SUB, and may be located on one side of the display area DA. Specifically, the first driver D-IC may be located in the first driver area DRA1 on the substrate SUB. The first driver D-IC may convert a digital data signal in a driving signal into an analog data signal, and may provide the converted data signal to the pixel. In other words, the first driver D-IC may provide a data voltage to the pixel. For example, the first driver D-IC may be used as a data driver (e.g., Figure 5 data driver 400).

[0058] The pad portion PD may be disposed in the first driver area DRA1 on the substrate SUB. The pad portion PD may include a plurality of pads. The pad portion PD may be electrically connected to the first driver D-IC and / or a printed circuit board.

[0059] The second driver GDV may be disposed in the non-display area NDA on the substrate SUB, and may be located on the other side of the display area DA disposed opposite to the side of the display area DA. Specifically, the second driver GDV may be located in the second driver area DRA2 on the substrate SUB. The second driver GDV may provide a driving signal to the pixel. The driving signal may include a gate signal and a light emitting control signal. For example, the second driver GDV may be used as a gate driver (e.g., Figure 5 ) and an emission driver (eg, Figure 5 of the transmitting driver 500).

[0060] The second driver GDV may be positioned in the first direction DR1 from the display area DA. In other words, the second driver GDV may be disposed adjacent to the display area DA in the first direction DR1. As described above, when the substrate SUB is bent in the second bending area BA2, the second driver GDV may be located on the lower surface of the display device DD1. Therefore, compared with a case where the second driver GDV is positioned in the second direction DR2 from the display area DA, a dead space of the display device DD1 may be reduced.

[0061] Figure 3 yes Figure 1 An enlarged plan view of area "A".

[0062] refer to Figure 1 and Figure 3 The display device DD1 according to the first embodiment of the present disclosure may include a plurality of pixels PX disposed in a display area DA on a substrate SUB. The pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2. Each of the pixels PX may include a light emitting element LD and one of the pixel circuits PXC.

[0063] The light emitting elements LD may be arranged in a matrix along the first direction DR1 and the second direction DR2. In other words, the light emitting elements LD may be arranged along a plurality of rows and a plurality of columns. For example, the light emitting elements LD may be arranged along a first element row DROW1, a second element row DROW2, a third element row DROW3, ​​a fourth element row DROW4, a fifth element row DROW5, and a sixth element row DROW6. The first element row DROW1, the second element row DROW2, the third element row DROW3, ​​the fourth element row DROW4, the fifth element row DROW5, and the sixth element row DROW6 may be arranged along the first direction DR1.

[0064] Each of the light emitting elements LD may include a first light emitting area EA1, a second light emitting area EA2, and a third light emitting area EA3 that emit light. Figure 3 In FIG. 1 , each of the light emitting elements LD is shown to include three light emitting areas EA1 , EA2 , and EA3 , but the present disclosure is not limited thereto. For example, each of the light emitting elements LD may include four or more light emitting areas.

[0065] For example, each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a triangular plane shape, a rectangular plane shape, a circular plane shape, a track-shaped plane shape, an elliptical plane shape, etc. In an embodiment, each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a rectangular plane shape. However, the present disclosure is not limited thereto, and each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a different plane shape.

[0066] In an embodiment, the size (i.e., area) of the first light emitting region EA1 may be the same as that of the second light emitting region EA2, and the size of the third light emitting region EA3 may be larger than that of the first light emitting region EA1 and that of the second light emitting region EA2. However, the present disclosure is not limited thereto, and the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 may have the same size.

[0067] A first light emitting element (eg, Figure 4 The first light emitting element LD1 of the embodiment of the present invention may be located in the first light emitting area EA1. The second light emitting element LD2 emitting the second light (eg, Figure 4 The second light emitting element LD2) may be located in the second light emitting area EA2. The third light emitting element (eg, Figure 4The third light emitting element LD3) may be located in the third light emitting area EA3. For example, the first light may be red light, the second light may be blue light, and the third light may be green light. However, the present disclosure is not limited thereto.

[0068] The pixel circuits PXC may be arranged in a matrix along the first direction DR1 and the second direction DR2. In other words, the pixel circuits PXC may be arranged along a plurality of rows and a plurality of columns. For example, the pixel circuits PXC may be arranged along a first circuit row CROW1, a second circuit row CROW2, a third circuit row CROW3, ​​a fourth circuit row CROW4, a fifth circuit row CROW5, and a sixth circuit row CROW6. The first circuit row CROW1, the second circuit row CROW2, the third circuit row CROW3, ​​the fourth circuit row CROW4, the fifth circuit row CROW5, and the sixth circuit row CROW6 may be arranged along the first direction DR1.

[0069] Each of the pixel circuits PXC may include a first pixel circuit, a second pixel circuit, and a third pixel circuit. The first pixel circuit may be connected to the first light emitting element, the second pixel circuit may be connected to the second light emitting element, and the third pixel circuit may be connected to the third light emitting element. Therefore, the first pixel circuit may provide a first drive current to the first light emitting element, the second pixel circuit may provide a second drive current to the second light emitting element, and the third pixel circuit may provide a third drive current to the third light emitting element.

[0070] The light emitting elements LD located in the first element row DROW1 may be respectively connected to the pixel circuits PXC located in the first circuit row CROW1. The light emitting elements LD located in the second element row DROW2 may be respectively connected to the pixel circuits PXC located in the second circuit row CROW2. For example, the first element row DROW1 may be arranged adjacent to the first circuit row CROW1 in the first direction DR1, and the second element row DROW2 may be arranged adjacent to the second circuit row CROW2 in the first direction DR1. In addition, the first circuit row CROW1 and the second circuit row CROW2 may be arranged between the first element row DROW1 and the second element row DROW2. In other words, the first element row DROW1, the first circuit row CROW1, the second circuit row CROW2 and the second element row DROW2 may be arranged sequentially along the first direction DR1.

[0071] Similarly, the light emitting elements LD located in the third element row DROW3 may be connected to the pixel circuits PXC located in the third circuit row CROW3, ​​respectively. The light emitting elements LD located in the fourth element row DROW4 may be connected to the pixel circuits PXC located in the fourth circuit row CROW4, respectively. For example, the third element row DROW3 may be arranged adjacent to the third circuit row CROW3 in the first direction DR1, and the fourth element row DROW4 may be arranged adjacent to the fourth circuit row CROW4 in the first direction DR1. In addition, the third circuit row CROW3 and the fourth circuit row CROW4 may be arranged between the third element row DROW3 and the fourth element row DROW4. In other words, the third element row DROW3, ​​the third circuit row CROW3, ​​the fourth circuit row CROW4 and the fourth element row DROW4 may be arranged sequentially along the first direction DR1.

[0072] Similarly, the light emitting elements LD located in the fifth element row DROW5 can be connected to the pixel circuits PXC located in the fifth circuit row CROW5, respectively. The light emitting elements LD located in the sixth element row DROW6 can be connected to the pixel circuits PXC located in the sixth circuit row CROW6, respectively. For example, the fifth element row DROW5 can be arranged adjacent to the fifth circuit row CROW5 in the first direction DR1, and the sixth element row DROW6 can be arranged adjacent to the sixth circuit row CROW6 in the first direction DR1. In addition, the fifth circuit row CROW5 and the sixth circuit row CROW6 can be arranged between the fifth element row DROW5 and the sixth element row DROW6. In other words, the fifth element row DROW5, the fifth circuit row CROW5, the sixth circuit row CROW6 and the sixth element row DROW6 can be arranged sequentially along the first direction DR1.

[0073] A pixel circuit group GPXC (which is a collection of a plurality of pixel circuits PXC) may be disposed between element rows. Figure 3 As shown, one pixel circuit group GPXC may include six pixel circuits PXC arranged along two rows and three columns. However, the number of pixel circuits PXC included in one pixel circuit group GPXC is not limited thereto.

[0074] The pixel circuit groups GPXC may be arranged in a matrix along the first direction DR1 and the second direction DR2. In other words, the pixel circuit groups GPXC may be arranged along a plurality of rows and a plurality of columns. The pixel circuit groups GPXC may be spaced apart from each other by a predetermined distance. That is, a separation space SPS in which the pixel circuit PXC is not disposed may be defined between the pixel circuit groups GPXC.

[0075] The separation space SPS may include a first separation space SPS1 and a second separation space SPS2. The first separation space SPS1 may be a separation space between the pixel circuit groups GPXC arranged along the first direction DR1. In other words, the first separation space SPS1 may be spaced apart from each other in the up-down direction (e.g., the first direction DR1) between the pixel circuit groups GPXC in a plan view.

[0076] The second separation spaces SPS2 may be separation spaces between the pixel circuit groups GPXC arranged along the second direction DR2. In other words, the second separation spaces SPS2 may be spaced apart from each other in the left-right direction (eg, second direction DR2) between the pixel circuit groups GPXC in a plan view.

[0077] In an embodiment, the light emitting element LD may be located in the separation space SPS between the pixel circuit groups GPXC. For example, the light emitting element LD may be located in the first separation space SPS1.

[0078] Figure 4 It is shown Figure 1 A cross-sectional view of a display device.

[0079] refer to Figure 4 The display device DD1 according to the first embodiment of the present disclosure may include a substrate SUB, a lower pattern BML, a buffer layer BUF, an active layer ACT, a gate insulating layer GID, a first gate electrode GE1, a second gate electrode GE2, and a third gate electrode GE3, an interlayer insulating layer ILD, a first source electrode SE1, a second source electrode SE2, and a third source electrode SE3, a first drain electrode DE1, a second drain electrode DE2, and a third drain electrode DE3, a first via insulating layer VIA1, a first lower connection electrode LCE1, a second lower connection electrode LCE2, and a third lower connection electrode LCE3, a second via insulating layer VIA2, a first upper connection electrode UCE1, a second upper connection electrode UCE2, and a third upper connection electrode UCE3, a third via insulating layer VIA3, a first light emitting element LD1, a second light emitting element LD2, and a third light emitting element LD3, and a pixel defining layer PDL. The first light emitting element LD1 may include a first pixel electrode AE1, a first light emitting layer EL1, and a common electrode CTE. The second light emitting element LD2 may include a second pixel electrode AE2, a second light emitting layer EL2, and a common electrode CTE. The third light emitting element LD3 may include a third pixel electrode AE3, a third light emitting layer EL3, and a common electrode CTE.

[0080] The substrate SUB may include a transparent material or an opaque material. The substrate SUB may be formed of a transparent resin substrate. A polyimide substrate may be an example of a transparent resin substrate. In this case, the polyimide substrate may include a first organic layer, a first barrier layer, a second organic layer, and the like. Alternatively, the substrate SUB may include a quartz substrate (e.g., a synthetic quartz substrate, a fluorine-doped quartz substrate), a calcium fluoride substrate, a soda-lime glass substrate, a non-alkaline glass substrate, and the like. These may be used alone or in combination with each other.

[0081] The lower pattern BML may be disposed on the substrate SUB. The lower pattern BML may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. Examples of materials that may be used as the lower pattern BML may include silver (Ag), an alloy including silver, molybdenum (Mo), an alloy including molybdenum, aluminum (Al), an alloy including aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other.

[0082] The buffer layer BUF may be disposed on the substrate SUB. The buffer layer BUF may prevent metal atoms or impurities from diffusing from the substrate SUB to the upper structure (e.g., the light emitting element LD). In addition, when the surface of the substrate SUB is uneven, the buffer layer BUF may be used to improve the flatness of the surface of the substrate SUB. For example, the buffer layer BUF may include an inorganic insulating material. Examples of inorganic insulating materials that may be used as the buffer layer BUF may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0083] The active layer ACT may be disposed on the buffer layer BUF. The active layer ACT may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, and the like. For example, the oxide semiconductor may include at least one oxide of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor may include amorphous silicon, polycrystalline silicon, and the like. In an embodiment, the active layer ACT may include a silicon semiconductor. The active layer ACT may include a first active pattern ACT1, a second active pattern ACT2, and a third active pattern ACT3. The first active pattern ACT1 may include a first source region, a first drain region, and a first channel region between the first source region and the first drain region. The second active pattern ACT2 may include a second source region, a second drain region, and a second channel region between the second source region and the second drain region. The third active pattern ACT3 may include a third source region, a third drain region, and a third channel region between the third source region and the third drain region.

[0084] The gate insulating layer GID may be disposed on the buffer layer BUF and the active layer ACT. The gate insulating layer GID may cover the active layer ACT on the substrate SUB and may have a substantially flat upper surface without generating a step difference around the active layer ACT. Alternatively, the gate insulating layer GID may cover the active layer ACT on the substrate SUB and may be disposed with a uniform thickness along the contour of the active layer ACT. The gate insulating layer GID may include an inorganic insulating material. Examples of inorganic insulating materials that may be used as the gate insulating layer GID may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0085] Each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may be disposed on the gate insulating layer GID. The first gate electrode GE1 may overlap with the first channel region of the first active pattern ACT1. The second gate electrode GE2 may overlap with the second channel region of the second active pattern ACT2. The third gate electrode GE3 may overlap with the third channel region of the third active pattern ACT3. Each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0086] The interlayer insulating layer ILD may be disposed on the gate insulating layer GID. The interlayer insulating layer ILD may cover the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 on the gate insulating layer GID, and may have a substantially flat upper surface without generating a step difference around the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3. Optionally, the interlayer insulating layer ILD may cover the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 on the gate insulating layer GID, and may be disposed with a uniform thickness along the contours of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3. The interlayer insulating layer ILD may include an inorganic insulating material. Examples of inorganic insulating materials that may be used as the interlayer insulating layer ILD may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other.

[0087] The first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 and the first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3 may be disposed on the interlayer insulating layer ILD. The first source electrode SE1 may be connected to the first source region of the first active pattern ACT1 through a contact hole formed through the gate insulating layer GID and the interlayer insulating layer ILD in the third direction DR3. The first drain electrode DE1 may be connected to the first drain region of the first active pattern ACT1 through a contact hole formed through the gate insulating layer GID and the interlayer insulating layer ILD in the third direction DR3. The second source electrode SE2 may be connected to the second source region of the second active pattern ACT2 through a contact hole formed through the gate insulating layer GID and the interlayer insulating layer ILD in the third direction DR3. The second drain electrode DE2 may be connected to the second drain region of the second active pattern ACT2 through a contact hole formed through the gate insulating layer GID and the interlayer insulating layer ILD in the third direction DR3. The third source electrode SE3 may be connected to the third source region of the third active pattern ACT3 through a contact hole formed through the gate insulating layer GID and the interlayer insulating layer ILD in the third direction DR3. The third drain electrode DE3 may be connected to the third drain region of the third active pattern ACT3 through a contact hole formed through the gate insulating layer GID and the interlayer insulating layer ILD in the third direction DR3. Each of the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 and the first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0088] Thus, a first thin film transistor TFT1 including a first active pattern ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1 may be formed. In addition, a second thin film transistor TFT2 including a second active pattern ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2 may be formed. In addition, a third thin film transistor TFT3 including a third active pattern ACT3, a third gate electrode GE3, a third source electrode SE3, and a third drain electrode DE3 may be formed. Each of the first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 may be used as a driving transistor. In other words, each of the first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3 may correspond to Figure 6 The first transistor T1 is shown in FIG.

[0089] The first via insulating layer VIA1 may be disposed on the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 and the first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3 on the interlayer insulating layer ILD. The first via insulating layer VIA1 may be disposed on the interlayer insulating layer ILD with a relatively thick thickness to fully cover the first source electrode SE1, the second source electrode SE2, and the third source electrode SE3 and the first drain electrode DE1, the second drain electrode DE2, and the third drain electrode DE3. The first via insulating layer VIA1 may include an organic insulating material. Examples of organic insulating materials that may be used as the first via insulating layer VIA1 may include photoresist, polyacrylic acid-based resins, polyimide-based resins, polyamide-based resins, siloxane-based resins, acrylic acid-based resins, epoxy-based resins, and the like. These may be used alone or in combination with one another.

[0090] The first lower connection electrode LCE1, the second lower connection electrode LCE2, and the third lower connection electrode LCE3 may be disposed on the first via insulating layer VIA1. The first lower connection electrode LCE1 may be connected to the first drain electrode DE1 through a contact hole formed through the first via insulating layer VIA1 in the third direction DR3. The second lower connection electrode LCE2 may be connected to the second drain electrode DE2 through a contact hole formed through the first via insulating layer VIA1 in the third direction DR3. The third lower connection electrode LCE3 may be connected to the third drain electrode DE3 through a contact hole formed through the first via insulating layer VIA1 in the third direction DR3. For example, each of the first lower connection electrode LCE1, the second lower connection electrode LCE2, and the third lower connection electrode LCE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0091] The second via insulating layer VIA2 may be disposed on the first via insulating layer VIA1 on the first lower connection electrode LCE1, the second lower connection electrode LCE2, and the third lower connection electrode LCE3. The second via insulating layer VIA2 may be disposed to have a relatively thick thickness to fully cover the first lower connection electrode LCE1, the second lower connection electrode LCE2, and the third lower connection electrode LCE3. The second via insulating layer VIA2 may include an organic insulating material. Examples of organic insulating materials that may be used as the second via insulating layer VIA2 may include photoresists, polyacrylic acid-based resins, polyimide-based resins, polyamide-based resins, siloxane-based resins, acrylic acid-based resins, epoxy-based resins, and the like. These may be used alone or in combination with one another.

[0092] The first upper connection electrode UCE1, the second upper connection electrode UCE2, and the third upper connection electrode UCE3 may be disposed on the second via insulating layer VIA2. The first upper connection electrode UCE1 may be connected to the first lower connection electrode LCE1 through a contact hole formed through the second via insulating layer VIA2 in the third direction DR3. The second upper connection electrode UCE2 may be connected to the second lower connection electrode LCE2 through a contact hole formed through the second via insulating layer VIA2 in the third direction DR3. The third upper connection electrode UCE3 may be connected to the third lower connection electrode LCE3 through a contact hole formed through the second via insulating layer VIA2 in the third direction DR3. For example, each of the first upper connection electrode UCE1, the second upper connection electrode UCE2, and the third upper connection electrode UCE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0093] Therefore, the first lower connection electrode LCE1 and the first upper connection electrode UCE1 can electrically connect the first thin film transistor TFT1 and the first light emitting element LD1. The second lower connection electrode LCE2 and the second upper connection electrode UCE2 can electrically connect the second thin film transistor TFT2 and the second light emitting element LD2. The third lower connection electrode LCE3 and the third upper connection electrode UCE3 can electrically connect the third thin film transistor TFT3 and the third light emitting element LD3.

[0094] The third via insulating layer VIA3 may be disposed on the first upper connection electrode UCE1, the second upper connection electrode UCE2, and the third upper connection electrode UCE3 on the second via insulating layer VIA2. The third via insulating layer VIA3 may be disposed to have a relatively thick thickness to fully cover the first upper connection electrode UCE1, the second upper connection electrode UCE2, and the third upper connection electrode UCE3. The third via insulating layer VIA3 may include an organic insulating material. Examples of organic insulating materials that may be used as the third via insulating layer VIA3 may include photoresist, polyacrylic acid-based resin, polyimide-based resin, polyamide-based resin, siloxane-based resin, acrylic acid-based resin, epoxy-based resin, etc. These may be used alone or in combination with each other.

[0095] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed on the third via insulating layer VIA3. The first pixel electrode AE1 may be connected to the first upper connection electrode UCE1 through a contact hole formed through the third via insulating layer VIA3 in the third direction DR3. The second pixel electrode AE2 may be connected to the second upper connection electrode UCE2 through a contact hole formed through the third via insulating layer VIA3 in the third direction DR3. The third pixel electrode AE3 may be connected to the third upper connection electrode UCE3 through a contact hole formed through the third via insulating layer VIA3 in the third direction DR3. Each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These may be used alone or in combination with each other. For example, each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be used as an anode electrode.

[0096] The pixel defining layer PDL may be disposed on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 on the third via insulating layer VIA3. The pixel defining layer PDL may cover the edge of each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3, and may expose a portion of the upper surface of each of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The pixel defining layer PDL may include an organic insulating material. Examples of organic insulating materials that may be used as the pixel defining layer PDL may include photoresists, polyacrylic acid-based resins, polyimide-based resins, polyamide-based resins, siloxane-based resins, acrylic acid-based resins, epoxy-based resins, and the like. These may be used alone or in combination with each other. In an embodiment, the pixel defining layer PDL may include an inorganic or organic material, which includes a light blocking material having a black color.

[0097] The first light-emitting layer EL1 may be disposed on the first pixel electrode AE1, the second light-emitting layer EL2 may be disposed on the second pixel electrode AE2, and the third light-emitting layer EL3 may be disposed on the third pixel electrode AE3. In addition, the first light-emitting layer EL1 may overlap with the first light-emitting region EA1, the second light-emitting layer EL2 may overlap with the second light-emitting region EA2, and the third light-emitting layer EL3 may overlap with the third light-emitting region EA3. The first light-emitting layer EL1, the second light-emitting layer EL2, and the third light-emitting layer EL3 may include an organic material that emits light of a preset color. For example, the first light-emitting layer EL1 may include an organic material that emits red light, the second light-emitting layer EL2 may include an organic material that emits blue light, and the third light-emitting layer EL3 may include an organic material that emits green light. However, the present disclosure is not limited thereto.

[0098] The common electrode CTE may be disposed on the first light emitting layer EL1, the second light emitting layer EL2, and the third light emitting layer EL3 on the pixel defining layer PDL. The common electrode CTE may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other. For example, the common electrode CTE may be used as a cathode electrode.

[0099] Thus, a first light emitting element LD1 including a first pixel electrode AE1, a first light emitting layer EL1 and a common electrode CTE may be formed. In addition, a second light emitting element LD2 including a second pixel electrode AE2, a second light emitting layer EL2 and a common electrode CTE may be formed. In addition, a third light emitting element LD3 including a third pixel electrode AE3, a third light emitting layer EL3 and a common electrode CTE may be formed.

[0100] An encapsulation layer (not shown) may be disposed on the common electrode CTE. The encapsulation layer may prevent impurities, moisture, etc. from penetrating into the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 from the outside. The encapsulation layer may include at least one inorganic layer and at least one organic layer. For example, the inorganic layer may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) etc. These may be used alone or in combination with each other. For example, the organic layer may include a cured polymer such as polyacrylate.

[0101] Although the display device DD1 including an organic light emitting display (OLED) device is shown as an example, the configuration of the present disclosure is not limited thereto. In other embodiments, the display device DD1 may include a liquid crystal display (LCD) device, a field emission display (FED) device, a plasma display panel (PDP) device, an electrophoretic image display (EPD) device, an inorganic light emitting display (ILED) device, or a quantum dot display device.

[0102] Figure 5 It is shown Figure 1 A block diagram of a display device.

[0103] refer to Figure 5 , the display device DD1 may include a display panel 100 and a display panel driver. The display panel 100 may include a display portion 110 that displays an image and a peripheral portion 120 disposed adjacent to the display portion 110. The peripheral portion 120 may include a gate driver 300 and an emission driver 500. The display panel driver may drive the display panel 100. The display panel driver may include a driving controller 200, a gate driver 300, and a data driver 400.

[0104] The display panel 100 may include gate signal lines GWL, GIL, and GCL, data lines DL, emission signal lines EML, and pixels PX connected to the gate signal lines GWL, GIL, and GCL, the data lines DL, and the emission signal lines EML.

[0105] The gate signal lines GWL, GIL, and GCL and the emission signal lines EML may extend in the second direction DR2. The data lines DL may extend in the first direction DR1.

[0106] The driving controller 200 may receive input image data IMG and input control signals CONT from a host processor (e.g., a graphics processing unit (GPU)). For example, the input image data IMG may include red image data, green image data, and blue image data. The input control signals CONT may include a main clock signal, a data enable signal, etc. The input control signals CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0107] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and output image data OIMG based on input image data IMG and an input control signal CONT.

[0108] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and may output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0109] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 400 based on the input control signal CONT, and may output the second control signal CONT2 to the data driver 400. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0110] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the emission driver 500 based on the input control signal CONT, and may output the third control signal CONT3 to the emission driver 500. The third control signal CONT3 may include a vertical start signal and an emission clock signal.

[0111] The driving controller 200 may receive input image data IMG and an input control signal CONT, and may generate output image data OIMG. The driving controller 200 may output the output image data OIMG to the data driver 400.

[0112] The gate driver 300 may generate a gate signal for output to the gate signal lines GWL, GIL, and GCL in response to the first control signal CONT1 received from the driving controller 200. The gate signal may include a write gate signal (eg, Figure 6 Write gate signal GW), initialization gate signal (for example, Figure 6 The initialization gate signal GI) and the compensation gate signal (eg, Figure 6 compensation gate signal GC).

[0113] The gate signal line may include a write gate line GWL, an initialization gate line GIL, and a compensation gate line GCL. For example, the gate driver 300 may output a write gate signal to the write gate line GWL. The gate driver 300 may output an initialization gate signal to the initialization gate line GIL. The gate driver 300 may output a compensation gate signal to the compensation gate line GCL.

[0114] The data driver 400 may receive the second control signal CONT2 and the output image data OIMG from the driving controller 200. The data driver 400 may generate a data voltage (eg, Figure 6The data driver 400 may output the data voltage DATA to the data line DL.

[0115] The emission driver 500 may receive the third control signal CONT3 from the driving controller 200. The emission driver 500 may generate an emission control signal (eg, Figure 6 The emission driver 500 may output the emission control signal to the emission signal line EML.

[0116] exist Figure 5 , for ease of description, the gate driver 300 is shown as being disposed on a first side of the display portion 110, and the emission driver 500 is shown as being disposed on a second side of the display portion 110. However, the present disclosure is not limited thereto. For example, both the gate driver 300 and the emission driver 500 may be disposed on a first side of the display portion 110, or the gate driver 300 and the data driver 400 may be disposed to face each other, with the display portion 110 disposed therebetween. In an embodiment, the gate driver 300 and the emission driver 500 may be integrally formed. Figure 1 The first driver D-IC shown may be used as the data driver 400, and Figure 1 The illustrated second driver GDV may be used as the gate driver 300 and the emission driver 500 .

[0117] Figure 6 It is shown that the Figure 1 A circuit diagram of a pixel in a display device.

[0118] refer to Figure 6 , each of the pixels PX may include a first light emitting element LD1 and a first pixel circuit, and the first pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 and a storage capacitor CST. However, the present disclosure is not limited thereto. For example, some of the configurations of the pixel circuit PXC may be omitted, and other configurations may be added to the pixel circuit PXC. The description of the first light emitting element LD1 and the first pixel circuit may be replaced by Figure 4 The description of the second light emitting element LD2 and the second pixel circuit shown in FIG. In addition, the description of the first light emitting element LD1 and the first pixel circuit can be replaced by Figure 4 Description of the third light emitting element LD3 and the third pixel circuit shown.

[0119] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to a gate node GN. The first electrode of the first transistor T1 may be connected to a first node N1. The second electrode of the first transistor T1 may be connected to a second node N2. The first transistor T1 may generate a driving current based on a voltage difference between the gate electrode and the first electrode. For example, the first transistor T1 may be referred to as a driving transistor.

[0120] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the second transistor T2 may receive a write gate signal GW. The second transistor T2 may be turned on or off in response to the write gate signal GW provided to the gate electrode of the second transistor T2. The first electrode of the second transistor T2 may receive a data voltage DATA. The second electrode of the second transistor T2 may be connected to the first node N1. When the second transistor T2 is turned on, the second transistor T2 may provide the data voltage DATA to the first electrode of the first transistor T1. For example, the second transistor T2 may be referred to as a write transistor.

[0121] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. The third transistor T3 may be connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. That is, the first electrode of the third transistor T3 may be connected to the gate node GN, and the second electrode of the third transistor T3 may be connected to the second node N2. The gate electrode of the third transistor T3 may receive the compensation gate signal GC. The third transistor T3 may be turned on or off in response to the compensation gate signal GC. When the third transistor T3 is turned on, the third transistor T3 may make the first transistor T1 diode-connected. That is, the third transistor T3 may compensate for the threshold voltage of the first transistor T1. For example, the third transistor T3 may be referred to as a compensation transistor.

[0122] like Figure 6 As shown, the third transistor T3 may have a single transistor structure. Alternatively, the third transistor T3 may have a double transistor structure, in which two transistors are connected in series.

[0123] The fourth transistor T4 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the fourth transistor T4 may receive an initialization gate signal GI. The fourth transistor T4 may be turned on or off in response to the initialization gate signal GI provided to the gate electrode of the fourth transistor T4. A gate initialization voltage VINT may be provided to the first electrode of the fourth transistor T4. The second electrode of the fourth transistor T4 may be connected to the gate node GN. When the fourth transistor T4 is turned on, the gate initialization voltage VINT may be provided to the gate electrode of the first transistor T1. For example, the fourth transistor T4 may be referred to as a gate initialization transistor.

[0124] like Figure 6 As shown, the fourth transistor T4 may have a single transistor structure. Alternatively, the fourth transistor T4 may have a double transistor structure, in which two transistors are connected in series.

[0125] The fifth transistor T5 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the fifth transistor T5 may receive an emission control signal EM. The fifth transistor T5 may be turned on or off in response to the emission control signal EM. A driving voltage ELVDD may be provided to the first electrode of the fifth transistor T5. The second electrode of the fifth transistor T5 may be connected to the first node N1. When the fifth transistor T5 is turned on, the fifth transistor T5 may provide a driving voltage ELVDD to the first electrode of the first transistor T1. For example, the fifth transistor T5 may be referred to as a first emission control transistor.

[0126] The sixth transistor T6 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the sixth transistor T6 may receive an emission control signal EM. In response to the emission control signal EM, the sixth transistor T6 may be turned on or off. The first electrode of the sixth transistor T6 may be connected to the second node N2. The second electrode of the sixth transistor T6 may be connected to the third node N3. When the sixth transistor T6 is turned on, the sixth transistor T6 may provide a driving current generated by the first transistor T1 to the first light emitting element LD1. For example, the sixth transistor T6 may be referred to as a second emission control transistor.

[0127] The seventh transistor T7 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the seventh transistor T7 may receive a write gate signal GW. The seventh transistor T7 may be turned on or off in response to the write gate signal GW. An anode initialization voltage VAINT may be provided to the first electrode of the seventh transistor T7. The second electrode of the seventh transistor T7 may be connected to the third node N3. When the seventh transistor T7 is turned on, the seventh transistor T7 may provide an anode initialization voltage VAINT to the anode electrode of the first light emitting element LD1. For example, the seventh transistor T7 may be referred to as an anode initialization transistor.

[0128] In an implementation, each of the first transistor T1 , the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 may be a PMOS transistor, and each of the third transistor T3 and the fourth transistor T4 may be an NMOS transistor.

[0129] Therefore, the active pattern of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a cation-doped silicon semiconductor. The active pattern of each of the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor.

[0130] The write gate signal GW for turning on each of the second transistor T2 and the seventh transistor T7 may have a low level. The emission control signal EM for turning on each of the fifth transistor T5 and the sixth transistor T6 may have a low level. The compensation gate signal GC for turning on the third transistor T3 may have a high level. The initialization gate signal GI for turning on the fourth transistor T4 may have a high level.

[0131] The storage capacitor CST may include a first electrode and a second electrode. The driving voltage ELVDD may be provided to the first electrode of the storage capacitor CST. The second electrode of the storage capacitor CST may be connected to the gate node GN. The storage capacitor CST may maintain the voltage level of the gate electrode of the first transistor T1 even when the second transistor T2 is turned off.

[0132] The first light emitting element LD1 may include an anode electrode and a cathode electrode. The anode electrode of the first light emitting element LD1 may be connected to the third node N3. The common voltage ELVSS may be supplied to the cathode electrode of the first light emitting element LD1. The first light emitting element LD1 may generate light having brightness corresponding to the driving current.

[0133] Figure 7 , Figure 8 , Fig. 9 and Fig.10 It is shown Figure 1 A plan view of a display device.

[0134] refer to Figure 7 and Figure 8 The display device DD1 according to the first embodiment of the present disclosure may include a substrate SUB, a second driver GDV, a light emitting element LD, a pixel circuit group GPXC, a data line, a first connection line CJL1, a second connection line CJL2, and a signal line DSL.

[0135] The pixel circuit group GPXC may be disposed in the display area DA on the substrate SUB. The pixel circuit group GPXC may be arranged in a matrix form along the first direction DR1 and the second direction DR2. The pixel circuit groups GPXC may be spaced apart from each other by a predetermined distance. That is, a separation space SPS in which no pixel circuit PXC is disposed may be defined between the pixel circuit groups GPXC. The separation space SPS may include a first separation space SPS1 and a second separation space SPS2. The first separation space SPS1 may be a separation space between the pixel circuit groups GPXC arranged along the first direction DR1. The second separation space SPS2 may be a separation space between the pixel circuit groups GPXC arranged along the second direction DR2.

[0136] The light emitting elements LD may be disposed in the display area DA on the substrate SUB. The light emitting elements LD may be arranged in a matrix along the first direction DR1 and the second direction DR2. In addition, the light emitting elements LD may be located in a separation space SPS (eg, a first separation space SPS1) between the pixel circuit groups GPXC.

[0137] The second driver GDV may be disposed on the substrate SUB in a non-display area (eg, Figure 1 Specifically, the second driver GDV may be disposed in the second driver area (eg, Figure 1 The second driver GDV may provide a driving signal to the pixel circuit PXC.

[0138] The first connection line CJL1 may be connected to the second driver GDV and may extend in the first direction DR1. Specifically, the first connection line CJL1 may be connected to the second driver GDV in the non-display area. The first connection line CJL1 may receive a driving signal from the second driver GDV. The first connection line CJL1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, the first connection line CJL1 may be connected to a second driver GDV in the non-display area. Figure 4 The first lower connection electrode LCE1, the second lower connection electrode LCE2 and the third lower connection electrode LCE3 on the first via insulating layer VIA1 are arranged in the same layer. Figure 4 The first connection line CJL1 is formed of the same material and through the same process as the first lower connection electrode LCE1, the second lower connection electrode LCE2, and the third lower connection electrode LCE3.

[0139] The second connection line CJL2 may be connected to the first connection line CJL1 and may extend in the second direction DR2. Specifically, the second connection line CJL2 may be connected to the first connection line CJL1 at the second contact point JP2 in the display area DA. More specifically, the second connection line CJL2 may be connected to the first connection line CJL1 in the separation space SPS (e.g., the first separation space SPS1) between the pixel circuit groups GPXC at the second contact point JP2. The second connection line CJL2 may receive a driving signal via the first connection line CJL1.

[0140] In an embodiment, the second contact point JP2 may be located in a first separation space SPS1 between the pixel circuit groups GPXC arranged along the first direction DR1. In other words, the second contact point JP2 may be located in a space spaced apart in the up-down direction between the pixel circuit groups GPXC in a plan view. In this case, the second connection line CJL2 may be spaced apart from the pixel circuit PXC in a plan view. In addition, at least a portion of the second connection line CJL2 may overlap with the light emitting element LD in a plan view.

[0141] The second connection line CJL2 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. In an embodiment, the second connection line CJL2 may include aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), titanium (Ti), etc. That is, the second connection line CJL2 may include a low resistance metal. These may be used alone or in combination with each other.

[0142] In an embodiment, the second connection line CJL2 can be connected to the Figure 4 The first, second, and third source electrodes SE1, SE2, and SE3 and the first, second, and third drain electrodes DE1, DE2, and DE3 on the interlayer insulating layer ILD are disposed in the same layer.

[0143] That is, you can use Figure 4 The second connection line CJL2 is formed of the same material and through the same process as the first, second, and third source electrodes SE1, SE2, and SE3 and the first, second, and third drain electrodes DE1, DE2, and DE3.

[0144] The signal line DSL may be connected to the second connection line CJL2. In an embodiment, the signal line DSL may include a portion extending in the second direction DR2 and a portion extending in the first direction DR1. For example, the signal line DSL may extend in the second direction DR2 at the display area DA, and may extend in the first direction DR1 at the non-display area (e.g., the peripheral area PA). Specifically, the signal line DSL may be connected to the second connection line CJL2 at a first contact point JP1 in the non-display area (e.g., the peripheral area PA). The signal line DSL may receive a drive signal via the second connection line CJL2. The signal line DSL may overlap with the pixel circuit PXC located in the same row (i.e., the pixel circuit PXC arranged along the second direction DR2) in a plan view. The signal line DSL may transmit a drive signal to the pixel circuit PXC located in the same row. The signal line DSL may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0145] In an embodiment, the second driver GDV may be positioned in the first direction DR1 from the display area DA, and the first contact point JP1 may be positioned in the second direction DR2 from the display area DA. For example, the second driver GDV may be located in a non-display area disposed adjacent to the display area DA in the first direction DR1, for example, in a non-display area on the upper side of the display area DA. The first contact point JP1 may be located in a non-display area disposed adjacent to the display area DA in the second direction DR2, for example, in a non-display area on the left and / or right side of the display area DA. In other words, the first contact point JP1 may be located in the peripheral area PA on the left and / or right side of the display area DA.

[0146] Although in Figure 7 and Figure 8 , but the data lines (e.g. Figure 1 The data lines DL) may extend in the first direction DR1 and may be arranged along the second direction DR2. Each of the data lines may be connected to the first driver (eg, Figure 1 Each of the data lines may receive a data voltage from the first driver. Each of the data lines may overlap with a pixel circuit PXC located in the same column (i.e., a pixel circuit PXC arranged along the first direction DR1) in a plan view. Each of the data lines may transmit a data voltage to the pixel circuit PXC located in the same column.

[0147] In an embodiment, if Figure 7As shown, the second driver GDV may include a gate driver 300 that provides a gate signal, the first connection line CJL1 may include a first gate connection line GJL1 connected to the gate driver 300, and the second connection line CJL2 may include a second gate connection line GJL2 connected to the first gate connection line GJL1. In addition, the signal line DSL may include a gate signal line GL that is connected to the second gate connection line GJL2 and transmits a gate signal provided from the gate driver 300. The second gate connection line GJL2 may be connected to the first gate connection line GJL1 in the first separation space SPS1 at a second contact point JP2. The gate signal line GL may be connected to the second gate connection line GJL2 in the peripheral area PA on the left and / or right side of the display area DA at the first contact point JP1.

[0148] In an embodiment, if Figure 8 As shown, the second driver GDV may include an emission driver 500 that provides an emission control signal, the first connection line CJL1 may include a first emission connection line EJL1 connected to the emission driver 500, and the second connection line CJL2 may include a second emission connection line EJL2 connected to the first emission connection line EJL1. In addition, the signal line DSL may include an emission signal line EML that is connected to the second emission connection line EJL2 and transmits an emission control signal provided from the emission driver 500. The second emission connection line EJL2 may be connected to the first emission connection line EJL1 in the first separation space SPS1 at a second contact point JP2. The emission signal line EML may be connected to the second emission connection line EJL2 in the peripheral area PA on the left and / or right side of the display area DA at the first contact point JP1.

[0149] When the second connection line CJL2 is connected to the first connection line CJL1 transmitting the driving signal at the second contact point JP2 in the area overlapping the pixel circuit PXC in the plan view, the brightness of the light emitted by the light-emitting element LD connected to the pixel circuit PXC overlapping the second contact point JP2 in the plan view may be different from the brightness of the light emitted by the light-emitting element LD connected to the pixel circuit PXC spaced apart from the second contact point JP2 in the plan view.

[0150] Similarly, when the signal line DSL is connected to the second connection line CJL2 transmitting the driving signal in the area overlapping the pixel circuit PXC in the plan view at the first contact point JP1, the brightness of the light emitted by the light emitting element LD connected to the pixel circuit PXC overlapping the first contact point JP1 in the plan view may be different from the brightness of the light emitted by the light emitting element LD connected to the pixel circuit PXC spaced apart from the first contact point JP1 in the plan view. Due to the brightness difference between the lights emitted by the light emitting elements LD, a display defect such as a spot may occur in the display device.

[0151] In order to suppress the display defect in which spots are visible in the display device DD1 according to the first embodiment of the present disclosure, the second connection line CJL2 may be connected to the first connection line CJL1 in the separation space SPS between the pixel circuit groups GPXC at the second contact point JP2, and the signal line DSL may be connected to the second connection line CJL2 in the peripheral area PA at the first contact point JP1. In other words, each of the first contact point JP1 and the second contact point JP2 may be spaced apart from the pixel circuit PXC in a plan view. Therefore, the brightness difference between the lights emitted by the light emitting element LD may be reduced or prevented, and the display defect in which spots are visible in the display device DD1 may be suppressed.

[0152] Further references Fig. 9 The display device DD1 according to the first embodiment of the present disclosure may further include a constant voltage line CVL. The constant voltage line CVL may include a first constant voltage line CVL1 and a second constant voltage line CVL2.

[0153] The first constant voltage line CVL1 may be connected to the second driver GDV and may extend in the first direction DR1. Specifically, the first constant voltage line CVL1 may be connected to the second driver GDV in the non-display area. The first constant voltage line CVL1 may overlap with the pixel circuits PXC located in the same column (i.e., the pixel circuits PXC arranged along the first direction DR1) in a plan view. The first constant voltage line CVL1 may receive a constant voltage from the second driver GDV. For example, the constant voltage may include Figure 6 The driving voltage ELVDD, the common voltage ELVSS, the gate initialization voltage VINT and the anode initialization voltage VAINT are shown.

[0154] The second constant voltage line CVL2 may be connected to the first constant voltage line CVL1 and may extend in the second direction DR2. The second constant voltage line CVL2 may overlap with the pixel circuits PXC located in the same row (i.e., the pixel circuits PXC arranged along the second direction DR2) in a plan view. The second constant voltage line CVL2 may be connected to the first constant voltage line CVL1 in the display area DA at the third contact point JP3. The second constant voltage line CVL2 may receive a constant voltage via the first constant voltage line CVL1. Therefore, the second constant voltage line CVL2 may transmit a constant voltage to the pixel circuits PXC located in the same row.

[0155] In an embodiment, the third contact point JP3 may overlap each of the pixel circuits PXC in a plan view. Since the constant voltage line CVL transmits a constant voltage instead of a driving signal, the brightness of light emitted by the light emitting element LD connected to the pixel circuit PXC overlapping the third contact point JP3 in a plan view may be the same as the brightness of light emitted by the light emitting element LD connected to the pixel circuit PXC spaced apart from the third contact point JP3 in a plan view.

[0156] In other words, even if the second constant voltage line CVL2 is connected to the first constant voltage line CVL1 transmitting a constant voltage in a region overlapping the pixel circuit PXC in plan view, a brightness difference may not occur between lights emitted by the light emitting elements LD.

[0157] The constant voltage line CVL may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other. In an embodiment, the first constant voltage line CVL1 may be connected to a first constant voltage line CVL2 disposed at Figure 4 The first upper connection electrode UCE1, the second upper connection electrode UCE2 and the third upper connection electrode UCE3 on the second via insulating layer VIA2 are arranged in the same layer. Figure 4 The first constant voltage line CVL1 is formed of the same material and through the same process as the first upper connection electrode UCE1, the second upper connection electrode UCE2 and the third upper connection electrode UCE3.

[0158] Further references Fig.10 , each of the gate signal line GL, the emission signal line EML, and the second constant voltage line CVL2 may extend in the second direction DR2 and may overlap with the pixel circuit PXC located in the same row in a plan view. In an embodiment, the gate signal line GL, the emission signal line EML, and the second constant voltage line CVL2 may be formed using the same material and by the same process. However, the present disclosure is not limited thereto.

[0159] The second driver GDV may provide a gate signal, an emission control signal, and a constant voltage. The gate signal may include a compensation gate signal (eg, Figure 6 The compensation gate signal GC), the write gate signal (for example, Figure 6 The write gate signal GW) and the initialization gate signal (for example, Figure 6 initialization gate signal GI).

[0160] The gate signal line GL may include a compensation gate line GCL, a write gate line GWL, and an initialization gate line GIL. The compensation gate line GCL may transmit a compensation gate signal provided from the second driver GDV to the pixel circuit PXC located in the same row. The write gate line GWL may transmit a write gate signal provided from the second driver GDV to the pixel circuit PXC located in the same row. The initialization gate line GIL may transmit an initialization gate signal provided from the second driver GDV to the pixel circuit PXC located in the same row.

[0161] The emission signal line EML may transmit the emission control signal provided from the second driver GDV to the pixel circuits PXC located in the same row. The second constant voltage line CVL2 may transmit the constant voltage provided from the second driver GDV to the pixel circuits PXC located in the same row.

[0162] Fig.11 is a plan view showing a display device according to a second embodiment of the present disclosure.

[0163] refer to Fig.11 , the display device DD2 according to the second embodiment of the present disclosure may include a substrate SUB, a second driver GDV, a light emitting element LD, a pixel circuit group GPXC, and a constant voltage line CVL′.

[0164] In addition to the constant voltage line CVL', Fig.11 The display device DD2 shown can be used with reference Figure 7 , Figure 8 , Fig. 9 and Fig.10 The display device DD1 described in the present invention is substantially the same as that described in the present invention. Figure 7 , Figure 8 , Fig. 9 and Fig.10 A description of the overlap is given of the description of the display device DD1.

[0165] The constant voltage line CVL' may include a first constant voltage line CVL1' and a second constant voltage line CVL2'. The first constant voltage line CVL1' may be connected to the second driver GDV and may extend in the first direction DR1. In an embodiment, the first constant voltage line CVL1' may be spaced apart from the pixel circuit PXC in a plan view. The first constant voltage line CVL1' may receive a constant voltage from the second driver GDV.

[0166] The second constant voltage line CVL2' may be connected to the first constant voltage line CVL1' and may extend in the second direction DR2. The second constant voltage line CVL2' may overlap with the pixel circuit PXC located in the same row in a plan view. The second constant voltage line CVL2' may be connected to the first constant voltage line CVL1' at the third contact point JP3' in the display area DA. The second constant voltage line CVL2' may receive a constant voltage via the first constant voltage line CVL1'. Therefore, the second constant voltage line CVL2' may transmit a constant voltage to the pixel circuit PXC located in the same row.

[0167] In an embodiment, the third contact point JP3' may be located in the separation space SPS between the pixel circuit groups GPXC. For example, the third contact point JP3' may be located in the second separation space SPS2 between the pixel circuit groups GPXC arranged along the second direction DR2. In other words, the third contact point JP3' may be located in the space between the pixel circuit groups GPXC arranged in the left-right direction in a plan view.

[0168] Fig.12 is a plan view showing a display device according to a third embodiment of the present disclosure.

[0169] refer to Fig.12 , the display device DD3 according to the third embodiment of the present disclosure may include a substrate SUB, a second driver GDV, a light emitting element LD, a pixel circuit group GPXC, and a constant voltage line CVL".

[0170] In addition to the constant voltage line CVL", Fig.12 The display device DD3 shown can be used with reference Figure 7 , Figure 8 , Fig. 9 and Fig.10 The display device DD1 described in the present invention is substantially the same as that described in the present invention. Figure 7 , Figure 8 , Fig. 9 and Fig.10 A description of the overlap is given of the description of the display device DD1.

[0171] The constant voltage line CVL” may include a first constant voltage line CVL1”, a second constant voltage line CVL2”, and a third constant voltage line CVL3. The first constant voltage line CVL1” may be connected to the second driver GDV and may extend in the first direction DR1. The first constant voltage line CVL1” may overlap with the pixel circuit PXC located in the same column in a plan view. The first constant voltage line CVL1” may receive a constant voltage from the second driver GDV.

[0172] The second constant voltage line CVL2" may be connected to the first constant voltage line CVL1" and may extend in the second direction DR2. In an embodiment, the second constant voltage line CVL2" may be spaced apart from the pixel circuit PXC in a plan view. The second constant voltage line CVL2" may be connected to the first constant voltage line CVL1" at a third contact point JP3" in the display area DA. The second constant voltage line CVL2" may receive a constant voltage via the first constant voltage line CVL1".

[0173] In an embodiment, the third contact point JP3" may be located in a separation space SPS between pixel circuit groups GPXC. For example, the third contact point JP3" may be located in a first separation space SPS1 between pixel circuit groups GPXC arranged along a first direction DR1. In other words, the third contact point JP3" may be located in a space between pixel circuit groups GPXC arranged in an up-and-down direction in a plan view.

[0174] The third constant voltage line CVL3 can be connected to the second constant voltage line CVL2” and can extend in the second direction DR2. Specifically, the third constant voltage line CVL3 can be connected to the second constant voltage line CVL2” in the peripheral area PA. The third constant voltage line CVL3 can receive a constant voltage via the second constant voltage line CVL2”. The third constant voltage line CVL3 can overlap with the pixel circuit PXC located in the same row in a plan view. The third constant voltage line CVL3 can transmit a constant voltage to the pixel circuit PXC located in the same row.

[0175] Fig.13 is a plan view showing a display device according to a fourth embodiment of the present disclosure.

[0176] refer to Fig.13 The display device DD4 according to the fourth embodiment of the present disclosure may include a substrate SUB, a second driver GDV, a light emitting element LD, a pixel circuit group GPXC, a first connection line CJL1, a second connection line CJL2, and a signal line DSL.

[0177] Except for the position where the first connection line CJL1 and the second connection line CJL2 are connected, Fig.13The display device DD4 shown can be used with reference Figure 7 , Figure 8 , Fig. 9 and Fig.10 The display device DD1 described in the present invention is substantially the same as that described in the present invention. Figure 7 , Figure 8 , Fig. 9 and Fig.10 A description of the overlap is given of the description of the display device DD1.

[0178] The first connection line CJL1 may be connected to the second driver GDV and may extend in the first direction DR1. The first connection line CJL1 may receive a driving signal from the second driver GDV. The first connection line CJL1 may include a first gate connection line GJL1 and a first emission connection line EJL1.

[0179] The second connection line CJL2 may be connected to the first connection line CJL1 and may extend in the second direction DR2. The second connection line CJL2 may be connected to the first connection line CJL1 in the separation space SPS between the pixel circuit groups GPXC at the second contact point JP2'. The second connection line CJL2 may receive a driving signal via the first connection line CJL1. The second connection line CJL2 may include a second gate connection line GJL2 and a second emission connection line EJL2.

[0180] In an embodiment, the second contact point JP2' may be located in the second separation space SPS2 between the pixel circuit groups GPXC arranged along the second direction DR2. In other words, the second contact point JP2' may be located in the space between the pixel circuit groups GPXC arranged in the left and right directions in a plan view. In this case, the first connection line CJL1 may be spaced apart from the pixel circuit PXC in a plan view.

[0181] Fig.14 is a plan view showing a display device according to a fifth embodiment of the present disclosure.

[0182] refer to Fig.14 The display device DD5 according to the fifth embodiment of the present disclosure may include a substrate SUB, a second driver GDV, a light emitting element LD, a pixel circuit group GPXC, a first connection line CJL1, a second connection line CJL2, and a signal line DSL.

[0183] Except for the position where the first connection line CJL1 and the second connection line CJL2 are connected, Fig.14 The display device DD5 shown can be used with reference Figure 7 , Figure 8 , Fig. 9 and Fig.10The display device DD1 described in the present invention is substantially the same as that described in the present invention. Figure 7 , Figure 8 , Fig. 9 and Fig.10 A description of the overlap is given of the description of the display device DD1.

[0184] The first connection line CJL1 may be connected to the second driver GDV and may extend in the first direction DR1. The first connection line CJL1 may receive a driving signal from the second driver GDV. The first connection line CJL1 may include a first gate connection line GJL1 and a first emission connection line EJL1.

[0185] The second connection line CJL2 may be connected to the first connection line CJL1 and may extend in the second direction DR2. The second connection line CJL2 may be connected to the first connection line CJL1 in the separation space SPS between the pixel circuit groups GPXC at the second contact point JP2". The second connection line CJL2 may receive a driving signal via the first connection line CJL1. The second connection line CJL2 may include a second gate connection line GJL2 and a second emission connection line EJL2.

[0186] In an embodiment, the second contact point JP2" may be located in the first separation space SPS1 and the second separation space SPS2. In other words, the second contact point JP2" may be located in a space between pixel circuit groups GPXC arranged in an up-down direction and in a space between pixel circuit groups GPXC arranged in a left-right direction in a top view. In this case, the second connection line CJL2 forming the second contact point JP2" in the first separation space SPS1 may be spaced apart from the pixel circuit PXC in a plan view. In addition, the first connection line CJL1 forming the second contact point JP2" in the second separation space SPS2 may be spaced apart from the pixel circuit PXC in a plan view.

[0187] Fig.15 is a plan view showing a display device according to a sixth embodiment of the present disclosure. Fig.16 It is shown Fig.15 A side view of a display device showing a curved shape.

[0188] refer to Fig.15 and Fig.16 , the display device DD6 according to the sixth embodiment of the present disclosure may include a substrate SUB, a first driver D-IC, a second driver GDV, a pad portion PD, and a data line DL.

[0189] In addition to the first driver D-IC and the second driver GDV being positioned adjacent to each other, Fig.15 The display device DD6 shown can be used with reference Figures 1 to 6The display device DD1 described in the present invention is substantially the same as that described in the present invention. Figures 1 to 6 A description of the overlap is given of the description of the display device DD1.

[0190] The substrate SUB may include a display area DA and a non-display area NDA. The display area DA may be defined as an area where an image is displayed. The non-display area NDA may be defined as an area where an image is not displayed. The non-display area NDA may surround the display area DA. The non-display area NDA may include a peripheral area PA, a bending area BA, and a driver area DRA.

[0191] The peripheral area PA may be located around the display area DA. For example, the peripheral area PA may completely surround the display area DA.

[0192] The bending area BA may extend from one side of the peripheral area PA. In a plan view, the driver area DRA may extend from the bending area BA and be located under the display area DA or the peripheral area PA. The substrate SUB may be bent in the bending area BA about a reference axis parallel to the second direction DR2. In this case, as shown in FIG. Fig.16 As shown, the driver area DRA may be located on the lower surface of the display device DD6.

[0193] like Fig.15 As shown, when the display device DD6 is unfolded (ie, when the substrate SUB is unfolded), the bending area BA may be located between the display area DA and the driver area DRA. Specifically, when the display device DD6 is unfolded, the bending area BA may be located between the peripheral area PA and the driver area DRA.

[0194] The first driver D-IC may be disposed in the non-display area NDA on the substrate SUB and may be located on one side of the display area DA. Specifically, the first driver D-IC may be located in the driver area DRA on the substrate SUB. The first driver D-IC may provide a pixel circuit (e.g., Fig.17 For example, the first driver D-IC may be used as a data driver (eg, Figure 5 data driver 400).

[0195] The pad portion PD may be disposed in the driver area DRA on the substrate SUB. The pad portion PD may be electrically connected to the first driver D-IC and / or the printed circuit board.

[0196] The second driver GDV may be disposed in the non-display area NDA on the substrate SUB and located on one side of the display area DA. Specifically, the second driver GDV may be located in the driver area DRA on the substrate SUB. In this case, the pad portion PD, the first driver D-IC, and the second driver GDV may be sequentially arranged in the driver area DRA along the first direction DR1. The second driver GDV may provide a driving signal to the pixel circuit. The driving signal may include a gate signal and an emission control signal. For example, the second driver GDV may be used as a gate driver (e.g., Figure 5 ) and an emission driver (eg, Figure 5 of the transmitting driver 500).

[0197] The second driver GDV may be positioned in the first direction DR1 from the display area DA. In other words, the second driver GDV may be disposed adjacent to the display area DA in the first direction DR1. As described above, when the substrate SUB is bent in the bending area BA, the second driver GDV may be located on the lower surface of the display device DD6. Therefore, compared with a case where the second driver GDV is positioned in the second direction DR2 from the display area DA, the dead zone of the display device DD6 may be reduced.

[0198] Fig.17 and Fig.18 It is shown Fig.15 A plan view of a display device.

[0199] refer to Fig.15 , Fig.17 and Fig.18 The display device DD6 according to the sixth embodiment of the present disclosure may include a substrate SUB, a first driver D-IC, a second driver GDV, a light emitting element LD, a pixel circuit group GPXC, a data line DL, a first connection line CJL1, a second connection line CJL2, a signal line DSL and a constant voltage line CVL.

[0200] In addition to the first driver D-IC and the second driver GDV being positioned adjacent to each other, the display device DD6 may be connected to the reference Figures 7 to 10 The display device DD1 described in the present invention is substantially the same as that described in the present invention. Figures 7 to 10 A description of the overlap is given of the description of the display device DD1.

[0201] The pixel circuit group GPXC may be disposed in the display area DA on the substrate SUB. The pixel circuit group GPXC may be arranged in a matrix form along the first direction DR1 and the second direction DR2. A separation space SPS in which the pixel circuit PXC is not disposed may be defined between the pixel circuit groups GPXC. The separation space SPS may include a first separation space SPS1 and a second separation space SPS2. The first separation space SPS1 may be defined as a separation space between the pixel circuit groups GPXC arranged along the first direction DR1. The second separation space SPS2 may be defined as a separation space between the pixel circuit groups GPXC arranged along the second direction DR2.

[0202] The first driver D-IC may be disposed in the non-display area NDA on the substrate SUB. Specifically, the first driver D-IC may be disposed in the driver area DRA on the substrate SUB. The first driver D-IC may provide a data voltage to the pixel circuit PXC. Fig.17 and Fig.18 Although not shown in the figure, each of the data lines DL may extend in the first direction DR1, and the data lines DL may be arranged along the second direction DR2. Each of the data lines DL may receive a data voltage from the first driver D-IC. Each of the data lines DL may transmit the data voltage to the pixel circuits PXC located in the same column.

[0203] The second driver GDV may be disposed in the non-display area NDA on the substrate SUB. Specifically, the second driver GDV may be disposed in the driver area DRA on the substrate SUB. In an embodiment, the second driver GDV may be disposed in the driver area DRA to be adjacent to the first driver D-IC. The second driver GDV may provide a driving signal to the pixel circuit PXC. For example, the driving signal may include a gate signal and an emission control signal. The second driver GDV may include a gate driver 300 that provides a gate signal and an emission driver 500 that provides an emission control signal.

[0204] The first connection line CJL1 may be connected to the second driver GDV in the non-display area NDA and may extend in the first direction DR1. The first connection line CJL1 may receive a driving signal from the second driver GDV. The first connection line CJL1 may include a first gate connection line GJL1 and a first emission connection line EJL1.

[0205] The second connection line CJL2 may be connected to the first connection line CJL1 and may extend in the second direction DR2. The second connection line CJL2 may be connected to the first connection line CJL1 in the separation space SPS between the pixel circuit groups GPXC at the second contact point JP2. The second connection line CJL2 may receive a driving signal via the first connection line CJL1. The second connection line CJL2 may include a second gate connection line GJL2 and a second emission connection line EJL2.

[0206] In an embodiment, the second contact point JP2 may be located in the first separation space SPS1 between the pixel circuit groups GPXC arranged along the first direction DR1. In this case, the second connection line CJL2 may be spaced apart from the pixel circuit PXC in a plan view.

[0207] The signal line DSL may be connected to the second connection line CJL2. In an embodiment, the signal line DSL may include a portion extending in the second direction DR2 and a portion extending in the first direction DR1. For example, the signal line DSL may extend in the second direction DR2 at the display area DA, and may extend in the first direction DR1 at the non-display area NDA. Specifically, the signal line DSL may be connected to the second connection line CJL2 at a first contact point JP1 in the peripheral area PA on the left and / or right side of the display area DA. The signal line DSL may receive a driving signal from the second connection line CJL2. The signal line DSL may transmit the driving signal to the pixel circuit PXC located in the same row. The signal line DSL may include a gate signal line GL and an emission signal line EML.

[0208] like Fig.18 As shown, the constant voltage line CVL may include a first constant voltage line CVL1 and a second constant voltage line CVL2. The first constant voltage line CVL1 may be connected to the second driver GDV and may extend in the first direction DR1. The first constant voltage line CVL1 may receive a constant voltage from the second driver GDV. The constant voltage may include Figure 6 The driving voltage ELVDD, the common voltage ELVSS, the gate initialization voltage VINT and the anode initialization voltage VAINT are shown.

[0209] The second constant voltage line CVL2 may be connected to the first constant voltage line CVL1 and may extend in the second direction DR2. The second constant voltage line CVL2 may be connected to the first constant voltage line CVL1 in the display area DA at the third contact point JP3. The second constant voltage line CVL2 may receive a constant voltage via the first constant voltage line CVL1. Therefore, the second constant voltage line CVL2 may transmit a constant voltage to the pixel circuits PXC located in the same row.

[0210] In an embodiment, the third contact point JP3 may overlap each of the pixel circuits PXC in a plan view. In an alternative embodiment, the third contact point JP3 may be located in a separation space SPS between the pixel circuit groups GPXC.

[0211] Fig.19 is a plan view showing a display device according to a seventh embodiment of the present disclosure.

[0212] refer to Fig.19 The display device DD7 according to the seventh embodiment of the present disclosure may include a substrate SUB, a first driver D-IC, a second driver GDV, a light emitting element LD, a pixel circuit group GPXC, a first connection line CJL1, a second connection line CJL2, and a signal line DSL.

[0213] Except for the position where the first connection line CJL1 and the second connection line CJL2 are connected, Fig.19 The display device DD7 shown can be used with reference Fig.17 and Fig.18 The display device DD6 described in the present invention is substantially the same as that described in the present invention. Fig.17 and Fig.18 The description of the display device DD6 overlaps the description.

[0214] The first connection line CJL1 may be connected to the second driver GDV and may extend in the first direction DR1. The first connection line CJL1 may receive a driving signal from the second driver GDV. The first connection line CJL1 may include a first gate connection line GJL1 and a first emission connection line EJL1.

[0215] The second connection line CJL2 may be connected to the first connection line CJL1 and may extend in the second direction DR2. The second connection line CJL2 may be connected to the first connection line CJL1 in the separation space SPS between the pixel circuit groups GPXC at the second contact point JP2'. The second connection line CJL2 may receive a driving signal via the first connection line CJL1. The second connection line CJL2 may include a second gate connection line GJL2 and a second emission connection line EJL2.

[0216] In an embodiment, the second contact point JP2' may be located in the second separation space SPS2 between the pixel circuit groups GPXC arranged along the second direction DR2. In this case, the first connection line CJL1 may be spaced apart from the pixel circuit PXC in a plan view.

[0217] Fig. 20 is a plan view showing a display device according to an eighth embodiment of the present disclosure.

[0218] refer to Fig. 20The display device DD8 according to the eighth embodiment of the present disclosure may include a substrate SUB, a first driver D-IC, a second driver GDV, a light emitting element LD, a pixel circuit group GPXC, a first connection line CJL1, a second connection line CJL2, and a signal line DSL.

[0219] Except for the position where the first connection line CJL1 and the second connection line CJL2 are connected, Fig. 20 The display device DD8 shown can be used with reference Fig.17 and Fig.18 The display device DD6 described in the present invention is substantially the same as that described in the present invention. Fig.17 and Fig.18 A description of the overlap is given of the description of the display device DD6.

[0220] The first connection line CJL1 may be connected to the second driver GDV and may extend in the first direction DR1. The first connection line CJL1 may receive a driving signal from the second driver GDV. The first connection line CJL1 may include a first gate connection line GJL1 and a first emission connection line EJL1.

[0221] The second connection line CJL2 may be connected to the first connection line CJL1 and may extend in the second direction DR2. The second connection line CJL2 may be connected to the first connection line CJL1 in the separation space SPS between the pixel circuit groups GPXC at the second contact point JP2". The second connection line CJL2 may receive a driving signal via the first connection line CJL1. The second connection line CJL2 may include a second gate connection line GJL2 and a second emission connection line EJL2.

[0222] In an embodiment, the second contact point JP2" may be located in the first separation space SPS1 and the second separation space SPS2. In this case, the second connection line CJL2 forming the second contact point JP2" in the first separation space SPS1 may be spaced apart from the pixel circuit PXC in a plan view. In addition, the first connection line CJL1 forming the second contact point JP2" in the second separation space SPS2 may be spaced apart from the pixel circuit PXC in a plan view.

[0223] The present disclosure may be applied to various display devices. For example, the present disclosure may be applied to various display devices, such as display devices for vehicles, ships, and airplanes, portable communication devices, display devices for display or information transmission, medical display devices, and the like.

[0224] The above is an example of an embodiment of the present disclosure and should not be construed as limiting thereof. Although several embodiments have been described with reference to the accompanying drawings, it will be readily appreciated by those skilled in the art that many changes and modifications may be made therein without departing from the spirit and scope of the present disclosure as defined in the appended claims.

Claims

1. A display device, comprising: A substrate, comprising a display area and a non-display area surrounding the display area; A pixel circuit group, arranged in a matrix form along a first direction and a second direction intersecting the first direction in the display area on the substrate, each of the pixel circuit groups comprising a pixel circuit; a first driver disposed on the substrate in the non-display area on one side of the display area and providing a data voltage to the pixel circuit; a second driver disposed on the substrate in the non-display area on the other side of the display area opposite to the one side and providing a driving signal to the pixel circuit; a first connection line connected to the second driver and extending in the first direction; a second connection line connected to the first connection line in a separation space between adjacent pixel circuit groups and extending in the second direction; as well as A signal line connected to the second connection line and transmitting the driving signal supplied from the second driver to the pixel circuit.

2. The display device according to claim 1, wherein: The second connection line and the signal line are connected at a first contact point in the non-display area, and Wherein, the first connection line and the second connection line are connected at a second contact point in the display area.

3. The display device according to claim 2, wherein: the second driver is positioned to be spaced apart from the display area in the first direction, and Wherein, the first contact point is positioned in the non-display area to be spaced apart from the display area in the second direction.

4. The display device according to claim 2, wherein: The second contact point is located in a first separation space between the adjacent pixel circuit groups arranged along the first direction.

5. The display device according to claim 4, further comprising: a light emitting element located in the separation space between the adjacent pixel circuit groups, Wherein, at least a portion of the second connecting line overlaps with the light emitting element in a plan view.

6. The display device according to claim 2, wherein: The second contact point is located in a second separation space between the adjacent pixel circuit groups arranged along the second direction.

7. The display device according to claim 1, wherein: The second driver includes a gate driver, and the gate driver provides a gate signal to the pixel circuit. Wherein, the first connection line comprises a first gate connection line connected to the gate driver, Wherein, the second connection line includes a second gate connection line connected to the first gate connection line, and The signal line includes a gate signal line connected to the second gate connection line and transmitting the gate signal provided from the gate driver.

8. The display device according to claim 1, wherein: The second driver includes an emission driver, the emission driver providing an emission control signal to the pixel circuit, Wherein, the first connection line comprises a first emission connection line connected to the emission driver, The second connection line includes a second transmission connection line connected to the first transmission connection line, and The signal line includes a transmission signal line, which is connected to the second transmission connection line and transmits the transmission control signal provided by the transmission driver.

9. The display device according to claim 1, further comprising: a constant voltage line, providing a constant voltage to the pixel circuit, wherein the constant voltage line includes a first constant voltage line connected to the second driver and extending in the first direction and a second constant voltage line connected to the first constant voltage line and extending in the second direction, and Wherein, the first constant voltage line and the second constant voltage line are connected at a third contact point in the display area.

10. The display device according to claim 9, wherein: The third contact point overlaps each of the pixel circuits in a plan view.

11. The display device according to claim 9, wherein: The third contact point is located in the separation space between the adjacent pixel circuit groups.

12. The display device according to claim 1, wherein: The non-display area includes: a first driver region, located on the one side of the display region and provided with the first driver; a second driver region located on the other side of the display region and provided with the second driver; and bending regions, respectively located between the display region and the first driver region and between the display region and the second driver region in a plan view, and The substrate can be bent in the bending region about a reference axis parallel to the second direction.

13. The display device according to claim 1, wherein: The second connection line includes at least one selected from the group consisting of aluminum, copper, silver, molybdenum, and titanium.

14. A display device comprising: A substrate, comprising a display area and a non-display area surrounding the display area; A pixel circuit group, arranged in a matrix form along a first direction and a second direction intersecting the first direction in the display area on the substrate, each of the pixel circuit groups comprising a pixel circuit; a first driver disposed on the substrate in the non-display area on one side of the display area and providing a data voltage to the pixel circuit; a second driver disposed on the substrate in the non-display area on the one side of the display area and providing a driving signal to the pixel circuit; a first connection line connected to the second driver and extending in the first direction; a second connection line connected to the first connection line in a separation space between adjacent pixel circuit groups and extending in the second direction; as well as A signal line connected to the second connection line and transmitting the driving signal supplied from the second driver to the pixel circuit.

15. The display device according to claim 14, wherein: The second connection line and the signal line are connected at a first contact point in the non-display area, wherein the second driver is positioned to be spaced apart from the display area in the first direction, and Wherein, the first contact point is positioned to be spaced apart from the display area in the second direction.

16. The display device according to claim 14, wherein: The first connection line and the second connection line are connected at a second contact point in the display area, and The second contact point is located in a first separation space between the adjacent pixel circuit groups arranged along the first direction.

17. The display device according to claim 14, wherein: The first connection line and the second connection line are connected at a second contact point in the display area, and The second contact point is located in a second separation space between the adjacent pixel circuit groups arranged along the second direction.

18. The display device according to claim 14, wherein: The second driver includes a gate driver, and the gate driver provides a gate signal to the pixel circuit. Wherein, the first connection line comprises a first gate connection line connected to the gate driver, Wherein, the second connection line includes a second gate connection line connected to the first gate connection line, and The signal line includes a gate signal line connected to the second gate connection line and transmitting the gate signal provided from the gate driver.

19. The display device according to claim 14, wherein: The second driver includes an emission driver, the emission driver providing an emission control signal to the pixel circuit, Wherein, the first connection line comprises a first emission connection line connected to the emission driver, The second connection line includes a second transmission connection line connected to the first transmission connection line, and The signal line includes a transmission signal line connected to the second transmission connection line and transmitting the transmission control signal provided from the transmission driver.

20. The display device according to claim 14, wherein: The non-display area includes: a driver area located on the one side of the display area and provided with each of the first driver and the second driver; and a bending area located between the display area and the driver area in a plan view, The substrate can be bent in the bending region about a reference axis parallel to the second direction.

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