Gate drive circuit and display panel

Abstract

The invention discloses a gate driving circuit and a display panel, the gate driving circuit comprises a plurality of gate driving units which are arranged in a cascade mode, and each gate driving unit comprises a pull-up circuit, a pull-down circuit and an output circuit; the pull-up circuit comprises a first active switch and a first capacitor, the output end of the first active switch is connected to the output circuit, the input end of the first active switch is connected to a pull-up signal line, and the control end of the first active switch is connected to one end of the first capacitor; the pull-up signal line is connected to the other end of the first capacitor; when a pull-up signal exists on the pull-up signal line, the first capacitor is charged, the first active switch is switched on, and when the pull-up signal does not exist on the pull-up signal line, the first active switch is switched off. The first capacitor is arranged, the first active switch is controlled to be turned on through charging of the first capacitor, and the stability of the gate drive circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Art

[0002] GOA (Gate Driver on Array) technology is the mainstream technology for display panels at present, which is conducive to further reducing the border of the display panel to achieve a narrow border or no border. Among them, the gate drive circuit is mainly implemented on the array substrate by thin film deposition, and the shift register circuit is implemented on the array substrate to realize the progressive scanning drive function of the display panel. In traditional active matrix displays, the row scanning signal is usually realized by an external integrated circuit. After adopting the panel GOA technology, the row scanning drive circuit can be manufactured using the same process as the thin film transistor (TFT) on the basis of only providing a few control signals from the external circuit, thereby realizing the progressive scanning drive function.

[0003] However, the pull-up circuit in the gate driving circuit is prone to burnout due to the presence of vias at the connection points, which results in high impedance. Summary of the invention

[0004] The purpose of the present application is to provide a gate drive circuit and a display panel. By setting a first capacitor and utilizing the charging of the first capacitor to control the opening of a first active switch, the problem of burning the via connecting the control end and the input end of the first active switch when the pull-up signal is too large, causing the gate drive unit to fail to work, is avoided, thereby improving the stability of the gate drive circuit.

[0005] The present application discloses a gate driving circuit, which is arranged on a base substrate of a display panel, wherein the gate driving circuit comprises a plurality of gate driving units arranged in cascade, wherein the gate driving unit comprises a pull-up circuit, a pull-down circuit and an output circuit; the pull-up circuit comprises a first active switch and a first capacitor, wherein the output end of the first active switch is connected to the output circuit, the input end of the first active switch is connected to a pull-up signal line, the control end of the first active switch is connected to one end of the first capacitor, and the pull-up signal line is connected to the other end of the first capacitor; when there is a pull-up signal on the pull-up signal line, the first capacitor is charged and the first active switch is turned on, and when there is no pull-up signal on the pull-up signal line, the first active switch is turned off.

[0006] Optionally, the pull-up circuit also includes a second active switch, the output end of the second active switch is connected to the output end of the first active switch, and when the second active switch is turned on, it is used to pull down the potential of the output end of the first active switch to the potential when the first active switch is turned off; the control end of the second active switch is connected to the pull-down circuit, and when the gate driving unit of the next level outputs, the pull-down circuit of the gate driving unit of the next level controls the second active switch of the current level to turn on.

[0007] Optionally, the display panel includes a base substrate, a first metal layer and a second metal layer, the first metal layer is arranged on the base substrate, the second metal layer is arranged on the first metal layer, and the second metal layer is insulated from the first metal layer; the input end and the output end of the first active switch are arranged in the second metal layer, and the control end of the first active switch is arranged in the first metal layer; the first capacitor includes a first electrode and a second electrode, the first electrode is arranged in the first metal layer, and the second electrode is arranged in the second metal layer; the first electrode is connected to the control end of the first active switch, and the second electrode is connected to the input end of the first active switch and the pull-up signal line.

[0008] Optionally, in the first-level gate driving unit, the pull-up signal line includes a frame start signal line, and the pull-up circuit also includes a connecting line, the frame start signal line is arranged in the first metal layer, and the connecting line is arranged in the second metal layer, the frame start signal line is connected to the connecting line through a via, and the input end of the first active switch is connected to the connecting line; the connecting line is also connected to the second electrode; wherein the pull-up signal is a frame start signal.

[0009] Optionally, in the nth level gate driving unit, the pull-up signal line includes a level transmission signal line, the pull-up circuit includes a third active switch, the control end and the input end of the third active switch are respectively connected to the level transmission signal line, wherein n is a natural number greater than 1, and the first active switch is only arranged in the first level gate driving unit.

[0010] Optionally, in the first-stage gate driving unit, the pull-up circuit further includes a fourth active switch, the input end of the fourth active switch is connected to the connecting line, the control end of the fourth active switch is connected to the connecting line through a via; and the output end of the fourth active switch is connected to the output circuit.

[0011] Optionally, when the frame start signal line outputs a frame start signal, the first active switch and the fourth active switch are turned on at the same time, and the first-stage gate driving unit outputs a scan signal.

[0012] Optionally, a ground signal line is further provided between the frame start signal line and the first active switch, and the connecting line crosses the ground signal line and is connected to the frame start signal line.

[0013] Optionally, the capacitance of the first capacitor is greater than or equal to 0.1 pF.

[0014] The present application also discloses a display panel, comprising a display substrate and a gate driving circuit as described above, which is arranged on the display substrate, wherein the gate driving circuit is used to drive the display panel to display.

[0015] The present application sets a first capacitor at the input and output of the first active switch, so that one end of the first capacitor is connected to the control end of the first active switch, and the other end of the first capacitor is connected to the input end of the first active switch. When the pull-up circuit receives the pull-up signal on the pull-up signal line, the first capacitor is charged so that the voltage of the control end of the first active switch rises to a preset voltage, so that the first active switch is in a conducting state. When the gate drive unit does not output, the first active switch is controlled to be in a cut-off state after the pull-up signal is removed. By setting the first capacitor, the via at the connection between the input end and the control end of the first active switch is omitted, and the pull-up signal is prevented from burning the via at the connection between the input end and the control end of the first active switch during the process of outputting the pull-up signal to the input end and the control end of the first active switch, causing the gate drive circuit to fail to work properly. The present application sets the first capacitor and uses the first capacitor charging to control the opening of the first active switch, avoiding the problem that when the pull-up signal is too large, the via connected to the control end and the input end of the first active switch is burned, causing the gate drive unit to fail to work, and improving the stability of the gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0017] Figure 1 is a schematic diagram of a gate driving circuit of a first embodiment of the present application;

[0018] Figure 2 is a schematic diagram of the film layer structure of the gate driving unit of the first embodiment of the present application;

[0019] Figure 3 is a schematic diagram of an equivalent circuit of a gate driving unit of the first embodiment of the present application;

[0020] Figure 4 is a schematic diagram of the nth-level gate driving unit of the present application;

[0021] Figure 5 is a schematic diagram of a gate driving circuit of a second embodiment of the present application;

[0022] Figure 6 is a schematic diagram of an equivalent circuit of a gate driving unit of a second embodiment of the present application;

[0023] Figure 7 is a schematic diagram of a gate driving circuit of a third embodiment of the present application;

[0024] Figure 8 is an equivalent schematic diagram of a gate driving circuit of the third embodiment of the present application;

[0025] Fig. 9 is a schematic diagram of a display panel of the present application.

[0026] Among them, 100, gate drive circuit; 110, gate drive unit; 111, pull-up circuit; 112, pull-down circuit; 113, output circuit; 114, maintenance module; T1, first active switch; T2, second active switch; T3, third active switch; T4, fourth active switch; C1, first capacitor; 120, first metal layer; 121, first electrode; 130, second metal layer; 131, second electrode; 132, connecting line; STV, frame start signal line; VSS, ground signal line; CLK, clock signal line; 200, display panel; 210, display substrate. DETAILED DESCRIPTION

[0027] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0028] In the description of the present application, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features; "multiple" means two or more. In addition, the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. indicating orientation or positional relationships are described based on the orientation or relative positional relationships shown in the accompanying drawings, and are only for the convenience of describing the simplified description of the present application, rather than indicating that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0029] The present application is described in detail below with reference to the accompanying drawings and optional embodiments.

[0030] Figure 1 is a schematic diagram of a gate driving circuit of the first embodiment of the present application, Figure 2 is a schematic diagram of the film structure of the gate driving unit of the first embodiment of the present application, Figure 3 is a schematic diagram of an equivalent circuit of a gate driving unit of the first embodiment of the present application, see Figures 1 to 3 As shown, the present application discloses a gate drive circuit 100, which is arranged on a substrate of a display panel. The gate drive circuit 100 includes a plurality of gate drive units 110 arranged in cascade, and the gate drive unit 110 includes a pull-up circuit 111, a pull-down circuit 112 and an output circuit 113; the pull-up circuit 111 includes a first active switch T1 and a first capacitor C1, the output end of the first active switch T1 is connected to the output circuit 113, the input end of the first active switch T1 is connected to a pull-up signal line, the control end of the first active switch T1 is connected to one end of the first capacitor C1, and the pull-up signal line is connected to the other end of the first capacitor C1; when there is a pull-up signal on the pull-up signal line, the first capacitor C1 is charged, and the first active switch T1 is turned on, and when there is no pull-up signal on the pull-up signal line, the first active switch T1 is turned off.

[0031] The present application sets a first capacitor C1 at the input and output ends of the first active switch T1, so that one end of the first capacitor C1 is connected to the control end of the first active switch T1, and the other end of the first capacitor C1 is connected to the input end of the first active switch T1. When the pull-up circuit 111 receives the pull-up signal on the pull-up signal line, the first capacitor C1 is charged so that the voltage of the control end of the first active switch T1 rises to a preset voltage, so that the first active switch T1 is in a conducting state. When the gate driving unit 110 does not output, the first active switch T1 is controlled to be in a cut-off state after the pull-up signal is removed. By setting the first capacitor C1, the via at the connection between the input end and the control end of the first active switch T1 is omitted, so as to prevent the pull-up signal from burning the via at the connection between the input end and the control end of the first active switch T1 during the process of outputting to the input end and the control end of the first active switch T1, so as to cause the gate driving circuit 100 to fail to work normally. The present application sets a first capacitor C1 and uses the charging of the first capacitor C1 to control the opening of the first active switch T1, thereby avoiding the problem that when the pull-up signal is too large, the via connecting the control end and the input end of the first active switch T1 is burned, causing the gate driving unit 110 to fail to work, thereby improving the stability of the gate driving circuit 100.

[0032] Among them, the main function of the pull-up circuit 111 is to increase the potential of the Q point, the output circuit 113 mainly outputs a scan signal at the Q point potential and the control line of the clock signal line CLK, the maintenance module 114 is mainly used to maintain the normal operation of the gate drive unit 110, and the pull-down circuit mainly negatively pulls down the Q point of the gate drive unit and the output circuit output signal.

[0033] Among them, the technology of setting the gate drive circuit 100 on the base substrate of the display panel is called GDL (GateDriver Less) technology, also known as GOA (Gate on Array) technology, which is a shift register circuit on the array substrate, that is, formed by using a film layer process on the base substrate to realize the progressive scanning driving function of the display panel. In traditional active matrix displays, the row scanning signal is usually realized by an external integrated circuit. After adopting the panel GDL technology, the row scanning driving circuit can be manufactured using the same process as the thin film transistor (TFT) on the basis of only providing a few control signals from the external circuit, thereby realizing the progressive scanning driving function.

[0034] The first active switch T1 is also called a thin film transistor. It generally requires multiple film layers to be formed on the substrate, such as a gate, an active layer, a source, a drain, etc. Generally speaking, the control end of the first active switch T1 is the gate of the thin film transistor, the output end of the first active switch T1 is the drain of the thin film transistor, and the input end of the first active switch T1 is the source of the thin film transistor. The gate is not located in the same layer as the source and the drain. Therefore, when the pull-up signal line needs to connect the input end and the control end of the first active switch T1 at the same time, that is, when the source and the gate that are not located in the same layer are connected at the same time, it is necessary to connect through a via. At the via position, the source and the gate of different layers are generally connected through electrodes. The number of vias corresponds to the impedance here. When the number of vias is large, the impedance here is small. However, due to limited wiring space, generally speaking, the number of vias is 2 to 4, and it also has a large impedance. Therefore, when the pull-up signal is transmitted to the gate or source of the first active switch T1 through the via hole, the via hole may be burned due to excessive impedance and heat generation, thereby causing the gate drive circuit 100 to fail to work properly. In addition, since the gate drive circuit 100 is output step by step, when the above problem occurs at a certain level, the entire gate drive circuit 100 will fail to output.

[0035] Specifically, the display panel includes a base substrate, a first metal layer 120 and a second metal layer 130, wherein the first metal layer 120 is disposed on the base substrate, and the second metal layer 130 is disposed on the first metal layer 120, and the first metal layer 120 and the second metal layer 130 are insulated from each other and are generally separated by an insulating material. The corresponding thin film transistor disposed on the base substrate of the present application uses the first metal layer 120 to form the gate of the thin film transistor, and uses the second metal layer 130 to form the source and drain of the thin film transistor, wherein the gate of the thin film transistor is generally the control end of the active switch, the source is generally the input end of the active switch, and the drain is generally the output end of the active switch.

[0036] In the gate drive circuit 100, in the pull-up circuit 111 of the gate drive unit 110, when the start signal is transmitted to the first active switch T1 of the pull-up circuit 111, the start signal is generally transmitted to the control end and the input end of the first active switch T1 respectively by setting a via, so as to drive the first active switch T1 to output the signal to the Q point, and the Q point controls the output circuit 113 to output the scan signal to the scan line. When the voltage of the start signal is large and the hole of the via is limited, the impedance at the position of the via is large, resulting in the problem of burning the via. Among them, the Q point is a key node in the gate drive unit 110, the pull-up circuit 111 is used to increase the potential of the Q point, and the pull-down circuit 112 is used to lower the voltage of the Q point. That is, under the control of the pull-up circuit 111 and the output circuit 113, the output of the scan signal is realized. Under the action of the pull-down circuit 112, the output circuit 113 no longer outputs the scan signal. Generally speaking, a clock signal line CLK is also provided in the output circuit 113. Under the control of the Q point potential and the clock signal line CLK, the plurality of scanning lines output scanning signals line by line.

[0037] In this embodiment, the first active switch T1 whose control terminal is directly connected to the input terminal is not provided in the pull-up circuit 111 of the gate driving unit 110, but the first capacitor C1 is used to control the on and off of the first active switch T1. The control terminal and the input terminal of the first active switch T1 are respectively connected to the two electrodes of the first capacitor C1. When the capacitor is charged, since the capacitor will keep its potential difference unchanged, the control terminal of the first active switch T1 will also change to the on voltage potential instantaneously, so that the first active switch T1 remains in the on state. Among them, the on voltage potential of the first active switch T1 is the threshold voltage of the first active switch T1. When the voltage of the control terminal of the first active switch T1 is greater than or equal to the threshold voltage, the first active switch T1 is turned on.

[0038] Specifically, the input end and the output end of the first active switch T1 are arranged in the second metal layer 130, and the control end of the first active switch T1 is arranged in the first metal layer 120; the first capacitor C1 includes a first electrode 121 and a second electrode 131, the first electrode 121 is arranged in the first metal layer 120, and the second electrode 131 is arranged in the second metal layer 130; the first electrode 121 is connected to the control end of the first active switch T1, and the second electrode 131 is connected to the input end of the first active switch T1 and the pull-up signal line. In this embodiment, the input end of the first active switch T1 is connected to a side electrode of the first capacitor C1, and the electrode is also connected to the pull-up signal line. When there is a pull-up signal on the pull-up signal line, the pull-up signal controls the control end of the first active switch T1 to change to a conduction voltage potential through the first capacitor C1, so that the pull-up signal is output from the input end of the first active switch T1 to the Q point.

[0039] In one embodiment, taking the first-level gate driving unit 110 as an example, in the first-level gate driving unit 110, the pull-up signal line includes a frame start signal line STV, the pull-up circuit 111 also includes a connecting line 132, the frame start signal line STV is arranged in the first metal layer 120, the connecting line 132 is arranged in the second metal layer 130, the frame start signal line STV is connected to the connecting line 132 through a via, the input end of the first active switch T1 is connected to the connecting line 132; the connecting line 132 is also connected to the second electrode 131; wherein the pull-up signal is a frame start signal.

[0040] Generally, in the gate driving circuit 100, the pull-up circuit 111 of the first several stages, such as the first stage and the second stage, of the gate driving unit 110 needs to be controlled by the frame start signal line STV, while the gate driving units 110 of other stages are outputted by the previous stage or the first two stages of the gate driving unit 110. Generally speaking, the level transmission signal between the two stages of the gate driving unit 110 is generally not connected through a via hole, so there is no need to set the first capacitor C1. Therefore, the first capacitor C1 of the present embodiment is only set in the gate driving unit 110 of the first stage, the second stage, etc., which needs to be controlled by the frame start signal line STV. Of course, the gate driving units 110 of other stages can be designed according to actual conditions.

[0041] Specifically, a ground signal line VSSVSS is also provided between the frame start signal line STV and the first active switch T1, and the connection line 132 crosses the ground signal line VSS and is connected to the frame start signal line STV. Of course, the clock signal line CLK mentioned above is also included, which needs to be connected to the multi-stage gate driving unit 110. Therefore, the clock signal line CLK is generally provided on the side of the frame start signal line STV closer to the first active switch T1, so as to reduce the parasitic capacitance and impedance caused by the cross-line.

[0042] Figure 4 is a schematic diagram of the nth level gate driving unit of the present application, see Figure 4 As shown, specifically, in the nth stage gate driving unit 110, the pull-up signal line includes a stage transmission signal line, the pull-up circuit 111 includes a third active switch T3, the control end and the input end of the third active switch T3 are respectively connected to the stage transmission signal line, wherein n is a natural number greater than 1, and the first active switch T1 is only arranged in the first stage gate driving unit 110.

[0043] In this embodiment, the main consideration is that the level transmission signal on the level transmission signal line is different from the above-mentioned frame start signal, and there is often no problem of burning the frame start signal. Therefore, in other levels of gate driving units 110, the above-mentioned first capacitor C1 may not be set, thereby reducing costs. Of course, the gate driving units 110 of other levels can also be protected, and the first capacitor C1 can also be synchronously set in the pull-up circuit 111 of each level of the gate driving circuit 100.

[0044] In one embodiment, the pull-up circuit 111 further includes a second active switch T2, the output end of the second active switch T2 is connected to the output end of the first active switch T1, and when the second active switch T2 is turned on, it is used to pull down the potential of the output end of the first active switch T1 to the potential when the first active switch T1 is turned off; the control end of the second active switch T2 is connected to the pull-down circuit 112, and when the gate driving unit 110 of the next stage outputs, the pull-down voltage Qb output by the pull-down circuit 112 of the gate driving unit 110 of the next stage controls the second active switch T2 of the current stage to be turned on.

[0045] In this embodiment, by setting the second active switch T2, when the current row scan line is scanned off, the second active switch T2 is controlled to release the potential at point Q. Moreover, at this time, the frame start signal on the frame start signal line STV is also at a low level. At this time, through the capacitive coupling effect of the first capacitor C1, the voltage at the control end of the first active switch T1 is pulled down to be lower than the above-mentioned turn-on voltage, so that the first active switch T1 is in a cut-off state. In this way, the pull-up circuit 111 of the gate driving unit 110 is controlled, and the frame start signal is no longer output to point Q.

[0046] It is worth mentioning that in actual settings, the control end of the second active switch T2 of the current gate driving unit 110 can also be connected to the pull-down circuit 112 of the next two levels of gate driving units 110, and does not need to be limited to the next level of gate driving unit 110.

[0047] Of course, on the basis of the above-mentioned second active switch T2, another second active switch T2 may be additionally added. The input end and the control end of the second active switch T2 are connected in the same manner as the above-mentioned second active switch T2, but the output end of the second active switch T2 is connected to the control end of the first active switch T1. When the second active switch T2 is turned on, the voltage of the control end of the first active switch T1 is released, thereby achieving a better effect of cutting off the first active switch T1.

[0048] Figure 5 is a schematic diagram of a gate driving circuit of a second embodiment of the present application, Figure 6is a schematic diagram of an equivalent circuit of a gate driving unit of the second embodiment of the present application, see Figures 5 and 6 As shown, in this embodiment, the present application also discloses another gate drive circuit 100, the gate drive circuit 100 is arranged on the substrate of the display panel, the gate drive circuit 100 includes a plurality of gate drive units 110 arranged in cascade, the gate drive unit 110 includes a pull-up circuit 111, a pull-down circuit 112 and an output circuit 113; the pull-up circuit 111 includes a first capacitor C1, and the pull-up circuit 111 is not provided with a first active switch T1, but directly increases the potential of the Q point through the coupling of the first capacitor C1. When there is a pull-up signal on the pull-up signal line, the first capacitor C1 is charged and a frame start signal is output to the Q point.

[0049] In this embodiment, the frame start signal is directly coupled to the Q point by a capacitor. Relatively speaking, the circuit design is simpler, but there is a problem of shutdown delay. For example, in the above embodiment, a second active switch T2 can be added. When the current gate drive unit 110 needs to stop output, the second active switch T2 is used to release the electricity in the first capacitor C1. In this embodiment, the capacity of the first capacitor C1 needs to be relatively large, at least greater than or equal to 10pF. In the first embodiment, the capacitance of the first capacitor C1 is greater than or equal to 0.1pF.

[0050] Figure 7 is a schematic diagram of a gate driving circuit of a third embodiment of the present application, Figure 8 is an equivalent schematic diagram of the gate drive circuit of the third embodiment of the present application, see Figures 7 and 8As shown, in this embodiment, the present application further discloses a gate driving circuit 100, the gate driving circuit 100 is arranged on the substrate of the display panel, the gate driving circuit 100 includes a plurality of gate driving units 110 arranged in cascade, the gate driving unit 110 includes a pull-up circuit 111, a pull-down circuit 112 and an output circuit 113; the pull-up circuit 111 includes a first active switch T1 and a first capacitor C1, the output end of the first active switch T1 is connected to the output circuit 113, the input end of the first active switch T1 is connected to the pull-up signal line, and the control end of the first active switch T1 is connected to the first capacitor C1 one end of the pull-up signal line is connected to the other end of the first capacitor C1; in the first-stage gate driving unit 110, the pull-up signal line includes a frame start signal line STV, the pull-up circuit 111 also includes a connecting line 132, the frame start signal line STV is arranged in the first metal layer 120, the connecting line 132 is arranged in the second metal layer 130, the frame start signal line STV is connected to the connecting line 132 through a via, the input end of the first active switch T1 is connected to the connecting line 132; the connecting line 132 is also connected to the second electrode 131; wherein the pull-up signal is a frame start signal.

[0051] In the first-stage gate driving unit 110, the pull-up circuit 111 further includes a fourth active switch T4, the input end of the fourth active switch T4 is connected to the connection line 132, the control end of the fourth active switch T4 is connected to the connection line 132 through a via, and the output end of the fourth active switch T4 is connected to the output circuit 113. When there is a pull-up signal on the pull-up signal line, the first capacitor C1 is charged and the first active switch T1 is turned on, and when there is no pull-up signal on the pull-up signal line, the first active switch T1 is turned off.

[0052] In this embodiment, a fourth active switch T4 is added on the basis of the first embodiment, and the fourth active switch T4 connects the control end of the fourth active switch T4 to the input end through a via, and is connected to the connecting line 132, and the connecting line 132 crosses the ground signal line VSSVSS and the clock signal line CLK and is connected to the frame start signal line STV. In this solution, by setting the first active switch T1 and the fourth active switch T4, the two work together. When the frame start signal line STV outputs a frame start signal, the first active switch T1 and the fourth active switch T4 are turned on at the same time, and the first-level gate drive unit 110 outputs a scan signal. Moreover, it is important that when the fourth active switch T4 cannot work normally due to the burning of the via, the first active switch T1 can still start normally through the action of the first capacitor C1 to improve the working stability of the gate drive circuit 100. It is worth mentioning that the other solutions in the first embodiment are also applicable to the third embodiment, and will not be repeated here.

[0053] Fig. 9 is a schematic diagram of the display panel of the present application, see Fig. 9 As shown, the present application further discloses a display panel, wherein the display panel 200 includes a display substrate 210 and a gate driving circuit 100 disposed on the display substrate, wherein the gate driving circuit 100 is used to drive the display panel to display.

[0054] The present application sets a first capacitor C1 at the input and output ends of the first active switch T1, so that one end of the first capacitor C1 is connected to the control end of the first active switch T1, and the other end of the first capacitor C1 is connected to the input end of the first active switch T1. When the pull-up circuit 111 receives the pull-up signal on the pull-up signal line, the first capacitor C1 is charged so that the voltage of the control end of the first active switch T1 rises to a preset voltage, so that the first active switch T1 is in a conducting state. When the gate driving unit 110 does not output, the first active switch T1 is controlled to be in a cut-off state after the pull-up signal is removed. By setting the first capacitor C1, the via at the connection between the input end and the control end of the first active switch T1 is omitted, so as to prevent the pull-up signal from burning the via at the connection between the input end and the control end of the first active switch T1 during the process of outputting to the input end and the control end of the first active switch T1, so as to cause the gate driving circuit 100 to fail to work normally. The present application sets a first capacitor C1 and uses the charging of the first capacitor C1 to control the opening of the first active switch T1, thereby avoiding the problem that when the pull-up signal is too large, the via connecting the control end and the input end of the first active switch T1 is burned, causing the gate driving unit 110 to fail to work, thereby improving the stability of the gate driving circuit 100, thereby improving the life and stability of the display panel.

[0055] It should be noted that the inventive concept of the present application can form a large number of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the embodiments or technical features described above can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effects will be enhanced.

[0056] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. A gate driving circuit, arranged on a base substrate of a display panel, the gate driving circuit comprising a plurality of gate driving units arranged in cascade, characterized in that: The gate driving unit includes a pull-up circuit, a pull-down circuit and an output circuit; The pull-up circuit comprises a first active switch and a first capacitor, wherein the output end of the first active switch is connected to the output circuit, the input end of the first active switch is connected to a pull-up signal line, the control end of the first active switch is connected to one end of the first capacitor, and the pull-up signal line is connected to the other end of the first capacitor; When there is a pull-up signal on the pull-up signal line, the first capacitor is charged and the first active switch is turned on. When there is no pull-up signal on the pull-up signal line, the first active switch is turned off.

2. The gate driving circuit according to claim 1, characterized in that: The pull-up circuit further includes a second active switch, the output end of the second active switch is connected to the output end of the first active switch, and when the second active switch is turned on, the second active switch is used to pull down the potential of the output end of the first active switch to the potential when the first active switch is turned off; The control end of the second active switch is connected to the pull-down circuit. When the gate driving unit of the next stage outputs, the pull-down circuit of the gate driving unit of the next stage controls the second active switch of the current stage to turn on.

3. The gate driving circuit according to claim 1, characterized in that: The display panel comprises a base substrate, a first metal layer and a second metal layer, wherein the first metal layer is arranged on the base substrate, the second metal layer is arranged on the first metal layer, and the second metal layer is insulated from the first metal layer; The input terminal and the output terminal of the first active switch are arranged in the second metal layer, and the control terminal of the first active switch is arranged in the first metal layer; The first capacitor includes a first electrode and a second electrode, the first electrode is arranged in the first metal layer, and the second electrode is arranged in the second metal layer; The first electrode is connected to a control end of the first active switch, and the second electrode is connected to an input end of the first active switch and the pull-up signal line.

4. The gate driving circuit according to claim 3, characterized in that: In the first-stage gate driving unit, the pull-up signal line includes a frame start signal line, the pull-up circuit also includes a connecting line, the frame start signal line is arranged in the first metal layer, the connecting line is arranged in the second metal layer, the frame start signal line is connected to the connecting line through a via, the input end of the first active switch is connected to the connecting line; the connecting line is also connected to the second electrode; Wherein, the pull-up signal is a frame start signal.

5. The gate driving circuit according to claim 3, characterized in that: In the nth stage of the gate driving unit, the pull-up signal line includes a stage transmission signal line, the pull-up circuit includes a third active switch, and the control end and the input end of the third active switch are respectively connected to the stage transmission signal line, Wherein, n is a natural number greater than 1, and the first active switch is only arranged in the first-stage gate driving unit.

6. The gate driving circuit according to claim 4, characterized in that: In the first-stage gate driving unit, the pull-up circuit further includes a fourth active switch, the input end of the fourth active switch is connected to the connecting line, the control end of the fourth active switch is connected to the connecting line through a via; and the output end of the fourth active switch is connected to the output circuit.

7. The gate driving circuit according to claim 6, characterized in that: When the frame start signal line outputs a frame start signal, the first active switch and the fourth active switch are turned on at the same time, and the first-stage gate driving unit outputs a scan signal.

8. The gate driving circuit according to claim 4, characterized in that: A ground signal line is further provided between the frame start signal line and the first active switch, and the connection line crosses over the ground signal line and is connected to the frame start signal line.

9. The gate driving circuit according to claim 1, characterized in that: The capacitance of the first capacitor is greater than or equal to 0.1 pF.

10. A display panel, characterized in that: It comprises a display substrate and a gate driving circuit as described in any one of claims 1 to 9 arranged on the display substrate, wherein the gate driving circuit is used to drive the display panel to display.

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