Display driver, display driving method, and display device

Abstract

The invention provides a display driver, a display driving method and a display device, the display driver is used for the display device, and the display driver comprises a storage unit, a receiving unit, a processing unit and a data voltage adjusting unit. The storage unit is configured to store a first charging duration control signal; the receiving unit is configured to receive a second charging duration control signal and image data; the processing unit is configured to determine a first charging duration according to the first charging duration control signal, determine a second charging duration according to the second charging duration control signal, and determine a first data voltage according to the image data; the data voltage adjusting unit is configured to determine a second data voltage according to the first charging duration, the second charging duration and the first data voltage, and the product of the first data voltage and the first charging duration is equal to the product of the second data voltage and the second charging duration. The brightness of the display panel can be effectively adjusted.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display driver, a display driving method and a display device. Background Art

[0002] With the development of display technology, the host side (controller) may need to suddenly adjust the charging time of the sub-pixels of the display panel. If there is a difference between the charging time setting of the sub-pixels within a frame driving period that the host side needs to set and the charging time setting of the sub-pixels originally burned and stored in the display driver, it will cause abnormal brightness of the display panel or require readjustment of the gamma value. Summary of the invention

[0003] In view of the shortcomings of the related art, the present application proposes a ... to solve the problem of ... in the related art.

[0004] An embodiment of the present application provides a display driver for a display device, wherein the display device further includes a controller and a display panel, wherein the display panel includes sub-pixels; the display driver includes:

[0005] A storage unit configured to store a first charging duration control signal of a sub-pixel within a frame of picture driving period;

[0006] A receiving unit configured to receive a second charging duration control signal and image data of a sub-pixel within a frame of picture driving period sent by the controller;

[0007] a processing unit configured to determine a first charging duration according to the first charging duration control signal, determine a second charging duration according to the second charging duration control signal, and determine a first data voltage according to the image data;

[0008] The data voltage adjustment unit is configured to determine a second data voltage according to the first charging time, the second charging time and the first data voltage, so that the display driver charges the sub-pixel according to the second data voltage and the second charging time control signal, wherein the product of the first data voltage and the first charging time is equal to the product of the second data voltage and the second charging time.

[0009] In some embodiments, the data voltage adjustment unit includes:

[0010] A first digital-to-analog converter, connected to the processing unit, configured to receive the first charging duration and convert the first charging duration into a first voltage;

[0011] a second digital-to-analog converter, connected to the processing unit, configured to receive the second charging duration and convert the second charging duration into a second voltage;

[0012] a division operation circuit, electrically connected to an output terminal of the first digital-to-analog converter and an output terminal of the second digital-to-analog converter, respectively, and configured to generate a feedback signal according to the first voltage and the second voltage; the feedback signal is equal to a ratio of the first voltage to the second voltage;

[0013] A first multiplier includes a first input terminal and a second input terminal; the first input terminal is connected to the processing unit and is used to receive the first data voltage; the second input terminal is connected to the division operation circuit and is used to receive a feedback signal output by the division operation circuit; the first multiplier is configured to generate the second data voltage according to the first data voltage and the feedback signal, and the second data voltage is equal to the product of the first data voltage and the feedback signal.

[0014] In some embodiments, the division circuit comprises:

[0015] a second multiplier, comprising a third input terminal, a fourth input terminal and a first output terminal, wherein the third input terminal is used to receive the second voltage output by the second digital-to-analog converter, and the fourth input terminal is connected to the second input terminal of the first multiplier;

[0016] an operational amplifier, comprising a non-inverting input terminal, a reverse input terminal, and a second output terminal, wherein the reverse input terminal is connected to the output terminal of the first digital-to-analog converter and the first output terminal of the second multiplier, the non-inverting input terminal is connected to a ground terminal, and the second output terminal is connected to the second input terminal of the first multiplier and the fourth input terminal of the second multiplier;

[0017] A first resistor and a second resistor, wherein the first resistor is connected between the output terminal of the first digital-to-analog converter and the inverting input terminal of the operational amplifier, and the second resistor is connected between the inverting input terminal of the operational amplifier and the first output terminal of the second multiplier, wherein the resistance value of the first resistor is the same as the resistance value of the second resistor.

[0018] In some embodiments, the division operation circuit further includes a third resistor, and the third resistor is connected between the non-inverting input terminal of the operational amplifier and the ground terminal.

[0019] In some embodiments, the division circuit comprises:

[0020] a second multiplier, comprising a third input terminal, a fourth input terminal and a first output terminal, wherein the third input terminal is used to receive the second voltage output by the second digital-to-analog converter, and the fourth input terminal is connected to the second input terminal of the first multiplier;

[0021] an operational amplifier, comprising a non-inverting input terminal, a reverse input terminal, and a second output terminal, wherein the non-inverting input terminal is connected to the first output terminal of the second multiplier and a ground terminal, the reverse input terminal is connected to the output terminal of the first digital-to-analog converter, and the second output terminal is connected to the second input terminal of the first multiplier and the fourth input terminal of the second multiplier;

[0022] A first resistor and a second resistor, wherein the first resistor is connected between the non-inverting input terminal of the operational amplifier and the ground terminal, and the second resistor is connected between the non-inverting input terminal of the operational amplifier and the first output terminal of the second multiplier; wherein the resistance value of the first resistor is the same as the resistance value of the second resistor.

[0023] In some embodiments, the division circuit comprises:

[0024] a second multiplier, comprising a third input terminal, a fourth input terminal and a first output terminal, wherein the third input terminal is used to receive the second voltage output by the second digital-to-analog converter, and the fourth input terminal is connected to the second input terminal of the first multiplier;

[0025] an operational amplifier, comprising a non-inverting input terminal, a reverse input terminal, and a second output terminal, wherein the non-inverting input terminal is connected to the output terminal of the first digital-to-analog converter, the reverse input terminal is connected to the first output terminal of the second multiplier and a ground terminal, and the second output terminal is connected to the second input terminal of the first multiplier and the fourth input terminal of the second multiplier;

[0026] A first resistor and a second resistor, wherein the first resistor is connected between the inverting input terminal of the operational amplifier and the ground terminal, and the second resistor is connected between the inverting input terminal of the operational amplifier and the first output terminal of the second multiplier, wherein the resistance value of the first resistor is the same as the resistance value of the second resistor.

[0027] In some embodiments, the division operation circuit further includes a third resistor, and the third resistor is connected between the non-inverting input terminal of the operational amplifier and the output terminal of the first digital-to-analog converter.

[0028] In some embodiments, the data voltage adjustment unit further includes a first capacitor connected between the first input terminal of the first multiplier and a ground terminal.

[0029] In some embodiments, the data voltage adjustment unit further includes a second capacitor connected between an output terminal of the first multiplier and a ground terminal.

[0030] In some embodiments, the display panel includes a first transistor and a second transistor, the gate of the first transistor is connected to the first scan line, the first electrode of the first transistor is connected to the sub-pixel, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the second transistor is connected to the second scan line, and the second electrode of the second transistor receives the second data voltage;

[0031] The first charging duration control signal includes a first timing signal corresponding to the first scan line and a second timing signal corresponding to the second scan line; the second charging duration control signal includes a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; the processing unit is configured to determine the first charging duration according to the first timing signal and the second timing signal, and determine the second charging duration according to the third timing signal and the fourth timing signal.

[0032] In some embodiments, the processing unit is specifically configured to: determine the duration during which the first timing signal and the second timing signal are both high level within a row of sub-pixel scanning period as the first charging duration; and determine the duration during which the third timing signal and the fourth timing signal are both high level within a row of sub-pixel scanning period as the second charging duration.

[0033] The present application also provides a display device, comprising the display driver, controller and display panel as described above;

[0034] The controller is configured to send a second charging time duration control signal and image data to the display driver.

[0035] The present application also provides a display driving method for a display driver of a display device, wherein the display device further includes a controller and a display panel, and the display panel includes sub-pixels; the display driving method includes:

[0036] Acquire a first charging duration control signal stored in the display driver, and a second charging duration control signal and image data sent by the controller;

[0037] determining a first charging duration according to the first charging duration control signal, determining a second charging duration according to the second charging duration control signal, and determining a first data voltage according to the image data;

[0038] A second data voltage is determined according to the first charging time, the second charging time and the first data voltage, so that the display driver charges the sub-pixel according to the second data voltage and the second charging time control signal, wherein the product of the first data voltage and the first charging time is equal to the product of the second data voltage and the second charging time.

[0039] In some embodiments, the display panel includes a first transistor and a second transistor, the gate of the first transistor is connected to a first scan line, the first electrode of the first transistor is connected to the sub-pixel, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the second transistor is connected to a second scan line, and the second electrode of the second transistor receives the second data voltage; the first charging time control signal includes a first timing signal corresponding to the first scan line and a second timing signal corresponding to the second scan line; the first charging time control signal includes a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; determining the first charging time according to the first charging time control signal and determining the second charging time according to the second charging time control signal specifically includes:

[0040] The first charging time duration is determined according to the first timing signal and the second timing signal, and the second charging time duration is determined according to the third timing signal and the fourth timing signal.

[0041] In some embodiments, determining the first charging duration according to the first timing signal and the second timing signal, and determining the second charging duration according to the third timing signal and the fourth timing signal specifically includes:

[0042] The first charging duration is determined as the time duration during which the first timing signal and the second timing signal are both at a high level within a row of sub-pixel scanning periods; and the second charging duration is determined as the time duration during which the third timing signal and the fourth timing signal are both at a high level within a row of sub-pixel scanning periods.

[0043] The beneficial effects of this application include:

[0044] In the present embodiment, when there is a difference between the second charging duration control signal of the sub-pixel within a frame of picture driving period set by the controller and the first charging duration control signal of the sub-pixel originally burned and stored by the display driver, the processing unit determines the first charging duration according to the first charging duration control signal, determines the second charging duration according to the second charging duration control signal, determines the first data voltage of the sub-pixel according to the image data, and the data voltage adjustment unit can determine the second data voltage according to the second charging duration, the first charging duration and the first data voltage, and then the display driver charges the sub-pixel according to the second data voltage and the second charging duration control signal to keep the brightness of the sub-pixel unchanged, and the display abnormality problem can be avoided without adjusting the gamma value.

[0045] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0047] Figure 1 Shown is a schematic structural diagram of a display device provided by an exemplary embodiment of the present application;

[0048] Figure 2 FIG. 1 is a schematic diagram of the structure of a data voltage adjustment unit provided by an exemplary embodiment of the present application;

[0049] Figure 3 Shown is a structural schematic diagram of a division operation circuit provided by an exemplary embodiment of the present application;

[0050] Figures 4 to 10 Shown are schematic structural diagrams of several division operation circuits provided by exemplary embodiments of the present application;

[0051] Fig.11 Shown is a schematic structural diagram of a display panel provided by an exemplary embodiment of the present application;

[0052] Fig.12 (a) shows a GOA timing diagram of a display driver in a standard mode of a display panel provided by an exemplary embodiment of the present application; Fig.12 (b) is a GOA timing diagram that needs to be set by a controller provided in an exemplary embodiment of the present application;

[0053] Fig.13 The display panel provided by the exemplary embodiment of the present application is a GOA timing diagram of the display driver in the power saving mode;

[0054] Fig.14 Shown is the correspondence between timing signals provided by the exemplary embodiment of the present application.

[0055] In the figure: DSIDATA-image data; CTRL1-first charging time control signal; CTRL2-second charging time control signal; t1-first charging time; t2-second charging time; U SRC1 -First data voltage; U SRC2 - second data voltage; DAC1 - first digital-to-analog converter; DAC2 - second digital-to-analog converter; B1 - first multiplier; B2 - second multiplier; A - operational amplifier; R1 - first resistor; R2 - second resistor; R3 - third resistor; V REF -reference voltage; C1-first capacitor; C2-second capacitor; U I1 - first voltage; U I2 - Second voltage; Uo2 -feedback signal; 10-first input terminal; 20-second input terminal; 30-third input terminal; 40-fourth input terminal; 50-first output terminal; 60-same direction input terminal; 70-reverse input terminal; 80-second output terminal; GND-ground terminal; TFT1-first transistor; TFT2-first transistor. DETAILED DESCRIPTION

[0056] When the host connected to the display panel needs to adjust the charging time of the sub-pixel of the display panel suddenly, if the charging time setting of the sub-pixel in the one-frame picture driving period that the host needs to set is different from the charging time setting of the sub-pixel originally burned and stored by the display driver, it will cause abnormal brightness of the display panel or need to readjust the gamma value. For example, when the CLK (clock signal corresponding to the scan line) and MUX (multiplexer control signal) that the host needs to set are inconsistent with the signal width of the CLK (clock signal corresponding to the scan line) and MUX (multiplexer control signal) originally burned by the display driver, it will further cause the charging time of the sub-pixel that the host needs to set to be different from the charging time of the sub-pixel originally set by the display driver. Since the grayscale brightness of the display panel = gamma constant × grayscale data voltage × charging time, if the sub-pixel charging time set by the host is longer than the charging time originally burned by the display driver, it will cause the brightness of the pixel to be high, that is, the brightness of the display panel is abnormal. However, if the display driver with the corresponding charging time set is sent back to the factory for re-programming in order to meet the host's demand for adjusting the charging time, the cost is high.

[0057] The display driver, display driving method and display device provided in the present application are intended to solve or improve the above technical problems in the related art.

[0058] The display driver, display driving method and display device in the embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features in the following embodiments can complement or be combined with each other.

[0059] like Figure 1As shown, an embodiment of the present application provides a display driver for a display device, wherein the display device further includes a controller and a display panel, wherein the display panel includes sub-pixels; the display driver includes a storage unit, a receiving unit, a processing unit, and a data voltage adjustment unit. The storage unit is configured to store a first charging duration control signal CTRL1 of a sub-pixel within a frame of picture driving period, wherein the first charging duration control signal CTRL1 is a control signal burned in the display panel and the display driver before leaving the factory; the receiving unit is configured to receive a second charging duration control signal CTRL2 and image data DSIDATA of a sub-pixel within a frame of picture driving period sent by the controller; the processing unit is configured to determine a first charging duration t1 according to the first charging duration control signal CTRL1, determine a second charging duration t2 according to the second charging duration control signal CTRL2, and determine a first data voltage U according to the image data DSIDATA. SRC1 The data voltage adjustment unit is configured to adjust the first charging time t1, the second charging time t2 and the first data voltage U SRC1 , determine the second data voltage U SRC2 , so that the display driver can drive the display according to the second data voltage U SRC2 and the first charging duration control signal CTRL1 to charge the sub-pixel, wherein the first data voltage U SRC1 The product of the first charging time t1 is equal to the second data voltage U SRC2 and the product of the second charging time t2.

[0060] In this embodiment, when there is a difference between the second charging time control signal of the sub-pixel in the one-frame picture driving period set by the controller and the first charging time control signal of the sub-pixel originally burned and stored by the display driver, the processing unit determines the first charging time t1 according to the first charging time control signal, determines the second charging time t2 according to the second charging time control signal CTRL2, and determines the first data voltage of the sub-pixel according to the image data. The data voltage adjustment unit can adjust the first data voltage of the sub-pixel according to the second charging time t2, the first charging time t1 and the first data voltage U SRC1 Determine the second data voltage U SRC2 , and then the display driver charges the sub-pixel according to the second data voltage and the second charging duration control signal to keep the brightness of the sub-pixel unchanged, and the display abnormality problem can be avoided without adjusting the gamma value.

[0061] In an embodiment of the present application, the display panel includes a plurality of sub-pixels, the image data includes a first data voltage corresponding to each sub-pixel, the processing unit determines the first charging duration corresponding to each sub-pixel according to the first charging duration control signal, determines the second charging duration corresponding to each sub-pixel according to the second charging duration control signal, and the data voltage adjustment unit can determine the second data voltage corresponding to each sub-pixel. When the display panel is displaying, the brightness of each sub-pixel does not change, so that the overall brightness of the display panel does not change.

[0062] In some embodiments, the storage unit may be a ROM (Read-Only Memory) of a display driver.

[0063] In some embodiments, the receiving unit may be a MIPI (Mobile Industry Processor Interface) interface; or a router or Bluetooth, in which case the display driver and the controller perform signal transmission via a wireless connection.

[0064] In some embodiments, the display driver further includes a temporary RAM (Random Access Memory), and the first charging duration control signal CTRL1 received by the receiving unit may be stored in the temporary RAM.

[0065] In some embodiments, the processing unit may include a source driver, which may receive the image data DSIDATA input by the controller and determine the first data voltage U according to the image data DSIDATA. SRC1 .

[0066] In some embodiments, Figure 2 As shown, the data voltage adjustment unit includes a first digital-to-analog converter DAC1, a second digital-to-analog converter DAC2, a division circuit and a first multiplier B1. The first digital-to-analog converter DAC1 is connected to the processing unit and is configured to receive the first charging time t1 and convert the first charging time t1 into a first voltage U I1 The second digital-to-analog converter DAC2 is connected to the processing unit and is configured to receive the second charging duration t2 and convert the second charging duration t2 into a second voltage U I2 The division circuit is electrically connected to the output terminal of the first digital-to-analog converter DAC1 and the output terminal of the second digital-to-analog converter DAC2, and is configured to divide the first voltage U by I1 and the second voltage U I2 Generate feedback signal U o2 ; Feedback signal U o2 Equal to the first voltage U I1 With the second voltage U I2The first multiplier B1 comprises a first input terminal 10 and a second input terminal 20; the first input terminal 10 is connected to the processing unit for receiving a first data voltage U SRC1 The second input terminal 20 is connected to the division circuit for receiving the feedback signal U output by the division circuit o2 The first multiplier B1 is configured to generate a first data voltage U SRC1 And feedback signal U o2 Generate the second data voltage U SRC2 , the second data voltage U SRC2 Equal to the first data voltage U SRC1 With the feedback signal U o2 The product of .

[0067] In this embodiment, the first data voltage U is converted into SRC1 Converted into the second data voltage U SRC2 , it can be realized that, according to the first charging time control signal CTRL1 received by the receiving unit of the display driver, the second data voltage U corresponding to the first charging time control signal CTRL1 is determined. SRC2 , so that the brightness of the display panel remains normal.

[0068] In some embodiments, Figure 3 As shown, the division operation circuit includes a second multiplier B2, an operational amplifier A, a first resistor R1 and a second resistor R2. The second multiplier B2 includes a third input terminal 30, a fourth input terminal 40 and a first output terminal 50. The third input terminal 30 is used to receive the second voltage U output by the second digital-to-analog converter DAC2. I2 , the fourth input terminal 40 is connected to the second input terminal 20 of the first multiplier B1; the operational amplifier A includes a non-inverting input terminal 60, a reverse input terminal 70 and a second output terminal 80, the reverse input terminal 70 is connected to the output terminal of the first digital-to-analog converter DAC1 and the first output terminal 50 of the second multiplier B2, the non-inverting input terminal 60 is connected to the ground terminal GND, and the second output terminal 80 is connected to the second input terminal 20 of the first multiplier B1 and the fourth input terminal 40 of the second multiplier B2; the first resistor R1 is connected between the output terminal of the first digital-to-analog converter DAC1 and the reverse input terminal 70 of the operational amplifier A, and the second resistor R2 is connected between the reverse input terminal 70 of the operational amplifier A and the first output terminal 50 of the second multiplier B2, wherein the resistance value of the first resistor R1 is the same as the resistance value of the second resistor R2.

[0069] In this embodiment, since the operational amplifier A can realize negative feedback, the first current I1 flowing through the first resistor R1 and the second current I2 flowing through the second resistor R2 are the same, that is, I1=I2, then U I1 / R1=-U o1 / R2, where the first voltage UI1 is the voltage of the circuit where the first resistor R1 is located, U o1 is the voltage of the circuit where the second resistor R2 is located (ie, the voltage output by the second multiplier B2).

[0070] Under the action of the second multiplier B2, U o1 =N2U I2 U o2 , where N2 is the multiplication coefficient of the second multiplier B2, and the second voltage U I2 is the voltage output by the second digital-to-analog converter DAC2, U o2 is the feedback signal.

[0071] Combining the above two equations, we can know that U I1 / R1=-N2U I2 U o2 / R2; the product coefficient N2 of the second multiplier B2 can be further set to -1, then U I1 / R1=U I2 U o2 / R2; and since R1=R2, then U o2 =U I1 / U I2 .

[0072] And U I1 =M1*V REF *t1,U I2 =M2*V REF *t2, where M1 is the conversion coefficient of the first digital-to-analog converter DAC1, M2 is the conversion coefficient of the second digital-to-analog converter DAC2, V REF is the reference voltage. M1 can be further set to M2; then U o2 =t1 / t2.

[0073] Under the action of the first multiplier B1, U SRC2 =N1U SRC1 U o2 , where N1 is the multiplication coefficient of the first multiplier B1, U SRC2 is the second data voltage, U SRC1 is the first data voltage. N1 can be further set to 1, then U SRC2 =U SRC1 U o2 =U SRC1 t1 / t2, thus the first charging time t1, the second charging time t2 and the first data voltage U SRC1 The second data voltage U is calculated SRC2 The data voltage adjustment unit provided in this embodiment has a simple structure and fewer components, and has a lower cost than returning the device to the factory for re-programming.

[0074] In some embodiments, Figure 4 As shown, the division operation circuit further includes a third resistor R3, and the third resistor R3 is connected between the non-inverting input terminal 60 of the operational amplifier A and the ground terminal GND.

[0075] In this embodiment, the third resistor R3 is provided to provide a certain damping effect, reduce parasitic capacitance and reduce inductive noise. In addition, if there is a risk of transient voltage or electrostatic discharge (ESD), the resistor can play a role of current limiting to protect the reverse input terminal 70 of the operational amplifier A.

[0076] In some embodiments, the resistance of the third resistor R3 is less than 10 kΩ.

[0077] In some embodiments, Figure 5 As shown, the division operation circuit includes a second multiplier B2, an operational amplifier A, a first resistor R1 and a second resistor R2. The second multiplier B2 includes a third input terminal 30, a fourth input terminal 40 and a first output terminal 50. The third input terminal 30 is used to receive the second voltage U output by the second digital-to-analog converter DAC2. I2 , the fourth input terminal 40 is connected to the second input terminal 20 of the first multiplier B1; the operational amplifier A includes a non-inverting input terminal 60, a reverse input terminal 70 and a second output terminal 80, the non-inverting input terminal 60 is connected to the first output terminal 50 of the second multiplier B2 and the ground terminal GND, the reverse input terminal 70 is connected to the output terminal of the first digital-to-analog converter DAC1, and the second output terminal 80 is connected to the second input terminal 20 of the first multiplier B1 and the fourth input terminal 40 of the second multiplier B2; the first resistor R1 is connected between the non-inverting input terminal 60 of the operational amplifier A and the ground terminal GND, and the second resistor R2 is connected between the non-inverting input terminal 60 of the operational amplifier A and the first output terminal 50 of the second multiplier B2; wherein the resistance value of the first resistor R1 is the same as the resistance value of the second resistor R2.

[0078] Similar to the above embodiment, in this embodiment, since the operational amplifier A can realize negative feedback, U I1 =-U o1 , where the first voltage U I1 is the voltage received by the inverting input terminal 70 of the operational amplifier A, U o1 It is the voltage input to the non-inverting input terminal 60 of the operational amplifier A.

[0079] Under the action of the second multiplying amplifier, U o1 =N2U I2 U 02 , where N2 is the multiplication coefficient of the second multiplier B2, and the second voltage U I2 is the voltage output by the second digital-to-analog converter DAC2, U o2is the feedback signal.

[0080] Combining the above two equations, we can know that U I1 =-N2U I2 U 02 , the product coefficient N2 of the second multiplier B2 can be further set to -1, then U I1 =U I2 U o2 ; then U o2 =U I1 / U I2 .

[0081] And U I1 =M1*V REF *t1,U I2 =M2*V REF *t2, where M1 is the conversion coefficient of the first digital-to-analog converter DAC1, M2 is the conversion coefficient of the second digital-to-analog converter DAC2, V REF is the reference voltage. We can further set M1=M2; then U o2 =t1 / t2.

[0082] Under the action of the first multiplier B1, U SRC2 =N1U SRC1 U o2 , where N1 is the multiplication coefficient of the first multiplier B1, U SRC2 is the second data voltage, U SRC1 is the first data voltage. We can further set N1=1, then U SRC2 =U SRC1 U o2 =U SRC1 t1 / t2. The first charging time t1, the second charging time t2 and the first data voltage U SRC1 The second data voltage U is calculated SRC2 The value of .

[0083] In some embodiments, Figure 6 As shown, the division operation circuit includes a second multiplier B2, an operational amplifier A, a first resistor R1 and a second resistor R2. The second multiplier B2 includes a third input terminal 30, a fourth input terminal 40 and a first output terminal 50. The third input terminal 30 is used to receive the second voltage U output by the second digital-to-analog converter DAC2. I2, the fourth input terminal 40 is connected to the second input terminal 20 of the first multiplier B1; the operational amplifier A includes a non-inverting input terminal 60, a reverse input terminal 70 and a second output terminal 80, the non-inverting input terminal 60 is connected to the output terminal of the first digital-to-analog converter DAC1, the reverse input terminal 70 is connected to the first output terminal 50 of the second multiplier B2 and the ground terminal GND, and the second output terminal 80 is connected to the second input terminal 20 of the first multiplier B1 and the fourth input terminal 40 of the second multiplier B2; the first resistor R1 is connected between the reverse input terminal 70 of the operational amplifier A and the ground terminal GND, and the second resistor R2 is connected between the reverse input terminal 70 of the operational amplifier A and the first output terminal 50 of the second multiplier B2, wherein the resistance value of the first resistor R1 is the same as the resistance value of the second resistor R2.

[0084] The data voltage adjustment unit provided in this embodiment has a small self-oscillation and a high circuit stability. Similar to the above-mentioned embodiment, in this embodiment, since the operational amplifier A can realize negative feedback, U I1 =-U o1 , where U I1 is the voltage received by the non-inverting input terminal 60 of the operational amplifier A (ie, the first voltage U I1 , the voltage output by the first digital-to-analog converter DAC1), U o1 is the voltage at the inverting input terminal 70 of the operational amplifier A.

[0085] Under the action of the second multiplying amplifier, U o1 =N2U I2 U 02 , where N2 is the multiplication coefficient of the second multiplier B2, and the second voltage U I2 is the voltage output by the second digital-to-analog converter DAC2, U o2 is the feedback signal.

[0086] Combining the above two equations, we can know that U I1 =-N2U I2 U 02 , the product coefficient N2 of the second multiplier B2 can be further set to -1, then U I1 =U I2 U o2 ; then U o2 =U I1 / U I2 .

[0087] And U I1 =M1*V REF *t1,U I2 =M2*V REF *t2, where M1 is the conversion coefficient of the first digital-to-analog converter DAC1, M2 is the conversion coefficient of the second digital-to-analog converter DAC2, VREF is the reference voltage. We can further set M1=M2; then U o2 =t1 / t2.

[0088] Under the action of the first multiplier B1, U SRC2 =N1U SRC1 U o2 , where N1 is the multiplication coefficient of the first multiplier B1, U SRC2 is the second data voltage, U SRC1 is the first data voltage. We can further set N1=1, then U SRC2 =U SRC1 U o2 =U SRC1 t1 / t2. The first charging time t1, the second charging time t2 and the first data voltage U SRC1 The second data voltage U is calculated SRC2 The value of .

[0089] In some embodiments, Figure 7 As shown, the division operation circuit further includes a third resistor R3, which is connected between the non-inverting input terminal 60 of the operational amplifier A and the output terminal of the first digital-to-analog converter DAC1. The third resistor R3 can play a role in current limiting and protect the non-inverting input terminal 60.

[0090] In some embodiments, Figure 8 As shown, the data voltage adjustment unit further includes a first capacitor C1, which is connected between the first input terminal 10 of the first multiplier B1 and the ground terminal GND. The first capacitor C1 can filter the input first data voltage U SRC1 DC noise, improve signal-to-noise ratio and enhance circuit stability.

[0091] In some embodiments, Fig. 9 As shown, the data voltage adjustment unit further includes a second capacitor C2, which is connected between the output terminal of the first multiplier B1 and the ground terminal GND. The second capacitor C2 can reduce the first multiplier B1 to the second data voltage U SRC2 The impact of AC output.

[0092] In some embodiments, Fig.10 As shown, the data voltage adjustment unit includes a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 is connected between the first input terminal 10 of the first multiplier B1 and the ground terminal GND. The second capacitor C2 is connected between the output terminal of the first multiplier B1 and the ground terminal GND. The beneficial effects are the same as those of the above embodiments and will not be repeated here.

[0093] In some embodiments, Fig.11As shown, the display panel includes a first transistor TFT1 and a second transistor TFT2, the gate of the first transistor TFT1 is connected to the first scan line, the first electrode of the first transistor TFT1 is connected to the sub-pixel, the second electrode of the first transistor TFT1 is connected to the first electrode of the second transistor TFT2, the gate of the second transistor TFT2 is connected to the second scan line, and the second electrode of the second transistor TFT2 receives the second data voltage U SRC2 ;

[0094] The first charging time control signal CTRL1 includes a first timing signal corresponding to the first scan line and a second timing signal corresponding to the second scan line (not shown in the figure); the second charging time control signal CTRL2 includes a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; the processing unit is configured to determine the first charging time t1 according to the first timing signal and the second timing signal, and determine the second charging time t2 according to the third timing signal and the fourth timing signal.

[0095] In this embodiment, the first charging time t1 can be determined by the first timing signal and the second timing signal stored in the storage unit of the display driver, and the second charging time t2 can be determined by the third timing signal and the fourth timing signal input by the controller. In the display driving process, the first charging time t1, the second charging time t2 and the first data voltage U obtained by converting the image data DSIDATA input by the controller can be obtained. SRC1 The input data voltage adjustment unit processes to obtain a second data voltage U SRC2 , a third timing signal may be input to the first transistor TFT1 through the first scan line, a fourth timing signal may be input to the second transistor TFT2 through the second scan line, and a second data voltage U may be input to the second transistor TFT2 through the output end of the data voltage adjustment unit. SRC2 , to realize the charging of sub-pixels.

[0096] In some embodiments, Fig.11 As shown, the first scan line may be a gate line, and the second scan line may be a demux scan line. The first transistor TFT1 may be a switch transistor of a pixel circuit connected to a sub-pixel, and the second transistor TFT2 may be a switch transistor for controlling demultiplexing in a multiplexer. The third timing signal may be a clock signal CLK1, CLK2, CLK3, CLK4 input by a controller, and the fourth timing signal may be a multiplexer control signal MUX1, MUX2, MUX3, MUX4 input by a controller.

[0097] In some embodiments, the processing unit is specifically configured to: determine the duration during which the first timing signal and the second timing signal are both high level within a row of sub-pixel scanning period as the first charging duration t1; and determine the duration during which the third timing signal and the fourth timing signal are both high level within a row of sub-pixel scanning period as the second charging duration t2.

[0098] In this embodiment, the first charging time t1 and the second charging time t2 can be further determined by setting the GOA timing signal. Fig.12 (a) shows the original GOA timing diagram of the storage unit when the display driver is in the standard driving mode (MUX1-2-1-2). Fig.12 (b) shows the GOA timing diagram set by the controller. As can be seen from the figure, the MUX width of the original GOA timing stored in the storage unit of the display driver is different from the MUX width of the GOA timing set by the controller, which will further cause the sub-pixel charging duration t2 to be set by the controller to be different from the sub-pixel charging duration t1 originally stored by the display driver. In this example, the first timing signal is the first CLK signal stored in the storage unit of the display driver, the second timing signal is the first MUX signal stored in the storage unit of the display driver, the third timing signal is the second CLK signal input by the controller, and the fourth timing signal is the second MUX signal input by the controller. In this embodiment, the first charging duration t1 can be determined by the duration that the first CLK signal and the first MUX signal are both high in the scanning duration of a row of pixels stored in the storage unit; the second charging duration t2 can be determined by the duration that the second CLK signal and the second MUX signal are both high in the scanning duration of a row of pixels set by the controller. In this example, the first charging time t1 = the width corresponding to the time when the first MUX signal is at a high level, and the second charging time t2 = the width corresponding to the time when the second MUX signal is at a high level. In one example, the first charging time t1 is 5 μs, and the second charging time t2 is 10 μs.

[0099] In other embodiments, Fig.13 As shown, Fig.13 The GOA timing diagram of the storage unit when the display driver is in the power saving driving mode (MUX1-2-2-1). In this embodiment, the first charging time t1 = (the width corresponding to the time when the first MUX signal is at a high level - Gap CLK ) / 2. Similarly, the second charging time t2 = (the width corresponding to the time when the second MUX signal is at a high level - Gap CLK ) / 2 (not shown in the figure). Then, the first data voltage U SRC1 Determine the second data voltage U SRC2 The numerical value of .

[0100] It should be noted that the first data voltage U in this application is SRC1 and the second data voltage U SRC2 It can be a positive or negative flip polarity signal (SRC), such as Fig.14 As shown, the SRC signal can be turned on or off according to the turning on of SOE (display driver internal enable signal).

[0101] For ease of understanding, the present application provides a specific embodiment as follows:

[0102] Taking 180 grayscale as an example, assuming that after the display driver of the display device performs gamma debugging, the base voltage of 180 grayscale is 4V, the compensation voltage of 180 grayscale is 0.6V, and the first data voltage U SRC1 =Equal to the basic voltage + compensation voltage, the first data voltage U0 of 0 gray scale is 0.1V, and the first data voltage U2 of 255 gray scale is 0.1V. 255 The first charging time t1 stored in the storage unit of the display driver is 5 μs, and the second charging time t2 to be set by the controller is 10 μs. n is the gamma constant of the n-th gray scale, the second data voltage U SRC2 =U SRC1 *t1 / t2, then:

[0103] The brightness corresponding to the different gray levels originally set in the storage unit of the display driver is:

[0104] L180=K 180 *U SRC1 *t1=K 180 *(0.6V+4V)*5μs=23K 180 ;

[0105] L255=K 255 *U 255 *t1=K 255 *6V*5μs=30K 255 ;

[0106] L0=K0*U0*t1=K0*0.1V*5μs=0.5K0;

[0107] Gamma value L180 =log(L 180 -L0) / log(L 255 -L0)=log(23K 180 -0.5K0) / log(30K 255 -0.5K0).

[0108] When the controller needs to reset the charging time of the sub-pixel, in the comparative example (the display driver is not provided with a data voltage adjustment unit), the brightness corresponding to different grayscales is:

[0109] L180=K 180 *U SRC1 *t2=K 180 *(0.6V+4V)*10μs=46K 180 ;

[0110] L255=K 255 *U 255 *t2=K 255 *6V*10μs=60K 255 ;

[0111] L0=K0*U0*t2=K0*0.1V*10μs=K0;

[0112] Gamma value L180 =log(L 180 -L0) / log(L 255 -L0)=log(46K 180 -K0) / log(60K 255 -K0). In the embodiment of the present application (display driver sets data voltage adjustment unit), the brightness corresponding to different gray scales is:

[0113] L180=K 180 *U SRC2 *t2=K 180 *U SRC1 *t1 / t2*t2=K 180 *(0.6V+4V)*5μs / 10μs*10μs

[0114] =23K 180 ;

[0115] L255=K 255 *U 255 *t1 / t2*t2=K 255 *6V*5μs / 10μs*10μs=30K 255 ;

[0116] L0=K0*U0*t1 / t2*t2=K0*0.1V*5μs / 10μs*10μs=0.5K0;

[0117] Gamma value L180 =log(L 180 -L0) / log(L 255 -L0)=log(23K 180 -0.5K0) / log(30K255 -0.5K0).

[0118] It can be seen that the gamma value corresponding to the display driver is significantly different from the gamma value corresponding to the controller. When the controller needs to adjust the charging time of the sub-pixel accordingly, the gamma value corresponding to the display driver is used, which will cause the display brightness of the display panel to be too high, resulting in display abnormality. In this embodiment, the brightness of the display panel can be restored to normal display by adjusting the data voltage without adjusting the gamma value.

[0119] Based on the same inventive concept, the present application also provides a display device, including the display driver, controller and display panel as described above; Figure 1 As shown, the controller is configured to send a second charging duration control signal CTRL2 and image data DSIDATA to the display driver.

[0120] The display device provided in this embodiment and the aforementioned display driver belong to the same inventive concept, and the description of relevant details and beneficial effects can be referred to each other, which will not be repeated here.

[0121] Based on the same inventive concept, the present application also provides a display driving method, combined with Figure 1 As shown, the following steps are included:

[0122] Step 100: Acquire a first charging time control signal CTRL1 stored in a display driver, and a second charging time control signal CTRL2 and image data DSIDATA sent by a controller;

[0123] Step 200: Determine the first charging time t1 according to the first charging time control signal CTRL1, determine the second charging time t2 according to the second charging time control signal CTRL2, and determine the first data voltage U according to the image data DSIDATA SRC1 ;

[0124] Step 300: According to the first charging time t1, the second charging time t2 and the first data voltage U SRC1 , determine the second data voltage U SRC2 , so that the display driver can drive the display according to the second data voltage U SRC2 and the first charging duration control signal CTRL1 to charge the sub-pixel, wherein the first data voltage U SRC1 The product of the first charging time t1 is equal to the second data voltage U SRC2 and the product of the second charging time t2.

[0125] The display driving method provided in this embodiment and the aforementioned display driver belong to the same inventive concept, and the description of relevant details and beneficial effects can be referred to each other, which will not be repeated here, and the same shall apply below.

[0126] In some embodiments, the display panel includes a first transistor TFT1 and a second transistor TFT2, the gate of the first transistor TFT1 is connected to the first scan line, the first electrode of the first transistor TFT1 is connected to the sub-pixel, the second electrode of the first transistor TFT1 is connected to the first electrode of the second transistor TFT2, the gate of the second transistor TFT2 is connected to the second scan line, and the second electrode of the second transistor TFT2 receives the second data voltage U SRC2 ; The first charging time control signal CTRL1 includes a first timing signal corresponding to the first scan line and a second timing signal corresponding to the first scan line; The first charging time control signal CTRL1 includes a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; In step 200, determining the first charging time t1 according to the first charging time control signal CTRL1 and determining the second charging time t2 according to the second charging time control signal CTRL2 specifically includes:

[0127] Step 210: Determine a first charging time length t1 according to the first timing signal and the second timing signal, and determine a second charging time length t2 according to the third timing signal and the fourth timing signal.

[0128] In some embodiments, determining the first charging duration t1 according to the first timing signal and the second timing signal, and determining the second charging duration t2 according to the third timing signal and the fourth timing signal in step 210 specifically includes:

[0129] The duration during which the first timing signal and the second timing signal are both high level in a row of sub-pixel scanning period is determined as the first charging duration t1; and the duration during which the third timing signal and the fourth timing signal are both high level in a row of sub-pixel scanning period is determined as the second charging duration t2.

[0130] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

Claims

1. A display driver, characterized in that: Used in a display device, the display device further comprising a controller and a display panel, the display panel comprising sub-pixels; the display driver comprising: A storage unit configured to store a first charging duration control signal of a sub-pixel within a frame of picture driving period; A receiving unit configured to receive a second charging duration control signal and image data of a sub-pixel within a frame of picture driving period sent by the controller; a processing unit configured to determine a first charging duration according to the first charging duration control signal, determine a second charging duration according to the second charging duration control signal, and determine a first data voltage according to the image data; The data voltage adjustment unit is configured to determine a second data voltage according to the first charging time, the second charging time and the first data voltage, so that the display driver charges the sub-pixel according to the second data voltage and the second charging time control signal, wherein the product of the first data voltage and the first charging time is equal to the product of the second data voltage and the second charging time.

2. The display driver according to claim 1, characterized in that: The data voltage adjustment unit comprises: A first digital-to-analog converter, connected to the processing unit, configured to receive the first charging duration and convert the first charging duration into a first voltage; a second digital-to-analog converter, connected to the processing unit, configured to receive the second charging duration and convert the second charging duration into a second voltage; a division operation circuit, electrically connected to an output terminal of the first digital-to-analog converter and an output terminal of the second digital-to-analog converter, respectively, and configured to generate a feedback signal according to the first voltage and the second voltage; the feedback signal is equal to a ratio of the first voltage to the second voltage; A first multiplier includes a first input terminal and a second input terminal; the first input terminal is connected to the processing unit and is used to receive the first data voltage; the second input terminal is connected to the division operation circuit and is used to receive a feedback signal output by the division operation circuit; the first multiplier is configured to generate the second data voltage according to the first data voltage and the feedback signal, and the second data voltage is equal to the product of the first data voltage and the feedback signal.

3. The display driver according to claim 2, characterized in that: The division operation circuit comprises: a second multiplier, comprising a third input terminal, a fourth input terminal and a first output terminal, wherein the third input terminal is used to receive the second voltage output by the second digital-to-analog converter, and the fourth input terminal is connected to the second input terminal of the first multiplier; an operational amplifier, comprising a non-inverting input terminal, a reverse input terminal, and a second output terminal, wherein the reverse input terminal is connected to the output terminal of the first digital-to-analog converter and the first output terminal of the second multiplier, the non-inverting input terminal is connected to a ground terminal, and the second output terminal is connected to the second input terminal of the first multiplier and the fourth input terminal of the second multiplier; A first resistor and a second resistor, wherein the first resistor is connected between the output terminal of the first digital-to-analog converter and the inverting input terminal of the operational amplifier, and the second resistor is connected between the inverting input terminal of the operational amplifier and the first output terminal of the second multiplier, wherein the resistance value of the first resistor is the same as the resistance value of the second resistor.

4. The display driver according to claim 3, characterized in that: The division operation circuit further includes a third resistor, and the third resistor is connected between the non-inverting input terminal of the operational amplifier and the ground terminal.

5. The display driver according to claim 2, characterized in that: The division operation circuit comprises: a second multiplier, comprising a third input terminal, a fourth input terminal and a first output terminal, wherein the third input terminal is used to receive the second voltage output by the second digital-to-analog converter, and the fourth input terminal is connected to the second input terminal of the first multiplier; an operational amplifier, comprising a non-inverting input terminal, a reverse input terminal, and a second output terminal, wherein the non-inverting input terminal is connected to the first output terminal of the second multiplier and a ground terminal, the reverse input terminal is connected to the output terminal of the first digital-to-analog converter, and the second output terminal is connected to the second input terminal of the first multiplier and the fourth input terminal of the second multiplier; A first resistor and a second resistor, wherein the first resistor is connected between the non-inverting input terminal of the operational amplifier and the ground terminal, and the second resistor is connected between the non-inverting input terminal of the operational amplifier and the first output terminal of the second multiplier; wherein the resistance value of the first resistor is the same as the resistance value of the second resistor.

6. The display driver according to claim 2, characterized in that: The division operation circuit comprises: a second multiplier, comprising a third input terminal, a fourth input terminal and a first output terminal, wherein the third input terminal is used to receive the second voltage output by the second digital-to-analog converter, and the fourth input terminal is connected to the second input terminal of the first multiplier; an operational amplifier, comprising a non-inverting input terminal, a reverse input terminal, and a second output terminal, wherein the non-inverting input terminal is connected to the output terminal of the first digital-to-analog converter, the reverse input terminal is connected to the first output terminal of the second multiplier and a ground terminal, and the second output terminal is connected to the second input terminal of the first multiplier and the fourth input terminal of the second multiplier; A first resistor and a second resistor, wherein the first resistor is connected between the inverting input terminal of the operational amplifier and the ground terminal, and the second resistor is connected between the inverting input terminal of the operational amplifier and the first output terminal of the second multiplier, wherein the resistance value of the first resistor is the same as the resistance value of the second resistor.

7. The display driver according to claim 6, characterized in that: The division operation circuit further includes a third resistor, and the third resistor is connected between the non-inverting input terminal of the operational amplifier and the output terminal of the first digital-to-analog converter.

8. The display driver according to claim 2, characterized in that: The data voltage adjustment unit further includes a first capacitor connected between a first input terminal of the first multiplier and a ground terminal.

9. The display driver according to claim 2, characterized in that: The data voltage adjustment unit further includes a second capacitor connected between an output terminal of the first multiplier and a ground terminal.

10. The display driver according to claim 1, characterized in that: The display panel includes a first transistor and a second transistor, the gate of the first transistor is connected to the first scan line, the first electrode of the first transistor is connected to the sub-pixel, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the second transistor is connected to the second scan line, and the second electrode of the second transistor receives the second data voltage; The first charging duration control signal includes a first timing signal corresponding to the first scan line and a second timing signal corresponding to the second scan line; the second charging duration control signal includes a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; the processing unit is configured to determine the first charging duration according to the first timing signal and the second timing signal, and determine the second charging duration according to the third timing signal and the fourth timing signal.

11. The display driver according to claim 10, characterized in that: The processing unit is specifically configured to: determine the duration during which the first timing signal and the second timing signal are both at a high level within a row of sub-pixel scanning periods as the first charging duration; and determine the duration during which the third timing signal and the fourth timing signal are both at a high level within a row of sub-pixel scanning periods as the second charging duration.

12. A display device, comprising the display driver, controller and display panel according to any one of claims 1 to 11; The controller is configured to send a second charging duration control signal and image data to the display driver.

13. A display driving method, used for a display driver of a display device, wherein the display device further comprises a controller and a display panel, and the display panel comprises sub-pixels; the display driving method comprises: Acquire a first charging duration control signal stored in the display driver, and a second charging duration control signal and image data sent by the controller; determining a first charging duration according to the first charging duration control signal, determining a second charging duration according to the second charging duration control signal, and determining a first data voltage according to the image data; A second data voltage is determined according to the first charging time, the second charging time and the first data voltage, so that the display driver charges the sub-pixel according to the second data voltage and the second charging time control signal, wherein the product of the first data voltage and the first charging time is equal to the product of the second data voltage and the second charging time.

14. The display driving method according to claim 13, characterized in that: The display panel includes a first transistor and a second transistor, the gate of the first transistor is connected to a first scan line, the first electrode of the first transistor is connected to the sub-pixel, the second electrode of the first transistor is connected to the first electrode of the second transistor, the gate of the second transistor is connected to a second scan line, and the second electrode of the second transistor receives the second data voltage; the first charging time control signal includes a first timing signal corresponding to the first scan line and a second timing signal corresponding to the second scan line; the first charging time control signal includes a third timing signal corresponding to the first scan line and a fourth timing signal corresponding to the second scan line; determining the first charging time according to the first charging time control signal and determining the second charging time according to the second charging time control signal specifically includes: The first charging time duration is determined according to the first timing signal and the second timing signal, and the second charging time duration is determined according to the third timing signal and the fourth timing signal.

15. The display driving method according to claim 14, characterized in that: The determining of the first charging duration according to the first timing signal and the second timing signal, and the determining of the second charging duration according to the third timing signal and the fourth timing signal specifically includes: The first charging duration is determined as the time duration during which the first timing signal and the second timing signal are both at a high level within a row of sub-pixel scanning periods; and the second charging duration is determined as the time duration during which the third timing signal and the fourth timing signal are both at a high level within a row of sub-pixel scanning periods.

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