Display device and data transmission method thereof

Abstract

The invention discloses a display device and a data transmission method thereof, which are used for realizing segmentation, caching and delay processing of data needing to be sent to a data driver on a display panel and improving a display effect. The display device comprises a data preprocessing circuit, a data caching circuit connected with the data preprocessing circuit, and a delay processing circuit connected with the data caching circuit. The data caching circuit comprises a plurality of line buffers, a plurality of line buffers and a plurality of line buffers The data preprocessing circuit is used for carrying out data segmentation processing on the image data according to the number of pixel data included in each row of pixels and the number of row buffers in the data caching circuit to obtain a plurality of data packaging packets and outputting each data packaging packet to one row buffer, and the time delay processing circuit is used for carrying out time delay processing on the image data according to the number of the pixel data included in each row of pixels and the number of the row buffers in the data caching circuit. And performing shift and delay adjustment on the data in the data encapsulation packets cached by the row buffer in the data cache circuit, so that the data of different data encapsulation packets of the pixel data in the same row simultaneously reach the corresponding data drivers.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device and a data transmission method thereof. Background Art

[0002] LVDS (Low Voltage Differential Signaling) is a small amplitude differential signal technology that uses a relatively low amplitude signal (about 350mV) to transmit data through a pair of differential PCB (Printed Circuit Board) traces or balanced cables.

[0003] Mini-LVDS is an interface technology that takes up less space and has LVDS functions. It is used in products such as laptops and LCD monitors. The application of Mini-LVDS can reduce the number of signal lines in the LCD monitor control module, which not only makes the circuit board design layout simpler, but also increases the product's work efficiency, reduces system costs, reduces the intensity of electromagnetic interference, and saves more electricity. Summary of the invention

[0004] An embodiment of the present application provides a display device and a data transmission method thereof, which are used to implement segmentation, caching, delay processing, etc. of data that needs to be sent to a data driver on a display panel, thereby avoiding the problem of different clock signal delays of different data drivers due to the different lengths of clock signal transmission lines corresponding to different data drivers on a PCB, thereby avoiding problems such as abnormal image data sampling.

[0005] A display device provided by an embodiment of the present application includes: a data preprocessing circuit, a data cache circuit connected to the data preprocessing circuit, and a delay processing circuit connected to the data cache circuit; wherein the data cache circuit includes a plurality of line buffers;

[0006] The data preprocessing circuit is used for:

[0007] receiving image data to be sent to a data driver on the display panel;

[0008] According to the number of pixel data included in each row of pixels and the number of row buffers in the data buffer circuit, the image data is subjected to data segmentation processing to obtain a plurality of data encapsulation packets, wherein each of the data encapsulation packets includes pixel data with continuous pixel positions;

[0009] Outputting each of the data encapsulation packets to one of the row buffers, wherein different data encapsulation packets are output to different row buffers;

[0010] Each of the row buffers is used to buffer one of the data encapsulation packets; wherein the data in the data encapsulation packets buffered by each row buffer is used to be output to a corresponding data driver on the display panel, and different row buffers correspond to different data drivers;

[0011] The delay processing circuit is used to shift and delay the data in the data encapsulation package cached by the row buffer in the data cache circuit, so that the data of different data encapsulation packages of the pixel data of the same row arrive at the corresponding data driver at the same time.

[0012] The display device provided in the embodiment of the present application realizes the segmentation, caching, delay processing, etc. of the data to be sent to the data driver on the display panel through the above-mentioned data preprocessing circuit, the data cache circuit connected to the data preprocessing circuit, and the delay processing circuit connected to the data cache circuit, thereby avoiding the problem of different clock signal delays of different data drivers due to the different lengths of clock signal transmission lines corresponding to different data drivers, thereby avoiding the problem of abnormal image data sampling and improving the display performance of the display device.

[0013] In some embodiments, the data preprocessing circuit is specifically used for:

[0014] For the received image data that needs to be sent to the data driver on the display panel, the image data corresponding to each data driver is arranged in sequence from left to right, or from right to left, according to the order of the data drivers arranged on the display panel, and then the arranged image data is divided to obtain various data encapsulation packages.

[0015] In some embodiments, the number of data drivers of the display panel includes 6, which are arranged on the display panel in the order from left to right, namely, a first data driver, a second data driver, a third data driver, a fourth data driver, a fifth data driver, and a sixth data driver;

[0016] The data buffer circuit includes 6 row buffers, which are the first row buffer, the second row buffer, the third row buffer, the fourth row buffer, the fifth row buffer, and the sixth row buffer in sequence;

[0017] The data preprocessing circuit divides the received image data to be sent to the data driver on the display panel into 6 data encapsulation packets, namely a first data encapsulation packet, a second data encapsulation packet, a third data encapsulation packet, a fourth data encapsulation packet, a fifth data encapsulation packet, and a sixth data encapsulation packet;

[0018] Wherein, the first data encapsulation packet corresponds to the first row buffer, and the first row buffer corresponds to the first data driver;

[0019] The second data encapsulation packet corresponds to the second line buffer, and the second line buffer corresponds to the second data driver;

[0020] The third data encapsulation packet corresponds to the third row buffer, and the third row buffer corresponds to the third data driver;

[0021] The fourth data encapsulation packet corresponds to the fourth row buffer, and the fourth row buffer corresponds to the fourth data driver;

[0022] The fifth data encapsulation packet corresponds to the fifth row buffer, and the fifth row buffer corresponds to the fifth data driver;

[0023] The sixth data encapsulation packet corresponds to the sixth row buffer, and the sixth row buffer corresponds to the sixth data driver.

[0024] In some embodiments, the number of pixel data included in each of the data encapsulation packets is the same.

[0025] In some embodiments, each row includes 1920 pixel data; wherein the first data encapsulation package includes pixel data of pixel 1 to pixel 320; the second data encapsulation package includes pixel data of pixel 321 to pixel 640; the third data encapsulation package includes pixel data of pixel 641 to pixel 960; the fourth data encapsulation package includes pixel data of pixel 961 to pixel 1280; the fifth data encapsulation package includes pixel data of pixel 1281 to pixel 1600; and the sixth data encapsulation package includes pixel data of pixel 1601 to pixel 1920.

[0026] In some embodiments, the image data to be sent to the data driver on the display panel is small amplitude differential signal Mini-LVDS data.

[0027] In some embodiments, the display device further comprises:

[0028] The data mapping circuit is used to perform data mapping processing on the data in the data encapsulation package cached by each row buffer after being processed by the delay processing circuit according to the Mini-LVDS data packaging method, and then transmit it to the corresponding data driver on the display panel.

[0029] In some embodiments, the data preprocessing circuit, the data buffer circuit, the delay processing circuit, and the data mapping circuit are all arranged on a timing controller in the display device.

[0030] In some embodiments, the display device further comprises: a display panel, and six data drivers disposed on the display panel; wherein the first data driver, the second data driver, and the third data driver are respectively connected to the first port on the left side of the timing controller; the fourth data driver, the fifth data driver, and the sixth data driver are respectively connected to the second port on the right side of the timing controller;

[0031] A pair of clock lines and three pairs of data lines are arranged between each of the data drivers and the timing controller, and the data sent by the data mapping circuit to each of the data drivers includes a clock signal and RGB three-channel pixel data, wherein the clock line transmits the clock signal, and each pair of the three pairs of data lines is used to transmit pixel data of one channel of the RGB three-channel pixel data.

[0032] A data transmission method provided in an embodiment of the present application includes:

[0033] A data preprocessing circuit disposed in the display device receives image data to be sent to a data driver on a display panel in the display device;

[0034] The data preprocessing circuit performs data segmentation processing on the image data according to the number of pixel data included in each row of pixels and the number of row buffers in the data buffer circuit provided in the display device to obtain a plurality of data encapsulation packets, wherein each of the data encapsulation packets includes pixel data of continuous pixel positions;

[0035] The data preprocessing circuit outputs each of the data encapsulation packets to one of the row buffers, wherein different data encapsulation packets are output to different row buffers;

[0036] Each of the row buffers caches one of the data encapsulation packets; wherein the data in the data encapsulation packets cached by each row buffer is used to be output to a corresponding data driver on the display panel, and different row buffers correspond to different data drivers;

[0037] The delay processing circuit arranged in the display device shifts and delays the data in the data encapsulation package cached by the row buffer in the data cache circuit, so that the data of different data encapsulation packages of the pixel data of the same row arrive at the corresponding data driver at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A schematic diagram of the structure of a display device provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of a display panel provided in an embodiment of the present application with six data drivers;

[0041] Figure 3 A schematic diagram of wiring between a data driver and a TCON provided on a display panel according to an embodiment of the present application;

[0042] Figure 4 A schematic diagram of the connection relationship between a data preprocessing circuit, a data buffer circuit, and a delay processing circuit provided in a display device according to an embodiment of the present application;

[0043] Figure 5 A schematic diagram of a data cache circuit provided in an embodiment of the present application including 6 row caches;

[0044] Figure 6 A schematic diagram of the corresponding relationship between the data encapsulation package, the row buffer, and the data driver provided in the embodiment of the present application;

[0045] Figure 7 A schematic diagram of the structure of each data encapsulation package obtained by data segmentation provided in an embodiment of the present application;

[0046] Figure 8 The display device provided in the embodiment of the present application further includes a schematic diagram of a data mapping circuit connected to the delay processing circuit;

[0047] Fig. 9 A schematic diagram of a data path cached in each row buffer provided in an embodiment of the present application, firstly being shifted and delayed by a delay processing circuit, then being sent to a data mapping circuit, and then being sent to a corresponding data driver after data mapping processing by the data mapping circuit;

[0048] Fig.10 A schematic diagram of the overall flow of a Mini-LVDS data processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] An embodiment of the present application provides a display device and a data transmission method thereof, which are used to implement segmentation, caching, delay processing, etc. of data that needs to be sent to a data driver on a display panel, thereby avoiding the problem of different clock signal delays of different data drivers due to the different lengths of clock signal transmission lines corresponding to different data drivers on a PCB, thereby avoiding problems such as abnormal image data sampling.

[0051] Among them, the method and the device are based on the same application concept. Since the method and the device solve the problem in a similar principle, the implementation of the device and the method can refer to each other, and the repeated parts will not be repeated.

[0052] The terms "first", "second", etc. (if any) in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than the content illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] The following examples and embodiments are to be understood as illustrative examples only. Although this specification may refer to "one", "an" or "some" examples or embodiments in several places, this does not mean that each such reference relates to the same example or embodiment, nor does it mean that the feature applies only to a single example or embodiment. Individual features of different embodiments may also be combined to provide other embodiments. In addition, terms such as "including" and "comprising" should be understood as not limiting the described embodiments to only those features that have been mentioned; such examples and embodiments may also include features, structures, units, modules, etc. that are not specifically mentioned.

[0054] The following is a detailed description of each embodiment of the present application in conjunction with the accompanying drawings. It should be noted that the display order of the embodiments of the present application only represents the order of the embodiments, and does not represent the advantages and disadvantages of the technical solutions provided by the embodiments.

[0055] like Figure 1 , is a schematic diagram of the structure of a display device shown in an embodiment of the present application, the display device includes: a display panel 101, a backlight assembly 102, a backlight driving circuit 103, an image processing unit 104 and a timing controller 105.

[0056] Among them, the backlight component 102 includes multiple backlight sources, each of which can adjust the brightness according to each backlight brightness control signal. The backlight component 102 can be divided into multiple backlight partitions corresponding to each backlight source. Each backlight partition can emit light of different brightness, and form a display image by performing light modulation through the display panel 101 placed above it.

[0057] The backlight driving circuit 103 includes a backlight processing unit with a processor function and a PWM driver ( Figure 1 not shown).

[0058] After being processed by the image processing unit 104 , the image signal generates image data, which is input to the timing controller 105 for driving the display panel 101 to perform light modulation.

[0059] In addition, in the image processing unit 104, after receiving the image signal, on the one hand, decoding processing is performed to obtain image data and the image data is output to the timing controller; on the other hand, according to the image signal, the backlight data of each partition is obtained according to the predetermined partition algorithm, and the global dimming signal is obtained, wherein the global dimming signal can also be obtained according to the user input adjustment, the backlight mode selection, and the combination of ambient light factors, etc., and the global dimming signal can be a PWM (Pulse Width Modulation) signal; and, the synchronization signal and the backlight data of each partition and the global dimming signal are obtained from the image signal and output to the backlight driving circuit 103, so as to drive the PWM driver according to the partition backlight data, so as to control the brightness of the backlight source of each partition. Among them, the image processing unit 104 can be the main processing chip of the image display device, such as: SoC chip (System-on-a-Chi, system-level chip), or other video processing chips.

[0060] Among them, in the timing controller 105, that is, the TCON (logic board, also known as the screen driver board, which is the timing controller of the display panel) chip, there is a data offset problem for the Mini-LVDS data transmission protocol, that is, when data is transmitted on the differential transmission line, at the same time, there is a data offset between different differential pairs that is not synchronized. In some embodiments, the method for adjusting the data offset is: ① adjusting the offset (Skew) between data pairs (Data pair); ② adjusting the offset between the clock signal (clock, referred to as CLK) and the data pair.

[0061] These two methods can correct the offset between data and clock to a certain extent, but they cannot solve the delay problem of the far-end and near-end clock transmission lines. The delay problem of the far-end and near-end clock transmission lines will lead to the phase inconsistency problem between the far-end data sampling and the near-end data sampling.

[0062] like Figure 2 As shown, for example, the display panel provides signals to the data lines of its pixel units through six data drivers (also called source drivers), which are a first data driver, a second data driver, a third data driver, a fourth data driver, a fifth data driver, and a sixth data driver;

[0063] See also Figure 3 , the timing controller TCON outputs Mini-LVDS data to the data driver through two signal output terminals, wherein the two output terminals (for example, respectively represented as Port0 and Port1) are respectively located on the left and right sides of TCON (not shown in the figure), one output terminal Port0 outputs Mini-LVDS data to the first data driver to the third data driver, and the other output terminal Port1 outputs Mini-LVDS data to the fourth data driver to the sixth data driver. Between each data driver and the timing controller TCON, there is a pair of clock lines (CLK) and 3 pairs of data transmission lines (for example, respectively represented as pair0, pair1, pair2), and these lines are laid out on the PCB ( Figure 3 In the figure, only the specific signal connection line between the first data driver and the timing controller is used as an example, and the wiring between the remaining data drivers and the timing controller is the same). This data transmission method between the timing controller and the data driver is also called a 2-port 3-pair Mini-LVDS data transmission method.

[0064] Among them, different data drivers are arranged at different positions on the display panel, such as Figure 2 As shown, the first data driver and the sixth data driver are far away from the timing controller, so they are called remote data drivers; the third data driver and the fourth data driver are close to the timing controller, so they are called near-end data drivers.

[0065] The connection lines (including data lines and clock lines) between the first data driver and the sixth data driver at the far end and TCON are longer than those between the third data driver and the fourth data driver at the near end. The clock signal arriving at the first data driver at the far end and the clock signal arriving at the third data driver at the near end have a certain time delay (i.e., a certain phase difference). If this phase difference is too large, it will cause the data sampling to shift, resulting in the failure of the first data driver at the far end to sample data correctly, thereby causing abnormal display of the screen on the display panel (Panel).

[0066] Therefore, see Figure 4 , the display device provided in the embodiment of the present application includes:

[0067] A data preprocessing circuit (Data Mapping) 201, a data cache circuit 202 connected to the data preprocessing circuit 201, and a delay processing circuit (Data Shift / Delay) 203 connected to the data cache circuit 202; wherein the data cache circuit 202 includes a plurality of line buffers (Line Buffer) ( Figure 4 not shown);

[0068] The data preprocessing circuit 201 is used for:

[0069] receiving image data to be sent to a data driver on the display panel;

[0070] According to the number of pixel data included in each row of pixels and the number of row buffers in the data buffer circuit, the image data is subjected to data segmentation processing to obtain a plurality of data encapsulation packets, wherein each of the data encapsulation packets includes pixel data with continuous pixel positions;

[0071] Outputting each of the data encapsulation packets to one of the row buffers, wherein different data encapsulation packets are output to different row buffers;

[0072] Each of the row buffers is used to buffer one of the data encapsulation packets; wherein the data in the data encapsulation packets buffered by each row buffer is used to be output to a corresponding data driver on the display panel, and different row buffers correspond to different data drivers;

[0073] The delay processing circuit 203 is used to shift and delay the data in the data encapsulation package cached by the row buffer in the data cache circuit, so that the data of different data encapsulation packages of the pixel data of the same row arrive at the corresponding data driver at the same time.

[0074] Wherein, the delay processing circuit 203, for example, includes a shift register, and through the processing of the shift register, a delayed sending time is set in each data encapsulation packet, so that different data encapsulation packets each have a specific time to be sent to the data driver, so that the external clock signal line connected to the data driver with a longer length will be sent earlier, and the external clock signal line connected to the data driver with a shorter length will be sent later. For example, after being processed by the above-mentioned delay processing circuit, the data that needs to be sent to the first data driver is sent earlier from the timing controller than the data that needs to be sent to the third data driver, and finally, the data in each data encapsulation packet can reach each data driver at the same time.

[0075] Therefore, the display device provided in the embodiment of the present application realizes the segmentation, caching, delay processing, etc. of the data to be sent to the data driver on the display panel through the above-mentioned data preprocessing circuit, the data cache circuit connected to the data preprocessing circuit, and the delay processing circuit connected to the data cache circuit, thereby avoiding the problem of different clock signal delays of different data drivers due to the different lengths of the clock signal transmission lines corresponding to different data drivers, thereby avoiding the problem of abnormal image data sampling and improving the display performance of the display device.

[0076] In some embodiments, the data preprocessing circuit 201 is specifically used for:

[0077] For the received image data that needs to be sent to the data driver on the display panel, the image data corresponding to each data driver is arranged in sequence from left to right, or from right to left, according to the order of the data drivers arranged on the display panel, and then the arranged image data is divided to obtain various data encapsulation packages.

[0078] In some embodiments, the number of data drivers of the display panel includes 6, for example Figure 2 As shown, in the order from left to right of the data drivers arranged on the display panel, they are respectively a first data driver, a second data driver, a third data driver, a fourth data driver, a fifth data driver, and a sixth data driver;

[0079] The data buffer circuit includes 6 row buffers, such as Figure 5 As shown, they are the first row buffer, the second row buffer, the third row buffer, the fourth row buffer, the fifth row buffer, and the sixth row buffer in sequence;

[0080] The data preprocessing circuit divides the received image data to be sent to the data driver on the display panel into 6 data encapsulation packets, namely a first data encapsulation packet, a second data encapsulation packet, a third data encapsulation packet, a fourth data encapsulation packet, a fifth data encapsulation packet, and a sixth data encapsulation packet;

[0081] Among them, Figure 6 As shown, the first data encapsulation packet corresponds to the first row buffer, and the first row buffer corresponds to the first data driver;

[0082] The second data encapsulation packet corresponds to the second line buffer, and the second line buffer corresponds to the second data driver;

[0083] The third data encapsulation packet corresponds to the third row buffer, and the third row buffer corresponds to the third data driver;

[0084] The fourth data encapsulation packet corresponds to the fourth row buffer, and the fourth row buffer corresponds to the fourth data driver;

[0085] The fifth data encapsulation packet corresponds to the fifth row buffer, and the fifth row buffer corresponds to the fifth data driver;

[0086] The sixth data encapsulation packet corresponds to the sixth row buffer, and the sixth row buffer corresponds to the sixth data driver.

[0087] In some embodiments, the number of pixel data included in each of the data encapsulation packets is the same.

[0088] In some embodiments, each row includes 1920 pixel data; wherein the first data encapsulation package includes pixel data of pixel 1 to pixel 320; the second data encapsulation package includes pixel data of pixel 321 to pixel 640; the third data encapsulation package includes pixel data of pixel 641 to pixel 960; the fourth data encapsulation package includes pixel data of pixel 961 to pixel 1280; the fifth data encapsulation package includes pixel data of pixel 1281 to pixel 1600; and the sixth data encapsulation package includes pixel data of pixel 1601 to pixel 1920.

[0089] In some embodiments, the image data to be sent to the data driver on the display panel is small amplitude differential signal Mini-LVDS data.

[0090] For example Figure 7As shown, the data preprocessing circuit preprocesses 3 pairs of Mini-LVDS data at 2 ports, specifically including: segmenting the Mini-LVDS data, for example, pixel 1 to pixel 320 is a data encapsulation package, pixel 321 to pixel 640 is a data encapsulation package, pixel 641 to pixel 960 is a data encapsulation package, and so on ( Figure 7 Only three data encapsulation packets are shown in the figure), resulting in six data encapsulation packets. Figure 7 Port0_pair0 shown in the figure indicates data transmitted on the first pair of data transmission lines pair0 between the output port Port0 on the TCON and the data driver; Port0_pair1 shown in the figure indicates data transmitted on the second pair of data transmission lines pair1 between the output port Port0 on the TCON and the data driver; Port0_pair2 shown in the figure indicates data transmitted on the third pair of data transmission lines pair0 between the output port Port2 on the TCON and the data driver. Pixel means pixel, R indicates red sub-pixel, G indicates green sub-pixel, and B indicates blue sub-pixel.

[0091] That is to say, if each row includes 1920 pixel data and the number of data drivers (referred to as drivers) of the display panel includes 6, the data preprocessing circuit divides the Mini-LVDS data corresponding to the same row of pixels into 6 data encapsulation packages, namely the first data encapsulation package, the second data encapsulation package, the third data encapsulation package, the fourth data encapsulation package, the fifth data encapsulation package, and the sixth data encapsulation package.

[0092] It can be seen that the main purpose and function of the data preprocessing circuit is to perform a new mapping of the Mini-LVDS data that needs to be sent to the data driver after TCON processing, and to map it according to the data corresponding to the near-end driver and the far-end driver. For example: each row of data on the image includes 1920*3 sub-pixel data, and the mapped data will be arranged in the order of the far-end first data driver → the second data driver → the near-end third data driver → the near-end fourth data driver → the fifth driver → the far-end sixth data driver, and the data required for each driver will be arranged.

[0093] Then, the data cache circuit will cache the 1920*3 sub-pixel data of each row through 6 row buffers, and the data of the 6 row buffers respectively correspond to the data required by the 6 driving positions. For example: if the data of each row is 1920 pixel data, then row buffer 1 corresponds to the data required by data driver 1 (data of 1-320 pixels), row buffer 2 corresponds to the data required by driver 2 (data of 321-640 pixels), row buffer 3 corresponds to the data required by data driver 3 (data of 641-960 pixels), row buffer 4 corresponds to the data required by driver 4 (data of 961-1280 pixels), row buffer 5 corresponds to the data required by driver 5 (data of 1281-1600 pixels), and row buffer 6 corresponds to the data required by driver 6 (data of 1601-1920 pixels). At this time, the data of the 6 row buffers are in a parallel relationship, that is, there is no delay relationship and timing relationship between the cached data.

[0094] In some embodiments, see Figure 8 The display device further includes: a data mapping circuit (Data ReMapping) 204 connected to the delay processing circuit 203.

[0095] The data mapping circuit 204 is used to perform data mapping processing on the data in the data encapsulation package cached by each row buffer after being processed by the delay processing circuit according to the Mini-LVDS data packaging method, and then transmit it to the corresponding data driver on the display panel, that is, for each data channel processed by the delay processing circuit (the data channel is the data from a row buffer), it is re-mapped and packaged according to the 8-bit 3pair mode of Mini-LVDS data and transmitted to the corresponding data driver.

[0096] See also Fig. 9 For each data cached in the row buffer, it is first shifted and delayed by the delay processing circuit, and then sent to the data mapping circuit. After the data mapping processing by the data mapping circuit, it is sent to the corresponding data driver.

[0097] In some embodiments, the data preprocessing circuit, the data buffer circuit, the delay processing circuit, and the data mapping circuit are all arranged on the timing controller in the display device, that is, they are all arranged on Figure 1 or Figure 2 The timing controller shown in FIG. 1 is used as an IP functional module.

[0098] In some embodiments, Figure 2As shown, the display device further includes: a display panel, and 6 data drivers arranged on the display panel; wherein the first data driver, the second data driver, and the third data driver are respectively connected to the first port on the left side of the timing controller; the fourth data driver, the fifth data driver, and the sixth data driver are respectively connected to the second port on the right side of the timing controller;

[0099] A pair of clock lines and three pairs of data lines are provided between each of the data drivers and the timing controller, and the data sent by the data mapping circuit to each of the data drivers includes a clock signal and RGB three-channel pixel data, wherein the clock line transmits the clock signal, and each pair of the three pairs of data lines is used to transmit pixel data of one channel of the RGB three-channel pixel data. Figure 3 As shown, the clock line pair between the first data driver and the timing controller transmits the clock signal, the data signal line pair pair0 between the first data driver and the timing controller transmits the R channel pixel data, the data signal line pair pair1 between the first data driver and the timing controller transmits the G channel pixel data, and the data signal line pair pair2 between the first data driver and the timing controller transmits the B channel pixel data. The same is true for other data drivers, which will not be repeated here.

[0100] See also Fig.10 , corresponding to the above-mentioned display device, an embodiment of the present application provides a data transmission method, including:

[0101] S11, a data preprocessing circuit provided in the display device receives image data to be sent to a data driver on a display panel in the display device;

[0102] S12, the data preprocessing circuit performs data segmentation processing on the image data according to the number of pixel data included in each row of pixels and the number of row buffers in the data buffer circuit provided in the display device to obtain a plurality of data encapsulation packets, wherein each of the data encapsulation packets includes pixel data of continuous pixel positions;

[0103] S13, the data preprocessing circuit outputs each of the data encapsulation packets to one of the row buffers, wherein different data encapsulation packets are output to different row buffers;

[0104] S14, each of the row buffers caches one of the data encapsulation packets; wherein the data in the data encapsulation packet cached by each row buffer is used to be output to a corresponding data driver on the display panel, and different row buffers correspond to different data drivers;

[0105] S15. A delay processing circuit is provided in the display device to shift and delay the data in the data encapsulation package cached by the row buffer in the data cache circuit, so that the data of different data encapsulation packages of the pixel data of the same row arrive at the corresponding data driver at the same time (the specific shift delay processing method can be implemented by using the existing technology and will not be described in detail in the embodiments of the present application).

[0106] In some embodiments, the step S11 specifically includes:

[0107] For the received image data that needs to be sent to the data driver on the display panel, the image data corresponding to each data driver is arranged in sequence from left to right, or from right to left, according to the order of the data drivers arranged on the display panel, and then the arranged image data is divided to obtain various data encapsulation packages.

[0108] In some embodiments, the number of data drivers of the display panel includes 6, which are arranged on the display panel in the order from left to right, namely, a first data driver, a second data driver, a third data driver, a fourth data driver, a fifth data driver, and a sixth data driver;

[0109] The data buffer circuit includes 6 row buffers, which are the first row buffer, the second row buffer, the third row buffer, the fourth row buffer, the fifth row buffer, and the sixth row buffer in sequence;

[0110] The data preprocessing circuit divides the received image data to be sent to the data driver on the display panel into 6 data encapsulation packets, namely a first data encapsulation packet, a second data encapsulation packet, a third data encapsulation packet, a fourth data encapsulation packet, a fifth data encapsulation packet, and a sixth data encapsulation packet;

[0111] Wherein, the first data encapsulation packet corresponds to the first row buffer, and the first row buffer corresponds to the first data driver;

[0112] The second data encapsulation packet corresponds to the second line buffer, and the second line buffer corresponds to the second data driver;

[0113] The third data encapsulation packet corresponds to the third row buffer, and the third row buffer corresponds to the third data driver;

[0114] The fourth data encapsulation packet corresponds to the fourth row buffer, and the fourth row buffer corresponds to the fourth data driver;

[0115] The fifth data encapsulation packet corresponds to the fifth row buffer, and the fifth row buffer corresponds to the fifth data driver;

[0116] The sixth data encapsulation packet corresponds to the sixth row buffer, and the sixth row buffer corresponds to the sixth data driver.

[0117] In some embodiments, the number of pixel data included in each of the data encapsulation packets is the same.

[0118] In some embodiments, each row includes 1920 pixel data; wherein the first data encapsulation package includes pixel data of pixel 1 to pixel 320; the second data encapsulation package includes pixel data of pixel 321 to pixel 640; the third data encapsulation package includes pixel data of pixel 641 to pixel 960; the fourth data encapsulation package includes pixel data of pixel 961 to pixel 1280; the fifth data encapsulation package includes pixel data of pixel 1281 to pixel 1600; and the sixth data encapsulation package includes pixel data of pixel 1601 to pixel 1920.

[0119] In some embodiments, the image data to be sent to the data driver on the display panel is small amplitude differential signal Mini-LVDS data.

[0120] In some embodiments, the method further comprises:

[0121] Through the data mapping circuit connected to the delay processing circuit, the data in the data encapsulation package cached by each row buffer after being processed by the delay processing circuit is data mapped according to the Mini-LVDS data packaging method, and then transmitted to the corresponding data driver on the display panel.

[0122] In some embodiments, the data preprocessing circuit, the data buffer circuit, the delay processing circuit, and the data mapping circuit are all arranged on a timing controller in the display device.

[0123] In some embodiments, the first data driver, the second data driver, and the third data driver are respectively connected to the first port on the left side of the timing controller; the fourth data driver, the fifth data driver, and the sixth data driver are respectively connected to the second port on the right side of the timing controller;

[0124] A pair of clock lines and three pairs of data lines are arranged between each of the data drivers and the timing controller, and the data sent by the data mapping circuit to each of the data drivers includes a clock signal and RGB three-channel pixel data, wherein the clock line transmits the clock signal, and each pair of the three pairs of data lines is used to transmit pixel data of one channel of the RGB three-channel pixel data.

[0125] The method provided in the embodiment of the present application can be applied to the display device provided in the above-mentioned embodiment of the present application, realizing data segmentation, data caching, data shifting and delay, and further data mapping adjustment, avoiding the data sampling abnormality problem caused by the delay of the clock signal transmission line corresponding to different data drivers on the PCB, thereby improving the picture display quality of the display panel.

[0126] It should be noted that the division of functional units (i.e., the above-mentioned modules) in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, the functional units in the various embodiments of the present application may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware or in the form of software functional units.

[0127] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program codes.

[0128] Any of the devices or apparatuses provided in the embodiments of the present application may specifically be a smart TV, a desktop computer, a portable computer, a smart phone, a tablet computer, a personal digital assistant (PDA), etc. It may include a central processing unit (CPU), a memory, an input / output device, etc. The input device may include a keyboard, a mouse, a touch screen, etc. The output device may include a display device, such as a liquid crystal display (LCD), a cathode ray tube (CRT), etc.

[0129] The memory may include a read-only memory (ROM) and a random access memory (RAM), and provides the processor with program instructions and data stored in the memory. In an embodiment of the present application, the memory may be used to store the program of any of the methods provided in the embodiments of the present application.

[0130] The processor calls the program instructions stored in the memory, and the processor is used to execute any of the methods provided in the embodiments of the present application according to the obtained program instructions.

[0131] The present application embodiment also provides a computer program product or computer program, which includes a computer instruction, which is stored in a computer-readable storage medium. The processor of the computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction so that the computer device executes any of the methods described in the above embodiments. The program product can use any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, - but not limited to - an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of readable storage media (non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0132] The embodiment of the present application provides a computer-readable storage medium for storing computer program instructions used by the apparatus provided in the embodiment of the present application, which includes a program for executing any of the methods provided in the embodiment of the present application. The computer-readable storage medium may be a non-transitory computer-readable medium.

[0133] The computer-readable storage medium can be any available medium or data storage device that can be accessed by a computer, including but not limited to magnetic storage (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical storage (such as CD, DVD, BD, HVD, etc.), and semiconductor storage (such as ROM, EPROM, EEPROM, non-volatile memory (NANDFLASH), solid-state drive (SSD)), etc.

[0134] It should be understood that:

[0135] The access technology through which entities in the communication network transmit traffic can be any suitable current or future technology, such as WLAN (Wireless Local Access Network), WiMAX (Worldwide Interoperability for Microwave Access), LTE, LTE-A, 5G, Bluetooth, infrared, etc.; in addition, the embodiments can also apply wired technology, for example, IP-based access technology, such as a wired network or a fixed line.

[0136] Embodiments suitable for being implemented as software code or a portion thereof and running using a processor or processing functionality are independent of the software code and may be specified using any known or future developed programming language, such as a high-level programming language such as objective-C, C, C++, C#, Java, Python, Javascript, other scripting languages, etc., or a low-level programming language such as machine language or assembler.

[0137] The implementation of the embodiments is hardware independent and may be implemented using any known or future developed hardware technology or any mixture thereof, such as a microprocessor or CPU (central processing unit), MOS (metal oxide semiconductor), CMOS (complementary MOS), BiMOS (bipolar MOS), BiCMOS (bipolar CMOS), ECL (emitter coupled logic) and / or TTL (transistor-transistor logic).

[0138] Embodiments may be implemented as separate devices, apparatuses, units, components, or functions, or in a distributed manner, for example, one or more processors or processing functions may be used or shared in a process, or one or more processing segments or processing portions may be used and shared in a process, wherein one physical processor or more than one physical processor may be used to implement one or more processing portions dedicated to a specific process as described.

[0139] The device may be implemented by a semiconductor chip, a chipset, or a (hardware) module including such a chip or chipset.

[0140] The embodiments may also be implemented as any combination of hardware and software, such as ASIC (Application Specific IC (Integrated Circuit)) components, FPGA (Field Programmable Gate Array) or CPLD (Complex Programmable Logic Device) components or DSP (Digital Signal Processor) components.

[0141] The embodiments may also be implemented as a computer program product including a computer usable medium having computer readable program code embodied therein, the computer readable program code being adapted to perform the processes as described in the embodiments, wherein the computer usable medium may be a non-transitory medium.

[0142] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) that contain computer-usable program code.

[0143] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0144] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0145] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0146] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A display device, characterized in that: The display device comprises: a data preprocessing circuit, a data cache circuit connected to the data preprocessing circuit, and a delay processing circuit connected to the data cache circuit; wherein the data cache circuit comprises a plurality of line buffers; The data preprocessing circuit is used for: receiving image data to be sent to a data driver on the display panel; According to the number of pixel data included in each row of pixels and the number of row buffers in the data buffer circuit, the image data is subjected to data segmentation processing to obtain a plurality of data encapsulation packets, wherein each of the data encapsulation packets includes pixel data with continuous pixel positions; Outputting each of the data encapsulation packets to one of the row buffers, wherein different data encapsulation packets are output to different row buffers; Each of the row buffers is used to buffer one of the data encapsulation packets; wherein the data in the data encapsulation packets buffered by each row buffer is used to be output to a corresponding data driver on the display panel, and different row buffers correspond to different data drivers; The delay processing circuit is used to shift and delay the data in the data encapsulation package cached by the row buffer in the data cache circuit, so that the data of different data encapsulation packages of the pixel data of the same row arrive at the corresponding data driver at the same time.

2. The display device according to claim 1, characterized in that The data preprocessing circuit is specifically used for: For the received image data that needs to be sent to the data driver on the display panel, the image data corresponding to each data driver is arranged in sequence from left to right, or from right to left, according to the order of the data drivers arranged on the display panel, and then the arranged image data is divided to obtain various data encapsulation packages.

3. The display device according to claim 2, characterized in that The number of the data drivers of the display panel includes 6, which are arranged on the display panel in the order from left to right, namely, a first data driver, a second data driver, a third data driver, a fourth data driver, a fifth data driver, and a sixth data driver; The data buffer circuit includes 6 row buffers, which are the first row buffer, the second row buffer, the third row buffer, the fourth row buffer, the fifth row buffer, and the sixth row buffer in sequence; The data preprocessing circuit divides the received image data to be sent to the data driver on the display panel into 6 data encapsulation packets, namely a first data encapsulation packet, a second data encapsulation packet, a third data encapsulation packet, a fourth data encapsulation packet, a fifth data encapsulation packet, and a sixth data encapsulation packet; Wherein, the first data encapsulation packet corresponds to the first row buffer, and the first row buffer corresponds to the first data driver; The second data encapsulation packet corresponds to the second line buffer, and the second line buffer corresponds to the second data driver; The third data encapsulation packet corresponds to the third row buffer, and the third row buffer corresponds to the third data driver; The fourth data encapsulation packet corresponds to the fourth row buffer, and the fourth row buffer corresponds to the fourth data driver; The fifth data encapsulation packet corresponds to the fifth row buffer, and the fifth row buffer corresponds to the fifth data driver; The sixth data encapsulation packet corresponds to the sixth row buffer, and the sixth row buffer corresponds to the sixth data driver.

4. The display device according to claim 3, characterized in that: The number of pixel data included in each of the data encapsulation packets is the same.

5. The display device according to claim 4, characterized in that: Each row includes 1920 pixel data; wherein the first data encapsulation package includes pixel data of pixel 1 to pixel 320; the second data encapsulation package includes pixel data of pixel 321 to pixel 640; the third data encapsulation package includes pixel data of pixel 641 to pixel 960; the fourth data encapsulation package includes pixel data of pixel 961 to pixel 1280; the fifth data encapsulation package includes pixel data of pixel 1281 to pixel 1600; and the sixth data encapsulation package includes pixel data of pixel 1601 to pixel 1920.

6. The display device according to claim 5, characterized in that: The image data to be sent to the data driver on the display panel is small amplitude differential signal Mini-LVDS data.

7. The display device according to claim 6, characterized in that: The display device further comprises: a data mapping circuit connected to the delay processing circuit; The data mapping circuit is used to perform data mapping processing on the data in the data encapsulation package cached by each row buffer after being processed by the delay processing circuit according to the Mini-LVDS data packaging method, and then transmit it to the corresponding data driver on the display panel.

8. The display device according to claim 7, characterized in that: The data preprocessing circuit, the data buffer circuit, the delay processing circuit, and the data mapping circuit are all arranged on a timing controller in the display device.

9. The display device according to claim 8, characterized in that: The display device further includes: a display panel, and six data drivers arranged on the display panel; wherein the first data driver, the second data driver, and the third data driver are respectively connected to the first port on the left side of the timing controller; the fourth data driver, the fifth data driver, and the sixth data driver are respectively connected to the second port on the right side of the timing controller; A pair of clock lines and three pairs of data lines are arranged between each of the data drivers and the timing controller, and the data sent by the data mapping circuit to each of the data drivers includes a clock signal and RGB three-channel pixel data, wherein the clock line transmits the clock signal, and each pair of the three pairs of data lines is used to transmit pixel data of one channel of the RGB three-channel pixel data.

10. A data transmission method, characterized in that: The method comprises: A data preprocessing circuit disposed in the display device receives image data to be sent to a data driver on a display panel in the display device; The data preprocessing circuit performs data segmentation processing on the image data according to the number of pixel data included in each row of pixels and the number of row buffers in the data buffer circuit provided in the display device to obtain a plurality of data encapsulation packets, wherein each of the data encapsulation packets includes pixel data of continuous pixel positions; The data preprocessing circuit outputs each of the data encapsulation packets to one of the row buffers, wherein different data encapsulation packets are output to different row buffers; Each of the row buffers caches one of the data encapsulation packets; wherein the data in the data encapsulation packets cached by each row buffer is used to be output to a corresponding data driver on the display panel, and different row buffers correspond to different data drivers; The delay processing circuit arranged in the display device shifts and delays the data in the data encapsulation package cached by the row buffer in the data cache circuit, so that the data of different data encapsulation packages of the pixel data of the same row arrive at the corresponding data driver at the same time.

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