Memory system and receiver

Abstract

A memory system includes a controller and a memory circuit. The controller outputs a first data strobe signal and a second data strobe signal. The memory circuit is coupled to the controller and receives first and second data strobe signals. The memory circuit includes a receiver. The receiver includes a logic conversion circuit. The logic conversion circuit is coupled to the controller. When the first data strobe signal and the second data strobe signal are at the same voltage level, the logic conversion circuit converts the first data strobe signal and the second data strobe signal into a third data strobe signal and a fourth data strobe signal. The third and fourth data strobe signals include different voltage levels. When the first data strobe signal and the second data strobe signal are at different voltage levels, the logic conversion circuit transmits the first data strobe signal as a third data strobe signal and transmits the second data strobe signal as a fourth data strobe signal. According to the scheme, the data strobe signals with the same voltage level are converted into the data strobe signals with different voltage levels specified by JEDEC, so that the memory chip operates normally.

Description

Technical Field

[0001] The present invention relates to an electronic system and an electronic device. Specifically, the present invention relates to a memory system and a receiver. Background Art

[0002] Existing controllers are defined by different memory companies, and the data strobe signal output by the controller violates the Joint Electron Device Engineering Council (JEDEC) memory standard during the standby phase (or undefined phase). Incorrect data strobe signals will cause memory circuit failure.

[0003] Therefore, the above technology still has many defects, and practitioners in this field need to develop other suitable memory systems and receivers. Summary of the invention

[0004] One aspect of the present invention relates to a memory system. The memory system includes a controller and a memory circuit. The controller is used to output a first data selection signal and a second data selection signal. The memory circuit is coupled to the controller and is used to receive the first data selection signal and the second data selection signal. The memory circuit includes a receiver. The receiver includes a logic conversion circuit. When the first data selection signal and the second data selection signal are at the same voltage level, the logic conversion circuit is used to convert the first data selection signal and the second data selection signal into a third data selection signal and a fourth data selection signal. The third data selection signal and the fourth data selection signal converted by the logic conversion circuit include different voltage levels. When the first data selection signal and the second data selection signal are at different voltage levels, the logic conversion circuit is used to transmit the first data selection signal as the third data selection signal, and to transmit the second data selection signal as the fourth data selection signal.

[0005] In some embodiments, the receiver further includes an amplifier. The amplifier is coupled to the logic conversion circuit and is used to receive and amplify the first data strobe signal and the second data strobe signal.

[0006] In some embodiments, the logic conversion circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first inverter, and a second inverter. The first input terminal is used to receive a first data selection signal. The second input terminal is used to receive a second data selection signal. The first output terminal is used to output a third data selection signal. The second output terminal is used to output a fourth data selection signal. The first inverter includes a first terminal and a second terminal. The second terminal of the first inverter is coupled to the second input terminal of the logic conversion circuit. The second inverter includes a first terminal and a second terminal. The second terminal of the second inverter is coupled to the first input terminal of the logic conversion circuit.

[0007] In some embodiments, the logic conversion circuit further includes a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first logic gate is coupled to the first input terminal of the logic conversion circuit. The second input terminal of the first logic gate is coupled to the first terminal of the first inverter. The output terminal of the first logic gate is coupled to the first output terminal of the logic conversion circuit. The second logic gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second logic gate is coupled to the first terminal of the second inverter. The second input terminal of the second logic gate is coupled to the second input terminal of the logic conversion circuit. The output terminal of the second logic gate is coupled to the second output terminal of the logic conversion circuit.

[0008] In some embodiments, the second logic gate further includes a third input terminal. The logic conversion circuit further includes a third inverter. The third inverter includes a first terminal and a second terminal. The first terminal of the third inverter is coupled to the third input terminal. The second terminal of the third inverter is coupled to the output terminal of the first logic gate.

[0009] In some embodiments, the logic conversion circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first inverter, and a second inverter. The first input terminal is used to receive a first data selection signal. The second input terminal is used to receive a second data selection signal. The first output terminal is used to output a third data selection signal. The second output terminal is used to output a fourth data selection signal. The first inverter includes a first terminal and a second terminal. The second terminal of the first inverter is coupled to the first input terminal of the logic conversion circuit. The second inverter includes a first terminal and a second terminal. The second terminal of the second inverter is coupled to the second input terminal of the logic conversion circuit.

[0010] In some embodiments, the logic conversion circuit further includes a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first logic gate is coupled to the first terminal of the first inverter. The second input terminal of the first logic gate is coupled to the second input terminal of the logic conversion circuit. The output terminal of the first logic gate is coupled to the first output terminal of the logic conversion circuit. The first input terminal of the second logic gate is coupled to the first terminal of the second inverter. The first input terminal of the second logic gate is coupled to the first input terminal of the logic conversion circuit. The second input terminal of the second logic gate is coupled to the first terminal of the second inverter. The output terminal of the second logic gate is coupled to the second output terminal of the logic conversion circuit.

[0011] In some embodiments, the second logic gate further includes a third input terminal. The third input terminal of the second logic gate is coupled to the output terminal of the first logic gate.

[0012] Another aspect of the present invention relates to a receiver. The receiver includes an amplifier and a logic conversion circuit. The amplifier is used to receive and amplify a first data selection signal and a second data selection signal from a controller. The logic conversion circuit is coupled to the amplifier. When the first data selection signal and the second data selection signal are at the same voltage level, the logic conversion circuit is used to convert the first data selection signal and the second data selection signal into a third data selection signal and a fourth data selection signal. The third data selection signal and the fourth data selection signal converted by the logic conversion circuit include different voltage levels. When the first data selection signal and the second data selection signal are at different voltage levels, the logic conversion circuit is used to transmit the first data selection signal as the third data selection signal, and to transmit the second data selection signal as the fourth data selection signal.

[0013] In some embodiments, the logic conversion circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first inverter, and a second inverter. The first input terminal is used to receive a first data selection signal. The second input terminal is used to receive a second data selection signal. The first output terminal is used to output a third data selection signal. The second output terminal is used to output a fourth data selection signal. The first inverter includes a first terminal and a second terminal. The second terminal of the first inverter is coupled to the second input terminal of the logic conversion circuit. The second inverter includes a first terminal and a second terminal. The second terminal of the second inverter is coupled to the first input terminal of the logic conversion circuit.

[0014] In some embodiments, the logic conversion circuit further includes a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first logic gate is coupled to the first input terminal of the logic conversion circuit. The second input terminal of the first logic gate is coupled to the first terminal of the first inverter. The output terminal of the first logic gate is coupled to the first output terminal of the logic conversion circuit. The second logic gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second logic gate is coupled to the first terminal of the second inverter. The second input terminal of the second logic gate is coupled to the second input terminal of the logic conversion circuit. The output terminal of the second logic gate is coupled to the second output terminal of the logic conversion circuit.

[0015] In some embodiments, the second logic gate further includes a third input terminal. The logic conversion circuit further includes a third inverter. The third inverter includes a first terminal and a second terminal. The first terminal of the third inverter is coupled to the third input terminal. The second terminal of the third inverter is coupled to the output terminal of the first logic gate.

[0016] In some embodiments, the logic conversion circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first inverter, and a second inverter. The first input terminal is used to receive a first data selection signal. The second input terminal is used to receive a second data selection signal. The first output terminal is used to output a third data selection signal. The second output terminal is used to output a fourth data selection signal. The first inverter includes a first terminal and a second terminal. The second terminal of the first inverter is coupled to the first input terminal of the logic conversion circuit. The second inverter includes a first terminal and a second terminal. The second terminal of the second inverter is coupled to the second input terminal of the logic conversion circuit.

[0017] In some embodiments, the logic conversion circuit further includes a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first logic gate is coupled to the first terminal of the first inverter. The second input terminal of the first logic gate is coupled to the second input terminal of the logic conversion circuit. The output terminal of the first logic gate is coupled to the first output terminal of the logic conversion circuit. The first input terminal of the second logic gate is coupled to the first terminal of the second inverter. The first input terminal of the second logic gate is coupled to the first input terminal of the logic conversion circuit. The second input terminal of the second logic gate is coupled to the first terminal of the second inverter. The output terminal of the second logic gate is coupled to the second output terminal of the logic conversion circuit.

[0018] In some embodiments, the second logic gate further includes a third input terminal. The third input terminal of the second logic gate is coupled to the output terminal of the first logic gate.

[0019] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a memory system and a receiver for converting data strobe signals of the same voltage level into data strobe signals of different voltage levels specified by JEDEC, so that the memory chip or memory circuit operates normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The content of this case can be better understood by referring to the embodiments in the subsequent paragraphs and the following drawings:

[0021] Figure 1 is a circuit block diagram of a memory system according to some embodiments of the present invention;

[0022] Figure 2 is a circuit block diagram of a receiver of a memory circuit of a memory system according to some embodiments of the present invention;

[0023] Figure 3 is a circuit block diagram of a logic conversion circuit of a receiver according to some embodiments of the present invention;

[0024] Figure 4is a signal timing diagram of a plurality of data strobe signals according to some embodiments of the present invention;

[0025] Figure 5 is a signal timing diagram of a plurality of data strobe signals according to some embodiments of the present invention;

[0026] Figure 6 is a circuit block diagram of a logic conversion circuit of a receiver according to some embodiments of the present invention;

[0027] Figure 7 is a circuit block diagram of a logic conversion circuit of a receiver according to some embodiments of the present invention; and

[0028] Figure 8 It is a circuit block diagram of a logic conversion circuit of a receiver according to some embodiments of the present invention. DETAILED DESCRIPTION

[0029] The spirit of the present invention will be clearly illustrated below with accompanying drawings and detailed descriptions. After understanding the embodiments of the present invention, any person skilled in the art can make changes and modifications based on the techniques taught by the present invention without departing from the spirit and scope of the present invention.

[0030] The terms used herein are only for describing specific embodiments and are not intended to be limiting of the present invention. Singular forms such as "a", "this", "here", "this" and "the" as used herein also include plural forms.

[0031] The words “include,” “including,” “have,” “contain,” etc. used in this document are open-ended terms, meaning including but not limited to.

[0032] The terms used herein generally have the ordinary meaning of each term used in the field, in the context of the present invention, and in the specific context, unless otherwise noted. Certain terms used to describe the present invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the present invention.

[0033] Figure 1 FIG. 1 is a circuit block diagram of a memory system 100 according to some embodiments of the present invention. Figure 1, the memory system 100 includes a controller 110 and a memory circuit 120. The controller 110 is coupled to the memory circuit 120. The controller 110 is used to transmit a plurality of signals CMD and a plurality of data through a plurality of data buses D1-D15. The memory circuit 120 includes a receiver 121 and a plurality of control circuits 122. The memory circuit 120 includes a dynamic random access memory (DRAM). In some embodiments, the plurality of signals CMD include a plurality of commands and a plurality of signals generated by the controller 110.

[0034] The controller 110 is used to generate a data strobe signal DQS1 and a data strobe signal DQS2 to the receiver 121 before the receiver 121 enters the preamble stage. The receiver 121 is used to accurately identify each transmission cycle within a clock cycle according to the data strobe signal DQS1 and the data strobe signal DQS2, so that the receiver 121 can receive multiple data from multiple data buses D1-D15.

[0035] In some embodiments, the data select signal DQS1 and the data select signal DQS2 represent the data select signals DQS_c and DQS_t defined by the JEDEC memory standard, respectively. The controller 110 can adjust the relationship between the data select signal DQS (DQS_c and DQS_t) and the clock signal CK (CK_t and CK_c) by writing the equalization characteristics and the feedback characteristics of the device. In detail, the aforementioned controller is used to use the rising edge or the falling edge of each of the data select signal DQS1 and the data select signal DQS2 to sample the clock signal. The technical terms "_t" and "_c" are used to represent the true value and the complement value of the differential signal pair, respectively.

[0036] Then, Double Data Rate Synchronous Dynamic Random-access Memory (DDRSDRAM) stands for "Double Data Rate Synchronous Dynamic Random Access Memory". The technical term "double data rate" can be used for any product that uses two edges (rising edge and falling edge) to periodically change a signal from "1" to "0" (or vice versa), such as a clock or data strobe. Double Data Rate Synchronous Dynamic Random Access Memory uses a bi-directional data strobe (DQS) that moves in parallel with DQ (input / output data) so that the Double Data Rate Synchronous Dynamic Random Access Memory can use the DQS signal as a reference signal to obtain the corresponding DQ signal. One DQS signal can respond to a 4-bit or 8-bit DQ signal. The basic benefit of using the DQS signal is to achieve a high data transfer rate per pin by reducing the access time of the Double Data Rate Synchronous Dynamic Random Access Memory and the propagation delay between the Dynamic Random Access Memory and the memory controller. In addition, we can ignore the skew between the input clock signals of the Dynamic Random Access Memory and the memory controller.

[0037] According to the regulations of the memory industry, such as the Joint Electronic Device Engineering Council (JEDEC), the data strobe signal DQS1 and the data strobe signal DQS2 are required to be at a high level and a low level respectively in the standby stage before the preamble stage (i.e., the data strobe signal DQS1 is at a high level and the data strobe signal DQS2 is at a low level). The preamble stage provides a timing window for the receiving device to enable its capture circuit when there is a known / valid potential on the data strobe signal, thereby avoiding false triggering of the capture circuit. During the preamble stage and the subsequent data input stage, the data strobe signal DQS1 and the data strobe signal DQS2 will change between a high level and a low level. In actual applications, some manufacturers or suppliers do not follow the regulations of the Joint Electronic Device Engineering Council (JEDEC), resulting in that the data selection signal DQS1 and the data selection signal DQS2 provided by these manufacturers are not at the correct level in the standby stage (i.e., the data selection signal DQS1 is at a high level and the data selection signal DQS2 is at a low level).

[0038] Specifically, in the standby phase before the leading phase, the data strobe signal DQS1 and the data strobe signal DQS2 (which should be high and low respectively according to the JEDEC regulations) output by the controller 110 are now mistakenly considered to be at the same voltage level, and the data strobe signal DQS1 and the data strobe signal DQS2 will cause the memory cell to fail. To avoid the memory cell from failing, the embodiment of the present case generates the data strobe signal DQS3 and the data strobe signal DQS4 based on the data strobe signal DQS1 and the data strobe signal DQS2, respectively, and the data strobe signal DQS3 and the data strobe signal DQS4 will follow the JEDEC regulations in the standby phase (i.e., the data strobe signal DQS3 is at a high level and the data strobe signal DQS4 is at a low level).

[0039] Figure 2 According to some embodiments of the present invention, Figure 1 FIG. 1 is a circuit block diagram of a receiver 121 of a memory circuit 120 of a memory system 100 . The receiver 121 includes an amplifier DA and a logic conversion circuit LC.

[0040] The amplifier DA is used to receive and amplify the data strobe signal DQS1 and the data strobe signal DQS2. In some embodiments, the amplifier DA includes a differential amplifier. The logic conversion circuit LC is coupled to the amplifier DA. In other words, the logic conversion circuit LC is used to convert the data strobe signal DQS1 (e.g., 0 or 1) and the data strobe signal DQS2 (e.g., 0 or 1) into the data strobe signal DQS3 (e.g., 1) and the data strobe signal DQS4 (e.g., 0).

[0041] Figure 3 The logic conversion circuit LC1 shown in some embodiments of the present invention corresponds to Figure 2 FIG. 1 is a circuit block diagram of a logic conversion circuit LC of a receiver 121. FIG.

[0042] The logic conversion circuit LC1 includes an input terminal N1, an input terminal N2, an output terminal N3 and an output terminal N4. The input terminal N1 is used to receive a data selection signal DQS1. The input terminal N2 is used to receive a data selection signal DQS2. The output terminal N3 is used to output a data selection signal DQS3. The output terminal N4 is used to output a data selection signal DQS4.

[0043] The logic conversion circuit LC1 further includes an inverter I1, an inverter I2, a logic gate G1, and a logic gate G2. Please count from the top and right of the components in the figure as the first end. Each of the inverter I1 and the inverter I2 includes a first end and a second end. The logic gate G1 includes an input end A, an input end B, and an output end X. The logic gate G2 includes an input end C, an input end D, and an output end Y. In some embodiments, the logic gate G1 includes an OR gate. The logic gate G2 includes an AND gate.

[0044] In some embodiments, the input terminal A of the logic gate G1 is coupled to the input terminal N1 of the logic conversion circuit LC1. The input terminal B of the logic gate G1 is coupled to the first terminal of the inverter I1. The second terminal of the inverter I1 is coupled to the input terminal N2 of the logic conversion circuit LC1. The output terminal X of the logic gate G1 is coupled to the output terminal N3 of the logic conversion circuit LC1.

[0045] The input terminal C of the logic gate G2 is coupled to the first terminal of the inverter I2. The second terminal of the inverter I2 is coupled to the input terminal N1 of the logic conversion circuit LC1. The input terminal D of the logic gate G2 is coupled to the input terminal N2 of the logic conversion circuit LC1. The output terminal Y of the logic gate G2 is coupled to the output terminal N4 of the logic conversion circuit LC1. The truth table of the logic conversion circuit LC1 is listed as follows.

[0046] Table 1.

[0047]

[0048] Figure 4 FIG. 1 is a signal timing diagram of data strobe signals DQS1 to DQS4 according to some embodiments of the present invention. The signal timing diagram includes a standby phase T1, a preamble phase T2 and a data input phase T3.

[0049] See also Figure 3 and Figure 4 , the data strobe signal DQS1 and the data strobe signal DQS2 are both erroneously at the same voltage level (eg, a low level L) in the standby stage T1.

[0050] In the standby stage T1, the data strobe signal DQS1 and the data strobe signal DQS2 are both at a low level L. The logic conversion circuit LC1 is used to convert the first data strobe signal DQS1 (e.g., a low level L) and the second data strobe signal DQS2 (e.g., a low level L) into a third data strobe signal DQS3 (e.g., a high level H) and a fourth data strobe signal DQS4 (e.g., a low level L). In the standby stage T1 before the leading stage T2, the third data strobe signal DQS3 and the fourth data strobe signal DQS4 will comply with JEDEC regulations.

[0051] In the preamble stage T2 and the data input stage T3, the first data strobe signal DQS1 and the second data strobe signal DQS2 are both switched between the high level H and the low level L. The logic conversion circuit LC1 is used to transfer the first data strobe signal DQS1 and the second data strobe signal DQS2 into the third data strobe signal DQS3 and the fourth data strobe signal DQS4, so that the logic conversion circuit LC1 does not affect the original operation of the preamble stage T2 and the data input stage T3.

[0052] However, the standby stage T1 before the leading stage T2 of the present embodiment is not limited to the voltage level of each of the first data strobe signal DQS1 and the second data strobe signal DQS2 being at the low level L. The voltage level of the data strobe signal DQS1 and the data strobe signal DQS2 may be at the high level H, which will be discussed in the following paragraphs.

[0053] Figure 5 FIG. 1 is a signal timing diagram of data strobe signals DQS1 to DQS4 according to some embodiments of the present invention. The signal timing diagram includes a standby phase T1, a preamble phase T2 and a data input phase T3.

[0054] Please refer to Figure 3 and Figure 5 , the data strobe signal DQS1 and the data strobe signal DQS2 are both erroneously at the same voltage level (eg, high level H) in the standby stage T1.

[0055] In the standby stage T1, the data strobe signal DQS1 and the data strobe signal DQS2 are both at a high level H. The logic conversion circuit LC1 is used to convert the first data strobe signal DQS1 (e.g., a high level H) and the second data strobe signal DQS2 (e.g., a high level H) into a third data strobe signal DQS3 (e.g., a high level H) and a fourth data strobe signal DQS4 (e.g., a low level L). In the standby stage T1 before the leading stage T2, the third data strobe signal DQS3 and the fourth data strobe signal DQS4 will comply with JEDEC regulations.

[0056] In the preamble stage T2 and the data input stage T3, the first data strobe signal DQS1 and the second data strobe signal DQS2 are both switched between the high level H and the low level L. The logic conversion circuit LC1 is used to transfer the first data strobe signal DQS1 and the second data strobe signal DQS2 into the third data strobe signal DQS3 and the fourth data strobe signal DQS4, so that the logic conversion circuit LC1 does not affect the original operation of the preamble stage T2 and the data input stage T3.

[0057] Figure 6 The logic conversion circuit LC2 shown in some embodiments of the present invention corresponds to Figure 2FIG. 1 is a circuit block diagram of a logic conversion circuit LC of a receiver 121. FIG.

[0058] The logic conversion circuit LC2 includes an input terminal N1, an input terminal N2, an output terminal N3 and an output terminal N4. The input terminal N1 is used to receive a data selection signal DQS1. The input terminal N2 is used to receive a data selection signal DQS2. The output terminal N3 is used to output a data selection signal DQS3. The output terminal N4 is used to output a data selection signal DQS4.

[0059] The logic conversion circuit LC2 further includes an inverter I3, an inverter I4, a logic gate G3, and a logic gate G4. Each of the inverter I1 and the inverter I2 includes a first terminal and a second terminal. The logic gate G3 includes an input terminal A, an input terminal B, and an output terminal X. The logic gate G4 includes an input terminal C, an input terminal D, and an output terminal Y. In some embodiments, the logic gate G3 includes a NAND gate. The logic gate G4 includes a NOR gate.

[0060] In some embodiments, an input terminal A of the logic gate G3 is coupled to a first terminal of an inverter I3. A second terminal of the inverter I3 is coupled to an input terminal N1 of the logic conversion circuit LC2. An input terminal B of the logic gate G3 is coupled to an input terminal N2 of the logic conversion circuit LC2. An output terminal X of the logic gate G3 is coupled to an output terminal N3 of the logic conversion circuit LC2.

[0061] The input terminal C of the logic gate G4 is coupled to the input terminal N1 of the logic conversion circuit LC2. The input terminal D of the logic gate G4 is coupled to the first terminal of the inverter I4. The second terminal of the inverter I4 is coupled to the input terminal N2 of the logic conversion circuit LC2. The output terminal Y of the logic gate G4 is coupled to the output terminal N4 of the logic conversion circuit LC2. The operation of the logic conversion circuit LC2 is similar to the operation of the logic conversion circuit LC1. The truth table of the logic conversion circuit LC2 is similar to Table 1 of the logic conversion circuit LC1.

[0062] Figure 7 The logic conversion circuit LC3 shown in some embodiments of the present invention corresponds to Figure 2 FIG. 1 is a circuit block diagram of a logic conversion circuit LC of a receiver 121. FIG. Figure 7 The logic conversion circuit LC3 and Figure 3 There are multiple differences between the logic conversion circuit LC1 of FIG. 1 and FIG. 2 . The first difference is that the logic conversion circuit LC3 further includes an inverter I3. The second difference is that the logic gate G2 further includes an input terminal E. The third difference is that the inverter I3 is coupled to the input terminal E of the logic gate G2 and the output terminal X of the logic gate G1. Figure 7 The remaining circuit structures of the embodiment are similar to Figure 3The circuit structure of the logic conversion circuit LC3 is not described in detail here. The operation of the logic conversion circuit LC3 is similar to the operation of the logic conversion circuit LC1. The truth table of the logic conversion circuit LC3 is similar to the truth table 1 of the logic conversion circuit LC1.

[0063] Figure 8 The logic conversion circuit LC4 shown in some embodiments of the present invention corresponds to Figure 2 FIG. 1 is a circuit block diagram of a logic conversion circuit LC of a receiver 121. FIG.

[0064] Figure 8 The logic conversion circuit LC4 and Figure 6 There are multiple differences between the logic conversion circuit LC2 of FIG. 1 and FIG. 2 . The first difference is that the logic gate G4 further includes an input terminal E. The second difference is that the input terminal E of the logic gate G4 is coupled to the output terminal X of the logic gate G3. Figure 8 The remaining circuit structures of the embodiment are similar to Figure 6 The circuit structure of the logic conversion circuit LC4 is not described in detail here. The operation of the logic conversion circuit LC4 is similar to the operation of the logic conversion circuit LC1. The truth table of the logic conversion circuit LC4 is similar to the truth table 1 of the logic conversion circuit LC1.

[0065] In some embodiments, the Boolean algebra of each logic conversion circuit LC1 to logic conversion circuit LC4 is listed as follows according to Table 1.

[0066]

[0067] According to the aforementioned embodiments, the present invention provides a memory system and a receiver for converting data strobe signals of the same voltage level into data strobe signals of different voltage levels specified by JEDEC, so that the memory chip or memory circuit operates normally.

[0068] Although the present invention is disclosed in detail with reference to the embodiments above, the present invention does not exclude other feasible implementations. Therefore, the protection scope of the present invention shall be determined by the appended claims, rather than being limited by the aforementioned embodiments.

[0069] For those skilled in the art, various changes and modifications can be made to the present invention without departing from the spirit and scope of the present invention. Based on the above embodiments, all changes and modifications made to the present invention are also included in the protection scope of the present invention.

[0070]

Explanation of symbols

[0071] 100: Memory System

[0072] 110: Controller

[0073] 120: Memory circuit

[0074] 121: Receiver

[0075] 122: Control circuit

[0076] CMD:Signal

[0077] D1-D15: Data bus

[0078] DA: amplifier

[0079] LC, LC1~LC4: logic conversion circuit

[0080] DQS1~DQS4: data selection signal

[0081] N1, N2, A, B, C, D, E: Input

[0082] N3, N4, X, Y: Output terminal

[0083] G1~G4: Logic gate

[0084] I1~I4:Inverter

[0085] H: High level

[0086] L: Low level

[0087] T1: Standby stage

[0088] T2: Leading stage

[0089] T3: Data input stage.

Claims

1. A memory system, characterized in that: Include: A controller, configured to output a first data strobe signal and a second data strobe signal; and A memory circuit is coupled to the controller and is used to receive the first data strobe signal and the second data strobe signal, wherein the memory circuit includes a receiver, wherein the receiver includes: A logic conversion circuit is coupled to the controller, wherein when the first data selection signal and the second data selection signal are at the same voltage level, the logic conversion circuit is used to convert the first data selection signal and the second data selection signal into a third data selection signal and a fourth data selection signal, wherein the third data selection signal and the fourth data selection signal converted by the logic conversion circuit include different voltage levels, wherein when the first data selection signal and the second data selection signal are at different voltage levels, the logic conversion circuit is used to transmit the first data selection signal as the third data selection signal, and to transmit the second data selection signal as the fourth data selection signal.

2. The memory system according to claim 1, wherein: The receiver also contains: The amplifier is coupled to the logic conversion circuit and is used for receiving and amplifying the first data strobe signal and the second data strobe signal.

3. The memory system according to claim 2, wherein: The logic conversion circuit comprises: A first input terminal, used for receiving the first data strobe signal; A second input terminal, used for receiving the second data strobe signal; A first output terminal, used for outputting the third data strobe signal; A second output terminal, used for outputting the fourth data strobe signal; The first inverter comprises: a first end; and A second terminal coupled to the second input terminal of the logic conversion circuit; and The second inverter comprises: a first end; and The second end is coupled to the first input end of the logic conversion circuit.

4. The memory system according to claim 3, characterized in that: The logic conversion circuit also includes: The first logic gate comprises: A first input terminal coupled to the first input terminal of the logic conversion circuit; A second input terminal coupled to the first terminal of the first inverter; as well as An output terminal coupled to the first output terminal of the logic conversion circuit; as well as The second logic gate comprises: A first input terminal coupled to the first terminal of the second inverter; A second input terminal coupled to the second input terminal of the logic conversion circuit; as well as The output terminal is coupled to the second output terminal of the logic conversion circuit.

5. The memory system according to claim 4, characterized in that: The second logic gate comprises a third input terminal, wherein the logic conversion circuit further comprises: The third inverter comprises: A first terminal coupled to the third input terminal; and The second end is coupled to the output end of the first logic gate.

6. The memory system according to claim 2, wherein: The logic conversion circuit comprises: A first input terminal, used for receiving the first data strobe signal; A second input terminal, used for receiving the second data strobe signal; A first output terminal, used for outputting the third data strobe signal; A second output terminal, used for outputting the fourth data strobe signal; The first inverter comprises: a first end; and A second terminal coupled to the first input terminal of the logic conversion circuit; and The second inverter comprises: a first end; and The second end is coupled to the second input end of the logic conversion circuit.

7. The memory system according to claim 5, characterized in that: The logic conversion circuit also includes: The first logic gate comprises: A first input terminal coupled to the first terminal of the first inverter; A second input terminal coupled to the second input terminal of the logic conversion circuit; as well as An output terminal coupled to the first output terminal of the logic conversion circuit; as well as The second logic gate comprises: A first input terminal coupled to the first input terminal of the logic conversion circuit; A second input terminal coupled to the first terminal of the second inverter; as well as The output terminal is coupled to the second output terminal of the logic conversion circuit.

8. The memory system according to claim 7, characterized in that: The second logic gate further includes a third input terminal, wherein the third input terminal of the second logic gate is coupled to the output terminal of the first logic gate.

9. A receiver, characterized in that: Include: an amplifier for receiving and amplifying a second data strobe signal from the first data strobe signal of the controller; and A logic conversion circuit is coupled to the amplifier, wherein when the first data selection signal and the second data selection signal are at the same voltage level, the logic conversion circuit is used to convert the first data selection signal and the second data selection signal into a third data selection signal and a fourth data selection signal, wherein the third data selection signal and the fourth data selection signal converted by the logic conversion circuit include different voltage levels, wherein when the first data selection signal and the second data selection signal are at different voltage levels, the logic conversion circuit is used to transmit the first data selection signal as the third data selection signal, and to transmit the second data selection signal as the fourth data selection signal.

10. The receiver according to claim 9, characterized in that The logic conversion circuit comprises: A first input terminal, used for receiving the first data strobe signal; A second input terminal, used for receiving the second data strobe signal; A first output terminal, used for outputting the third data strobe signal; A second output terminal, used for outputting the fourth data strobe signal; The first inverter comprises: a first end; and A second terminal coupled to the second input terminal of the logic conversion circuit; and The second inverter comprises: a first end; and The second end is coupled to the first input end of the logic conversion circuit.

11. The receiver according to claim 10, characterized in that The logic conversion circuit also includes: The first logic gate comprises: A first input terminal coupled to the first input terminal of the logic conversion circuit; A second input terminal coupled to the first terminal of the first inverter; as well as An output terminal coupled to the first output terminal of the logic conversion circuit; as well as The second logic gate comprises: A first input terminal coupled to the first terminal of the second inverter; A second input terminal coupled to the second input terminal of the logic conversion circuit; as well as The output terminal is coupled to the second output terminal of the logic conversion circuit.

12. The receiver according to claim 11, characterized in that The second logic gate further comprises a third input terminal, wherein the logic conversion circuit further comprises: The third inverter comprises: A first terminal coupled to the third input terminal; and The second end is coupled to the output end of the first logic gate.

13. The receiver according to claim 9, characterized in that The logic conversion circuit comprises: A first input terminal, used for receiving the first data strobe signal; A second input terminal, used for receiving the second data strobe signal; A first output terminal, used for outputting the third data strobe signal; A second output terminal, used for outputting the fourth data strobe signal; The first inverter comprises: a first end; and A second terminal coupled to the first input terminal of the logic conversion circuit; and The second inverter comprises: a first end; and The second end is coupled to the second input end of the logic conversion circuit.

14. The receiver according to claim 13, characterized in that The logic conversion circuit also includes: The first logic gate comprises: A first input terminal coupled to the first terminal of the first inverter; A second input terminal coupled to the second input terminal of the logic conversion circuit; as well as An output terminal coupled to the first output terminal of the logic conversion circuit; as well as The second logic gate comprises: A first input terminal coupled to the first input terminal of the logic conversion circuit; A second input terminal coupled to the first terminal of the second inverter; as well as The output terminal is coupled to the second output terminal of the logic conversion circuit.

15. The receiver according to claim 14, characterized in that The second logic gate further includes a third input terminal, wherein the third input terminal of the second logic gate is coupled to the output terminal of the first logic gate.

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