Power-on detection circuit and power-on detection method

Abstract

This invention provides a power-on detection circuit, characterized by comprising: a power detection unit, which receives an external power signal from an external power source and receives a high-voltage signal (higher than the external power signal) from an internal power source of the chip, detects the high-voltage signal, and obtains a high-voltage detection signal with the same voltage as the external power signal; a delay unit, which delays the high-voltage detection signal input from the power detection unit for a predetermined time to obtain a delayed voltage detection signal; and a latching unit, which receives the external power detection signal from the external power source, receives the delayed voltage detection signal from the delay unit, latches the delayed voltage detection signal, and outputs a final detection signal.

Description

Technical Field

[0001] This invention relates to the field of circuit testing, and more particularly to a power-on detection circuit and a power-on detection method. Background Technology

[0002] Powering on a DRAM is a crucial step in its workflow. Only when the chip's internal power supply is ready can it enter normal operation or other test states, and an initialization process can be used to establish the necessary power supply within the DRAM chip. This circuitry contains output signals for power detection (internal signals from the power-on module indicating initialization completion or power readiness). Therefore, the power-on detection signal should remain stable during the power-on process. However, during its boost process, the internal power supply may fluctuate due to unexpected noise or problems, resulting in an unstable power-on detection signal.

[0003] Some power-on detection signals are used to enable level shifters or latches. During initialization, the inputs of many circuit modules are in an unknown state. Instability of these power-on detection signals can also make the output state of level shifters or latches unknown. This may cause the next stage of the circuit to capture some incorrect logic and incorrect state.

[0004] If the enable state is locked and kept stable when the power-on detection signal first reaches the target value, the state of other related circuits during the power-on process can be determined earlier and more stably. Summary of the Invention

[0005] The technical problem that the invention aims to solve

[0006] The purpose of this invention is to provide a power-on detection circuit and a power-on detection method. This power-on detection circuit and method can filter out glitches in the input signal under certain unexpected circumstances, and maintain the output state unchanged when the internal power signal reaches a specified value and tends to a stable state, thereby preventing the final power detection signal from experiencing a brief and unexpected drop.

[0007] Technical solutions to solve technical problems

[0008] According to one embodiment of the present invention, a power-on detection circuit is provided, comprising: a power detection unit, wherein the power detection unit receives an external power signal from an external power source and receives a high voltage signal with a voltage higher than the external power signal from an internal power source of the chip, detects the high voltage signal, and obtains a high voltage detection signal with the same voltage as the external power signal; a delay unit, wherein the delay unit delays the high voltage detection signal input from the power detection unit for a predetermined time to obtain a delayed voltage detection signal; and a latching unit, wherein the latching unit receives the external power detection signal from the external power source, receives the delayed voltage detection signal from the delay unit, latches the delayed voltage detection signal, and outputs a final detection signal.

[0009] Further, the power detection unit includes: a first transistor; a second transistor, the gate of the second transistor being connected to the gate of the first transistor to form a first connection point; a pull-down unit, the pull-down unit being used to pull down the first connection point to turn on the first transistor and the second transistor when the external power signal is powered on and reaches a predetermined external power detection threshold, and the external power detection signal becomes high, so that the external power signal is output from the second connection point connected to the drain of the pull-down unit and the second transistor via the second transistor; a pull-up unit, the pull-up unit being used to pull up the first connection point to turn off the first switching element and the second switching element when the external power signal is powered on and reaches a predetermined external power detection threshold, and the external power detection signal becomes high, and the high voltage signal is enabled to start rising and is input to the pull-up unit and reaches above the predetermined detection threshold; and an inverter, the inverter being used to invert the signal at the second connection point.

[0010] Furthermore, when the high voltage signal rises above the detection threshold, the first connection point is pulled up by the pull-up unit, causing the second transistor to turn off, and the second connection point is pulled down to a low level by the pull-down unit, thereby making the high voltage detection signal high.

[0011] Furthermore, when the high voltage signal is less than the detection threshold, the pull-up unit is turned off, and the first connection point is pulled down through the pull-down unit. The second connection point becomes a high level of the external power supply signal transmitted by the second transistor, thereby making the high voltage detection signal a low level.

[0012] Furthermore, when interference causes the high-voltage detection signal to be erroneously triggered to a high level before the specified time during the power-on process of the high-voltage signal, the delay unit delays the specified time.

[0013] Furthermore, the specified time is the duration during which the high-voltage detection signal is erroneously triggered to a high level.

[0014] Furthermore, the specified time is set to 2ns to 4ns.

[0015] Furthermore, when the external power supply detection signal becomes high, the latch is enabled and activated.

[0016] When a high-level signal is received from the delay voltage detection signal from the delay unit, the final detection signal output by the latch unit becomes high, and the delay voltage detection signal is latched.

[0017] According to another embodiment of the present invention, a power-on detection method is provided, comprising: a power detection step, wherein the power detection step inputs an external power signal from an external power source and inputs a high voltage signal with a voltage higher than that of the external power signal from an internal power source of the chip, and detects the high voltage signal to obtain a high voltage detection signal with the same voltage as the external power signal; a delay step, wherein the delay step delays the input high voltage detection signal for a predetermined time to obtain a delayed voltage detection signal; and a latching step, wherein the latching step inputs the external power detection signal and the delayed voltage detection signal obtained in the delay step, latches the delayed voltage detection signal, and outputs a final detection signal.

[0018] Furthermore, when the external power signal reaches the specified external power detection threshold, and the external power detection signal becomes high, the first connection point is pulled down by the pull-down unit to turn on the first transistor and the second transistor. Thus, the external power signal is output from the second connection point, which is connected to the drain of the second transistor via the pull-down unit. When the external power signal reaches the specified external power detection threshold, and the external power detection signal becomes high, when the high voltage signal is enabled and begins to rise and is input to the pull-up unit and reaches the specified detection threshold, the first connection point is pulled up by the pull-up unit to turn off the first transistor and the second transistor. The signal at the second connection point is inverted by the inverter.

[0019] Furthermore, when the high voltage signal rises above the detection threshold, the first connection point is pulled up by the pull-up unit, causing the second transistor to turn off, and the second connection point is pulled down to a low level by the pull-down unit, thereby making the high voltage detection signal high.

[0020] Furthermore, when the high voltage signal is less than the detection threshold, the pull-up unit is turned off, and the first connection point is pulled down through the pull-down unit. The second connection point becomes a high level of the external power supply signal transmitted by the second transistor, thereby making the high voltage detection signal a low level.

[0021] Furthermore, if interference causes the high-voltage detection signal to be erroneously triggered to a high level before the specified time during the power-on process of the high-voltage signal, the specified time is delayed.

[0022] Furthermore, the specified time is the duration during which the high-voltage detection signal is erroneously triggered to a high level. Further, the specified time is set to 2ns to 4ns.

[0023] Furthermore, when the external power supply detection signal becomes high, the final detection signal becomes high when the high-level signal of the delayed voltage detection signal is received, and the delayed voltage detection signal is latched.

[0024] Invention Effects

[0025] According to the present invention, a power-on detection circuit and a power-on detection method can be provided, which can filter out glitches in the input signal under certain unexpected circumstances, and maintain the output state unchanged when the internal power signal is detected to reach a specified value and tend to be stable, thereby preventing the final power detection signal from experiencing a brief unexpected drop. Attached Figure Description

[0026] The invention can be better understood by describing exemplary embodiments of the invention in conjunction with the accompanying drawings, in which:

[0027] Labeling Explanation: 100 Power-on Detection Circuit, 1 Power Detection Unit, 2 Delay Unit, 3 Latch Unit, 4 External Power Detection Unit, Q1 First Transistor, Q2 Second Transistor, Q3 Third Transistor, Q4 Fourth Transistor, Q5 Fifth Transistor, Q6 Sixth Transistor, 11 Pull-up Unit, 12 Pull-down Unit, 13, 21, 22, 23, 31 Inverter, C1, C2 Capacitor, RS1 First NOR Gate, RS2 Second NOR Gate, VDDi External Power Signal, VSi Ground, High_power High Voltage Signal, High_power_detect High Voltage Detection Signal, Delay_power_detect Delay Voltage Detection Signal, External_power_detect External Power Detection Signal, Final detect Final Detection Signal, External_power_detect_point External Power Detection Threshold, High_power_detect_point Detection Threshold, P1 First Connection Point, P2 Second Connection Point, P3 Third Connection Point, P4 Fourth Connection Point.

[0028] Figure 1 This is a structural block diagram of the power-on detection circuit involved in this invention.

[0029] Figure 2 This is a structural diagram of the power detection section in the power-on detection circuit involved in the present invention.

[0030] Figure 3 This is a structural diagram of the delay section in the power-on detection circuit involved in this invention.

[0031] Figure 4 This is a structural diagram of the latch section in the power-on detection circuit involved in this invention.

[0032] Figure 5 This is a waveform diagram of the power-on process of the relevant signals involved in this invention.

[0033] Figure 6 This is a simplified flowchart of the power-on detection method involved in this invention. Detailed Implementation

[0034] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0035] In the description of this disclosure, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," etc., indicating orientation or positional relationships are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The directional terms appearing in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of this disclosure. In the description of this disclosure, it should also be noted that, unless otherwise explicitly specified and limited, the terms "connected," "linked," "relative," "interlocking," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0036] In this document, the term "implementation" means that a particular feature, structure, or characteristic described in connection with an implementation may be included in at least one implementation of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same implementation, nor is it a separate or alternative implementation mutually exclusive with other implementations. It will be explicitly and implicitly understood by those skilled in the art that the implementations described herein can be combined with other implementations.

[0037] The power-on detection circuit 100 and method involved in the present invention will now be described with reference to the accompanying drawings.

[0038] Figure 1 This is a structural block diagram of the power-on detection circuit 100 involved in this invention. (See diagram below.) Figure 1 As shown, the power-on detection circuit 100 includes a power detection unit 1, a delay unit 2, and a latch unit 3.

[0039] like Figure 1As shown, the power detection unit 1 receives an external power signal VDDi from an external power source and a high-voltage signal (High_power) that is higher than the external power signal VDDi from the internal power source of the Dr am chip. The power detection unit 1 detects the input high-voltage signal and obtains a high-voltage detection signal (High_power_detect) that is the same voltage as the external power signal VDDi. Furthermore, the delay unit 2 is connected to the power detection unit 1 and delays the high-voltage detection signal input from the power detection unit 1 for a predetermined time to obtain a delayed voltage detection signal (delay_power_detect). The latch unit 3 receives the external power detection signal (External_power_detect) from an external power source and the delayed voltage detection signal from the delay unit 2, latches the delayed voltage detection signal, and outputs a final detection signal (Final detect). This final detection signal is the power-on detection signal of the power-on detection circuit 100. Additionally, the external power detection signal is obtained by the external power detection unit 4 detecting the external power signal VDDi.

[0040] The above structure filters out glitches that may be caused by erroneous triggering, and also locks the output state of the power-on detection circuit 100, thereby preventing the logic of the final output detection signal from being reversed when the internal power supply voltage is unstable or drops. Furthermore, it provides a stable and noise-resistant output signal for other circuits using this power-on detection signal.

[0041] The following is a reference to the appendix. Figure 2-4 The circuit structures of the power detection unit 1, the delay unit 2, and the latch unit 3 will be described separately. Figure 2 This is a structural diagram of the power detection unit 1 in the power-on detection circuit 100 according to the present invention. Figure 3 This is a structural diagram of the delay section 2 in the power-on detection circuit 100 involved in the present invention. Figure 4 This is a structural diagram of the latching section 3 in the power-on detection circuit 100 involved in the present invention.

[0042] like Figure 2 As shown, the power detection unit 1 mainly includes a pull-up unit 11, a first transistor Q1, a second transistor Q2, a pull-down unit 12, and an inverter 13.

[0043] The gate of the first transistor Q1 is connected to the gate of the second transistor Q2 to form a first connection point P1. This first connection point P1 is connected to the pull-up control output terminal up_Con of the pull-up unit 11 described below. In addition, the source of each transistor receives an external power supply signal VDDi from an external power supply. Here, the first and second transistors Q1 and Q2 are P-type transistors, but are not limited to this.

[0044] The pull-down unit 12 includes a pull-down input terminal down_VIN 1 for inputting an external power supply signal VDDi, a ground terminal GND (VSi) for grounding, a pull-down control terminal down_Con connected to the drain of the first transistor Q1 via a third connection point P3, and a pull-down output terminal down_OUT connected to the drain of the second transistor Q2 via a second connection point P2. Furthermore, the first connection point P1 is connected to the third connection point P3. The pull-down unit 12 is used to pull down the first connection point P1 through the pull-down control terminal down_Con when the external power signal VDDi is powered on and reaches the specified external power detection threshold (External_power_detect_point). When the external power detection signal obtained by the external power detection unit 4 detects the external power signal VDDi becomes high, the voltage at the first connection point P1 is lowered, thereby making the voltage input to the gate of each transistor low, so that the first transistor Q1 and the second transistor Q2 are turned on. The external power signal VDDi is output from the second connection point P2, which is connected to the drain of the second transistor Q2, through the pull-down output terminal down_OUT of the pull-down unit 12 to the inverter 13 described below.

[0045] The pull-up unit 11 includes a first pull-up input terminal up_VIN1 for inputting the external power signal VDDi, a second pull-up input terminal up_VIN2 for inputting a high-voltage signal (High_power) from the chip's internal power supply that is higher than the external power signal VDDi, and a pull-up output control terminal up_Con. When the external power signal VDDi is powered on and reaches a predetermined external power detection threshold (External_power_detect_point), and when the external power detection signal obtained by detecting the external power signal VDDi through the external power detection unit 4 becomes high, when the high-voltage signal is enabled and starts to rise and is input to the pull-up unit 11 and reaches or exceeds the predetermined detection threshold (High_power_detect_point) of the pull-up unit 11, the pull-up output control terminal up_Con pulls up the first connection point P1, that is, makes the voltage at the first connection point P1 high, thereby making the voltage input to the gate of each transistor high, thus turning off the first transistor Q1 and the second transistor Q2.

[0046] Furthermore, the power detection unit 1 also includes an inverter 13, which inverts the input signal output from the drain of the second transistor Q2. In other words, the inverter 13 inverts the signal at the second connection point P2.

[0047] The working principle of the power detection unit 1 will be explained below. Specifically, when the external power signal is powered on and reaches the specified external power detection threshold (External_power_detect_point), and the external power detection signal (External_power_detect) becomes high, the high voltage signal (High_power) is enabled and begins to rise.

[0048] During the rise of the high-voltage signal, interference may occur, causing glitches. These glitches can lead to the output high-voltage detection signal being erroneously triggered. Furthermore, when the circuit controlled by the high-voltage detection signal is enabled, the load on the high-voltage power supply increases rapidly, causing the high-voltage signal to drop below the detection threshold specified by the pull-up unit 11. The pull-up function of the pull-up unit 11 is then disabled, and the potential of the first connection point P1 is pulled down by the pull-down unit 12 to become low. The second connection point P2 becomes high due to the external power supply signal VDDi transmitted by the second transistor Q2, which is then inverted by the inverter 13, ultimately resulting in a low-level output high-voltage detection signal.

[0049] After the circuit stabilizes for a short period of time, the current consumption of the high-voltage power supply by the circuit controlled by the high-voltage detection signal gradually decreases and stabilizes. When the high-voltage signal returns to its normal ramp-up state and reaches or exceeds the detection threshold specified by the pull-up unit 11, the potential of the first connection point P1 is pulled up to the high level again by the pull-up unit 11, causing the second transistor to be cut off. The potential of the second connection point P2 is pulled down to the low level by the pull-down unit 12, and inverted by the inverter 13. Finally, the high-voltage detection signal output becomes high level.

[0050] like Figure 3 As shown, the delay section 2 includes: third transistors Q3 to sixth transistors Q6, capacitors C1 and C2, and inverters 21 to 23. It is assumed that third transistor Q3 and fourth transistor Q4 are P-type transistors, and fifth transistor Q5 and sixth transistor Q6 are N-type transistors, but this is not a limitation. Specifically, third transistors Q3 to sixth transistor Q6 are connected in series, meaning the source of third transistor Q3 receives the external power signal VDDi from an external power source, the source of fourth transistor Q4 is connected to the drain of third transistor Q3, the source of fifth transistor Q5 is connected to the drain of fourth transistor Q4, the source of sixth transistor Q6 is connected to the drain of fifth transistor Q5, and the drain of sixth transistor Q6 is grounded. Furthermore, each transistor Q3 to Q6 has an inverter 21 connected to its gate, receiving a high-voltage detection signal from the power detection section 1. The fourth connection point P4, where the drain of fourth transistor Q4 connects to the source of fifth transistor Q5, is connected to two inverters 22 and 23 in sequence to output a delayed voltage detection signal (Delay_power_detect).

[0051] The delay unit 2 also includes capacitors C1 and C2 connected to the fourth connection point P4. One end of capacitor C1 is connected to an external power supply signal, and the other end is connected to the fourth connection point P4. One end of capacitor C2 is grounded, and the other end is connected to the fourth connection point P4. Capacitors C1 and C2 are used to filter unwanted noise, etc.

[0052] The working principle of delay unit 2 will be explained. As mentioned above, during the rise of the high-voltage signal, interference may occur, resulting in glitches. These glitches can cause the output high-voltage detection signal to be erroneously triggered within a very short time. That is, when interference causes the high-voltage detection signal to become high for a very short time during the power-on process, delay unit 2 needs to perform a delay operation to prevent the high-voltage detection signal from being erroneously triggered. The delay time, i.e., the specified time, is generally the duration during which the high-voltage detection signal is erroneously triggered to a high level. This specified time can generally be set to 2ns to 4ns. In addition, the aforementioned very short time generally refers to less than or equal to this specified time. This can solve the fluctuations caused by "minor faults" during power-up.

[0053] like Figure 4 As shown, the latch unit 3 includes two NOR gates RS1 and RS2 whose input and output terminals are cross-coupled. Specifically, the input terminal RS1_VIN1 of NOR gate RS1 receives a delayed voltage detection signal from the delay unit 2, and the other input terminal RS1_VIN2 of NOR gate RS1 is connected to the output terminal RS2_VOUT of NOR gate RS2. Furthermore, the input terminal RS2_VIN1 of NOR gate RS2 is connected to the output terminal RS1_VOUT of NOR gate RS1, and the other input terminal RS2_VIN2 of NOR gate RS2 receives an external power supply detection signal from an external source. The output terminal of NOR gate RS2 is also connected to an inverter 31, thereby outputting a final detection signal.

[0054] When the external power supply detection signal goes high, the latch unit 3 is enabled. Furthermore, upon receiving a high-level signal from the delay voltage detection signal from the delay unit 2, the output of the latch unit 3, i.e., the final detection signal, goes high, thereby locking the state of the delay voltage detection signal. Thereafter, regardless of any changes in the input to the latch unit 3, its output will not change.

[0055] Furthermore, the external power supply detection signal input to the latch unit 3 is a signal obtained by the external power supply detection unit 4 detecting the external power supply signal VDDi. For example... Figure 1 and Figure 4 As shown, the input terminal RS2_VIN2 of the NOR gate RS2 of the latch unit 3 is connected to the external power supply detection unit 4.

[0056] Next, refer to Figure 5 The power-on process of the relevant signals is explained. Figure 5 This is a waveform diagram of the power-on process of the relevant signals involved in this invention. For example... Figure 5 As shown, from top to bottom, the waveforms of the external power signal (VDDi), high voltage signal (High_power), high voltage detection signal (High_power_detect), external power detection signal (External_power_detect), delayed voltage detection signal (Delay_power_detect), and final detection signal (Final detect) are displayed. Furthermore, Figure 5 The upper horizontal dashed line represents the external power detection threshold (External_power_detect_point), and the lower horizontal dashed line represents the detection threshold (High_power_detect_point).

[0057] In addition, t1 to t4 represent time. At time t1, the external power supply signal is powered on and reaches the external power supply detection threshold. The external power supply detection signal becomes high level, and the high voltage signal is enabled and begins to rise.

[0058] At time t2, the high-voltage signal is interfered with during its rise, causing glitches. These glitches cause the high-voltage detection signal output by the power supply detection unit 1 to be erroneously triggered within a very short time, such as... Figure 5 As shown, a glitch occurs in the high-voltage signal at t2, which causes the high-voltage detection signal to be erroneously triggered and become high-level. However, this erroneous fluctuation is generally very short, approximately between 2ns and 4ns. At this time, by setting the delay unit 2, this erroneous fluctuation can be filtered out.

[0059] At time t3, when the high-voltage signal rises to the detection threshold, the delay signal becomes high. Latch unit 3 receives the high-level signal sent from delay unit 2, and its output becomes high to lock the current state of the high-voltage detection signal, i.e., the high-level state. When the high-voltage signal rises above the detection threshold, the circuits enabled by the high-voltage detection signal begin to operate, increasing the load on the high-voltage power supply for a short time, causing the high-voltage signal to drop below the detection threshold. At this time, since the high-voltage signal is below the detection threshold, the high-voltage detection signal changes from high to low, and the delay voltage detection signal of delay unit 2 also changes from high to low. However, since the high-level state of the high-voltage detection signal is locked by latch unit 3, the final detection signal to be output will not change.

[0060] At time t4, the power load decreases, and the high-voltage signal gradually returns to its normal ramp-up state. At this point, the high-voltage signal has reached the detection threshold, causing the high-voltage detection signal to change from low to high, and the delayed voltage detection signal also changes from low to high. After receiving the delayed voltage detection signal, latch unit 3 outputs the final detection signal.

[0061] As described above, the structure of this invention can filter out glitches that may be caused by erroneous triggering and lock the output state, thereby preventing the signal logic of the power-on detection circuit 100 from being reversed when the power supply is unstable or drops. The improved circuit can provide a stable and noise-resistant output signal for other circuits that use the power-on detection signal.

[0062] Furthermore, compared to single-supply input detection circuits, dual-supply input detection circuits have the following characteristics: when the detected supply voltage is higher than the system voltage, the output is the system voltage value. When the high voltage signal reaches or exceeds the detection threshold, the output high voltage detection signal becomes high; conversely, when the high voltage signal is lower than the detection threshold, the output high voltage detection signal becomes low. In other words, as soon as the high voltage signal reaches or exceeds the detection threshold, the output high voltage detection signal immediately becomes high; as soon as the high voltage signal falls below the detection threshold, the output high voltage detection signal immediately becomes low. However, in a single-supply detection circuit, if the supply voltage signal exceeds the detection threshold, the output becomes high. If the supply voltage signal is then pulled down below the detection threshold, as long as the pulldown is not significant (e.g., less than 100mV), the output will remain high and will not become low.

[0063] The power-on detection method described below will be explained.

[0064] First, in the power detection step S1, an external power signal is input from an external power source, and a high voltage signal with a voltage higher than that of the external power signal is input from the internal power source of the chip. The input high voltage signal is detected to obtain a high voltage detection signal with the same voltage as the external power signal.

[0065] In delay step S2, the input high-voltage detection signal is delayed for a specified time to obtain a delayed voltage detection signal. In latching step S3, an external power supply detection signal is input, along with the delayed voltage detection signal obtained in delay step S2. The delayed voltage detection signal is latched, and the final detection signal is output.

[0066] Furthermore, in the aforementioned power detection step S1, when the external power signal reaches the specified external power detection threshold, and the external power detection signal becomes high, the first connection point P1 is pulled down by the pull-down unit 12 to turn on the first transistor Q1 and the second transistor Q2, so that the external power signal is output from the second connection point P2, which is connected to the drain of the second transistor Q2 via the second transistor Q2.

[0067] When the external power supply signal is powered on and reaches the specified external power supply detection threshold, the external power supply detection signal becomes high. When the high voltage signal is enabled and starts to rise and is input to the pull-up unit 11 and reaches above the specified detection threshold, the first connection point P1 is pulled up through the pull-up unit 11 to turn off the first transistor Q1 and the second transistor Q2.

[0068] In addition, the signal at the second connection point P2 is inverted by inverter 13.

[0069] Furthermore, when the high voltage signal rises above the specified detection threshold, the pull-up unit 11 pulls up the first connection point P1, causing the second transistor Q2 to turn off, and the pull-down unit 12 pulls down the second connection point P2 to a low level, thereby making the high voltage detection signal high. When the high voltage signal is below the detection threshold, the pull-up unit 11 turns off, the second connection point P2 becomes high due to the external power supply signal VDDi transmitted by the second transistor Q2, and the pull-down unit 12 pulls down the first connection point P1, thereby making the high voltage detection signal low.

[0070] Furthermore, in the aforementioned delay step 2, if interference causes the high-voltage detection signal to be erroneously triggered to a high level within a specified time during the high-voltage signal power-on process, a delay of the specified time is applied. This specified time is the duration during which the high-voltage detection signal is erroneously triggered to a high level. This specified time is set to 2ns to 4ns. By delaying the signal by the specified time, signal glitches with a width of 2-4ns can be filtered out.

[0071] Furthermore, in the latching step 3 above, when the external power supply detection signal becomes high, the final detection signal becomes high when the high-level signal of the delayed voltage detection signal is received, and the delayed voltage detection signal is latched.

[0072] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or aspects thereof) can be used in combination with each other. Furthermore, many modifications can be made to adapt particular conditions or materials to the teachings of the various embodiments of the invention without departing from the scope of the invention. While the dimensions and types of materials described herein are used to define parameters of the various embodiments of the invention, the embodiments are not intended to be restrictive but are exemplary. Many other embodiments will become apparent to those skilled in the art upon reading the above description. Therefore, the scope of the various embodiments of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A power-on detection circuit, characterized in that, include: The power detection unit receives an external power signal from an external power source and a high-voltage signal (higher than the external power signal) from the chip's internal power source. It then detects the high-voltage signal to obtain a high-voltage detection signal that is the same as the voltage of the external power signal. The delay unit delays the high voltage detection signal input from the power supply detection unit for a predetermined time to obtain a delayed voltage detection signal; as well as The latching unit receives an external power supply detection signal from the external power supply and a delay voltage detection signal from the delay unit. The latch is enabled based on the external power supply detection signal, then locks the current state of the high voltage detection signal based on the delayed voltage detection signal, and outputs the final detection signal.

2. The power-on detection circuit as described in claim 1, characterized in that, The power detection unit includes: First transistor; The second transistor has its gate connected to the gate of the first transistor to form a first connection point; A pull-down unit is used to pull down the first connection point to turn on the first transistor and the second transistor when the external power signal is powered on and reaches a specified external power detection threshold and the external power detection signal becomes high. The external power signal is then output from the second connection point, which is connected to the drain of the pull-down unit and the second transistor, via the second transistor. A pull-up unit, wherein when the external power signal is powered on and reaches a predetermined external power detection threshold, and the external power detection signal becomes high, when the high voltage signal is enabled, starts to rise, is input to the pull-up unit, and reaches or exceeds the predetermined detection threshold, the pull-up unit pulls up the first connection point to turn off the first transistor and the second transistor; and An inverter, used to invert the signal at the second connection point.

3. The power-on detection circuit as described in claim 2, characterized in that, When the high voltage signal rises above the detection threshold, the first connection point is pulled up by the pull-up unit, causing the second transistor to turn off. The pull-down unit pulls the second connection point down to a low level, thereby making the high voltage detection signal high.

4. The power-on detection circuit as described in claim 2, characterized in that, When the high voltage signal is less than the detection threshold, the pull-up unit is turned off. By pulling down the first connection point through the pull-down unit, the second connection point becomes a high level of the external power supply signal transmitted by the second transistor being turned on, thereby making the high voltage detection signal a low level.

5. The power-on detection circuit as described in claim 1, characterized in that, When interference causes the high-voltage detection signal to be erroneously triggered to a high level within a time period less than or equal to the specified time during the power-on process of the high-voltage signal, the delay unit delays the specified time.

6. The power-on detection circuit as described in claim 5, characterized in that, The specified time is the duration during which the high-voltage detection signal is erroneously triggered to a high level.

7. The power-on detection circuit as described in claim 6, characterized in that, The specified time is set to 2ns to 4ns.

8. The power-on detection circuit as described in claim 1, characterized in that, When the external power supply detection signal goes high, the latch is enabled and activated. When a high-level signal is received from the delay voltage detection signal from the delay unit, the final detection signal output by the latch unit becomes high, and the delay voltage detection signal is latched.

9. A power-on detection method, characterized in that, include: The power detection step involves inputting an external power signal from an external power source and inputting a high-voltage signal from the chip's internal power source that is higher than the external power signal. The high-voltage signal is then detected to obtain a high-voltage detection signal that is the same as the voltage of the external power signal. A delay step is performed to delay the input high-voltage detection signal by a specified time to obtain a delayed voltage detection signal; as well as The latching step involves inputting an external power supply detection signal and the delay voltage detection signal obtained in the delay step. In the latching step, the system is enabled based on the external power supply detection signal, then the current state of the high voltage detection signal is locked based on the delayed voltage detection signal, and the final detection signal is output.

10. The power-on detection method as described in claim 9, characterized in that, When the external power signal reaches the specified external power detection threshold, and the external power detection signal becomes high, the first connection point is pulled down by the pull-down unit to turn on the first and second transistors. Thus, the external power signal is output via the second transistor from the second connection point where the pull-down unit and the drain of the second transistor are connected. When the external power supply signal reaches the specified external power supply detection threshold, and the external power supply detection signal becomes high, if the high voltage signal is enabled, starts to rise, is input to the pull-up unit, and reaches or exceeds the specified detection threshold, the pull-up unit pulls up the first connection point to turn off the first transistor and the second transistor. The signal at the second connection point is inverted by an inverter.

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