Semiconductor device metal ohmic contact preparation method and semiconductor structure
By using the stress material layer as a barrier layer in self-aligned silicide growth, combined with stress memory technology, the problems of complex process and low efficiency in the prior art are solved, and efficient preparation and performance improvement of semiconductor devices are achieved.
Patent Information
- Application Number
- CN202510013653.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-04-11
AI Technical Summary
In the prior art, in the process of forming self-aligned silicides after stress memory technology, it is necessary to remove stress silicon nitride thin film and deposit additional silicide barrier layers, resulting in complex processes and low efficiency, affecting the rapid mass production of semiconductor devices.
The stress material layer is used as a barrier layer in self-aligned silicide growth, combined with stress memory technology, to avoid removing the stress material layer before patterning, and without the need for additional deposition of the barrier layer, simplifying the preparation process.
The preparation process of semiconductor structures is simplified, the preparation efficiency is improved, and the production cost is reduced. At the same time, the speed performance of semiconductor devices is improved through stress memory technology, and the contact resistance and delay are reduced.
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Figure CN119811990A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a metal ohmic contact of a semiconductor device and a semiconductor structure. Background Art
[0002] Salicide (Self-Aligned Silicide) can provide a gold-gold and gold-semiconductor ohmic contact between the contact structure and the silicon structure of the subsequent process, reducing contact resistance and delay. Salicide growth uses a self-aligned process. The common method is to first deposit a silicide barrier layer (Silicide Block, SAB), then open the area where silicide needs to grow by photolithography and etching, and then deposit NiPt nickel-platinum alloy and perform rapid annealing.
[0003] Stress memory technology (SMT) is used in advanced process technology to enhance the carrier mobility of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The common method is to first deposit silicon oxide and stressed silicon nitride films, then transfer the stress to the silicon substrate through spike annealing or laser annealing, and finally remove the stressed silicon nitride film by etching.
[0004] In the prior art, in the process of first implementing stress memory technology and then forming self-aligned silicide, it is necessary to remove the stress silicon nitride film of the stress memory technology and then deposit the silicide barrier layer. The preparation process is complicated and the preparation efficiency is low, which is not conducive to the rapid mass production of semiconductor devices.
[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0006] In response to the problems in the prior art, the purpose of the present application is to provide a method for preparing a metal ohmic contact of a semiconductor device and a semiconductor structure, combining stress memory technology with the barrier layer technology in the formation of self-aligned silicide, using a stress material layer as a barrier layer in the growth of self-aligned silicide, without the need for additional deposition of a barrier layer, thereby simplifying the preparation process of the semiconductor structure and improving the preparation efficiency of the semiconductor structure.
[0007] The present invention provides a method for preparing a metal ohmic contact of a semiconductor device, comprising the following steps:
[0008] providing a substrate;
[0009] After forming a stress material layer on one side of the substrate, an annealing treatment is performed;
[0010] Performing patterning to open the stress material layer in the target area;
[0011] A metal layer is deposited and annealed to allow the metal layer to react with the substrate to form metal silicide.
[0012] In some embodiments, forming a stress material layer on one side of the substrate comprises the following steps:
[0013] forming a first oxide layer on one side of the substrate;
[0014] A stress material layer is formed on a side of the first oxide layer away from the substrate.
[0015] In some embodiments, the stressed material layer is a stressed silicon nitride layer.
[0016] In some embodiments, before performing the patterning process to open the stress material layer in the target area, the following steps are also included:
[0017] A second oxide layer is formed on a side of the stress material layer away from the substrate.
[0018] In some embodiments, forming a second oxide layer on a side of the stress material layer facing away from the substrate comprises the following steps:
[0019] A second oxide layer is deposited on a side of the stress material layer away from the substrate, wherein the second oxide layer is a silicon dioxide layer.
[0020] In some embodiments, the patterning process to open the stress material layer in the target area includes the following steps:
[0021] A photolithography process is performed, and the stress material layer in the target area is opened by etching.
[0022] In some embodiments, the step of opening the stress material layer in the target area by etching comprises the following steps:
[0023] opening the second oxide layer and the photoresist layer in the target area by wet etching;
[0024] opening the stress material layer in the target area by wet etching;
[0025] The first oxide layer is opened in the target area by wet etching.
[0026] In some embodiments, the metal layer is a nickel-platinum alloy layer.
[0027] The embodiment of the present application also provides a semiconductor structure obtained by using the above-mentioned method for preparing the metal ohmic contact of the semiconductor device.
[0028] The method for preparing the metal ohmic contact of the semiconductor device and the semiconductor structure provided in this application have the following advantages:
[0029] By adopting the present application, the stress memory technology is combined with the barrier layer technology in the formation of self-aligned silicide, and the stress material layer is used as the barrier layer in the growth of self-aligned silicide. There is no need to remove the stress material layer before patterning, and there is no need to deposit an additional barrier layer, which simplifies the preparation process of the semiconductor structure and improves the preparation efficiency of the semiconductor structure. The driving current of the semiconductor device is increased by the stress memory technology, the speed performance of the semiconductor device is improved, and the contact resistance in the semiconductor device is reduced by forming a self-aligned silicide, and the delay is reduced, thereby improving the performance of the semiconductor device.
[0030] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0032] Figure 1 It is a flow chart of a method for preparing a metal ohmic contact of a semiconductor device according to an embodiment of the present application;
[0033] Figure 2 It is a schematic diagram of providing a substrate in a method for preparing a metal ohmic contact of a semiconductor device according to an embodiment of the present application;
[0034] Figure 3 It is a schematic diagram after forming a stress material layer in a method for preparing a metal ohmic contact of a semiconductor device according to an embodiment of the present application;
[0035] Figure 4 It is a schematic diagram after forming a second oxide layer in a method for preparing a metal ohmic contact of a semiconductor device according to an embodiment of the present application;
[0036] Figure 5 It is a schematic diagram of a method for preparing a metal ohmic contact of a semiconductor device in an embodiment of the present application after photolithography and etching. DETAILED DESCRIPTION
[0037] The example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. "Or" and "or" in the specification may both represent "and" or "or". Spatial relationship terms such as "on..." and the like can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented to be "under..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptions used herein are interpreted accordingly.
[0038] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.
[0039] In the existing process of first implementing stress memory technology and then forming self-aligned silicide, it is necessary to remove the stress silicon nitride film of the stress memory technology and then deposit the silicide barrier layer. The preparation process is complicated and the preparation efficiency is low, which is not conducive to the rapid mass production of semiconductor devices. Based on this, the present application aims to provide a method for preparing a metal ohmic contact of a semiconductor device and a semiconductor structure obtained by using the preparation method, using a stress material layer as a barrier layer in the growth of self-aligned silicide, without the need for additional deposition of a barrier layer, simplifying the preparation process of the semiconductor structure, improving the preparation efficiency of the semiconductor structure, and reducing the production cost.
[0040] like Figure 1 As shown, the present application provides a method for preparing a metal ohmic contact of a semiconductor device, comprising the following steps:
[0041] S100: providing a substrate;
[0042] The base includes a silicon substrate, in which a transistor structure (including a gate, a source, a drain, etc.) is formed, for example;
[0043] S200: After forming a stress material layer on one side of the substrate, performing annealing treatment;
[0044] The stress material layer can generate stress in the semiconductor device, and this stress can change the lattice structure of the semiconductor material, thereby affecting the mobility of carriers, thereby effectively improving the performance of the semiconductor device;
[0045] By performing annealing on the semiconductor structure deposited with the stress material layer, the stress of the stress material layer is transferred to the substrate, so that the stress can be effectively memorized; in this embodiment, the annealing may include laser annealing or spike annealing;
[0046] S300: performing patterning to open the stress material layer in the target area;
[0047] When patterning is performed, the stress material layer is used as a barrier layer; the target area is, for example, an active area (source, drain, etc.) of a semiconductor structure;
[0048] S400: depositing a metal layer, and performing annealing treatment to allow the metal layer to react with the substrate to form a metal silicide;
[0049] In this embodiment, the metal layer is a nickel-platinum alloy layer, but the present application is not limited thereto. The specific material of the metal layer can be selected according to the actual needs of the semiconductor device, and is not limited to the examples given here. The deposition of the metal layer is achieved, for example, by physical vapor deposition. The thickness of the metal layer can be selected according to the actual needs of the semiconductor device.
[0050] By adopting the present application, stress memory technology is combined with barrier layer technology in self-aligned silicide formation. Stress memory technology (SMT) is mainly used to improve the performance of semiconductor devices. Its basic principle is to introduce stress in the semiconductor manufacturing process and make the device remember this stress, thereby changing the band structure and carrier mobility of the semiconductor material. In the current semiconductor manufacturing process, as the size of semiconductor devices continues to shrink, stress memory technology can improve performance by improving carrier mobility without changing the basic size of the device. Self-aligned silicide (Salicide) is a technology used to reduce the metal-semiconductor contact resistance in semiconductor manufacturing. Its basic principle is to use photolithography and etching processes to pre-define the active area (source, drain, etc.) of semiconductor devices (such as transistors), and then deposit metal on the surface of the entire semiconductor structure. Through high-temperature annealing, the metal reacts with the silicon in the active area to form silicide. Since the reaction between metal and silicon is carried out in the pre-defined active area, the formation of this silicide is automatically aligned with the active area. In semiconductor devices, the contact resistance between metal and silicon has a great impact on device performance. Self-aligned silicide technology can significantly reduce this contact resistance and improve the conductivity of the device. Through the self-alignment mechanism, the reliance on high-precision lithography to accurately align the metal and active area is reduced. This helps to improve manufacturing accuracy and consistency in mass production and reduce the defect rate of semiconductor devices caused by alignment errors.
[0051] The present application uses a stress material layer as a barrier layer in the growth of self-aligned silicide. There is no need to remove the stress material layer before patterning, nor is there any need to deposit an additional barrier layer, which simplifies the preparation process of the semiconductor structure, improves the preparation efficiency of the semiconductor structure, and reduces production costs. The stress memory technology is used to increase the driving current of the semiconductor device, improve the speed performance of the semiconductor device, and the formation of self-aligned silicide is conducive to reducing the contact resistance in the semiconductor device and reducing the delay, thereby improving the performance of the semiconductor device.
[0052] In this embodiment, the step S200: forming a stress material layer on one side of the substrate includes the following steps:
[0053] forming a first oxide layer on one side of the substrate;
[0054] The first oxide layer is, for example, a silicon dioxide layer, which can isolate and protect the internal structure of the substrate and help adjust the stress to a certain extent. As a stress buffer layer, it helps to more effectively transfer and control the stress. The first oxide layer can be formed, for example, by chemical vapor deposition or physical vapor deposition.
[0055] forming a stress material layer on a side of the first oxide layer away from the substrate; in this embodiment, the stress material layer is a stress silicon nitride layer;
[0056] The stressed silicon nitride layer can exert stress on the semiconductor structure below. This stress can change the lattice structure of the semiconductor material, thereby affecting the mobility of carriers;
[0057] The stress material layer can be obtained by chemical vapor deposition or physical vapor deposition. According to needs, the stress magnitude and direction of the stress material layer can be controlled by adjusting the parameters of the deposition process, such as gas flow, reaction temperature, pressure, etc., to meet the performance requirements of the semiconductor device.
[0058] The thickness of the first oxide layer and the stressed silicon nitride layer can be selected and set according to the actual production requirements of the semiconductor device. The thickness of the first oxide layer is generally less than the thickness of the stressed silicon nitride layer.
[0059] In this embodiment, the step S300: performing patterning to open the stress material layer in the target area, further includes the following steps:
[0060] A second oxide layer is formed on the side of the stress material layer away from the substrate. Since the stress silicon nitride layer is not suitable for direct contact with the photoresist in the subsequent photolithography process, the second oxide layer can isolate and protect the stress material layer and the photoresist layer. The thickness of the second oxide layer can be selected and set according to the actual production needs of the semiconductor device. The second oxide layer is generally a thin film layer with a small thickness, but the present application is not limited thereto.
[0061] In this embodiment, forming a second oxide layer on a side of the stress material layer away from the substrate comprises the following steps:
[0062] A second oxide layer is deposited on a side of the stress material layer away from the substrate, wherein the second oxide layer is a silicon dioxide layer.
[0063] In this embodiment, the step S300: performing patterning to open the stress material layer in the target area includes the following steps:
[0064] A photolithography process is performed, and the stress material layer in the target area is opened by etching.
[0065] Specifically, photoresist is coated on the surface of the second oxide layer, and a photolithography machine is used for exposure processing. Then, a chemical solution is used to dissolve the exposed photoresist according to a preset pattern, so that the pattern on the mask is revealed on the photoresist layer.
[0066] In one embodiment, the step of opening the stress material layer in the target area by etching comprises the following steps:
[0067] opening the second oxide layer and the photoresist layer in the target area by wet etching;
[0068] For example, hydrogen fluoride HF and SPM (sulfuric acid-hydrogen peroxide mixture) are used to etch and open the second oxide layer and the photoresist layer of the target area;
[0069] opening the stress material layer in the target area by wet etching;
[0070] opening the first oxide layer in the target area by wet etching;
[0071] For example, phosphoric acid H3PO4 and hydrogen fluoride HF are used in sequence to sequentially remove the stress material layer and the first oxide layer in the target area.
[0072] Wet etching is a process that uses the chemical reaction between a chemical solution and the etched material to remove materials. During the wet etching process, the material to be etched is brought into contact with a chemical solution, causing the atoms or molecules on the surface of the material to react with the chemicals in the solution to generate products that are soluble in the solution, thereby achieving material removal.
[0073] Compared with dry etching, wet etching equipment is relatively simple and has lower cost. The structure and operation of the etching groove and some basic auxiliary equipment are relatively easy to understand and master, and do not require complex plasma generating equipment and vacuum systems like dry etching. Since wet etching is used in this embodiment, dry etching is not required, the process is simpler, and the number of wafers processed each time by wet etching is large, which is conducive to improving processing efficiency and further improving the preparation efficiency of semiconductor devices. And wet etching replaces dry etching, reducing defects and production costs.
[0074] Combine the following Figures 2 to 5 The specific implementation process of the stress memory technology implementation method in a specific example is introduced. It is understandable that the structure shown in the drawings and the following description are only examples and are not intended to limit the scope of protection of this application. The shapes and sizes of the various film layers shown in the drawings are only examples and are not intended to limit the scope of protection of this application. In different implementations, the shapes and sizes of each film layer can be adaptively selected and adjusted according to the structural requirements and process requirements of the semiconductor device, and all fall within the scope of protection of this application.
[0075] Figure 2 FIG. 1 is a schematic diagram of providing a substrate in a method for preparing a metal ohmic contact of a semiconductor device according to an embodiment of the present application. Figure 2 As shown, corresponding to the above step S100, a substrate 100 is first provided, and the substrate 100 includes a silicon substrate in which a semiconductor structure is formed.
[0076] Figure 3FIG. 1 is a schematic diagram of a method for preparing a metal ohmic contact of a semiconductor device according to an embodiment of the present application after forming a stress material layer. Figure 3 As shown, corresponding to the above step S200, a first oxide layer 200 is formed on one side of the substrate 100. The first oxide layer 200 is, for example, a silicon dioxide layer, which can isolate and protect the internal structure of the substrate and help adjust the stress to a certain extent; the first oxide layer 200 can be formed, for example, by chemical vapor deposition or physical vapor deposition. Then, a stress material layer 300 is formed on the side of the first oxide layer 200 away from the substrate 100; in this embodiment, the stress material layer 300 is a stress silicon nitride layer. The stress material layer 300 can generate stress in the semiconductor device, and this stress can change the lattice structure of the semiconductor material, thereby affecting the mobility of the carriers, thereby effectively improving the performance of the semiconductor device. The stress material layer 300 can be obtained by chemical vapor deposition or physical vapor deposition. According to needs, the stress magnitude and direction of the stress material layer can be controlled by adjusting the parameters of the deposition process, such as gas flow, reaction temperature, pressure, etc., to meet the performance requirements of the semiconductor device.
[0077] Then, laser annealing or spike annealing is used to anneal the structure formed with the stress material layer 300. Due to the presence of the stress memory material layer, the volume expansion of the gate is suppressed during the annealing process, so that the stress can be effectively memorized. The temperature and time of annealing are precisely controlled according to the characteristics of the stress material and the semiconductor device. Therefore, the stress memory technology is beneficial to increase the driving current of the semiconductor device and improve the speed performance of the semiconductor device. The annealing method can be selected as needed. Laser annealing is a process that uses a high-energy-density laser beam to locally heat and anneal semiconductor materials. When the laser beam irradiates the surface of the semiconductor material, the material absorbs the energy of the laser, causing the surface temperature to rise sharply in a very short time. Spike annealing is a rapid thermal annealing technology, which is characterized by an extremely fast heating speed, which can heat the semiconductor material to a high temperature in a short time and then cool it quickly.
[0078] Figure 4 FIG. 4 is a schematic diagram of a method for preparing a metal ohmic contact of a semiconductor device according to an embodiment of the present application after forming a second oxide layer 400. Figure 4 As shown, a second oxide layer 400 is deposited on one side of the annealed semiconductor structure. The second oxide layer 400 is, for example, a silicon dioxide layer, and is used to isolate and protect the stress material layer from the subsequent photoresist.
[0079] Figure 5 FIG. 1 is a schematic diagram of a method for preparing a metal ohmic contact of a semiconductor device according to an embodiment of the present application after photolithography and etching. Figure 5As shown, corresponding to the above step S300, the annealed semiconductor structure is patterned to open the stress material layer and the first oxide layer in the target area. Specifically, the semiconductor structure is processed by photolithography and etching, and after the second oxide layer 400 is removed by wet etching, the regional stress material layer and the first oxide layer can be etched by dry etching and wet etching respectively, or the stress material layer and the first oxide layer can be removed by wet etching respectively. When patterning, the stress material layer is used as a barrier layer; the target area is, for example, the active area (source, drain, etc.) of the semiconductor structure. Therefore, the stress material layer is used as a barrier layer in the growth of self-aligned silicide. There is no need to remove the stress material layer before patterning, and there is no need to deposit an additional barrier layer, which simplifies the preparation process of the semiconductor structure and reduces the production cost.
[0080] Then, corresponding to the above step S400, a metal layer is deposited and annealed so that the metal layer reacts with the substrate to form a metal silicide. The formation of self-aligned silicide is conducive to reducing the contact resistance in the semiconductor device and reducing the delay, thereby improving the performance of the semiconductor device. The temperature and time of annealing are precisely controlled according to the characteristics of the metal layer and the semiconductor device. The annealing method can be selected as needed, such as rapid annealing, laser annealing, spike annealing, etc.
[0081] The embodiment of the present application also provides a semiconductor structure obtained by using the above-mentioned method for preparing the metal ohmic contact of the semiconductor device. The semiconductor structure includes at least a substrate and a metal silicide layer formed on one side of the substrate. By using the method for preparing the metal ohmic contact of the semiconductor device, the semiconductor device having the semiconductor structure has higher production efficiency and product quality, and has lower production cost. The driving current of the semiconductor device is increased by stress memory technology, the speed performance of the semiconductor device is improved, and the contact resistance in the semiconductor device is reduced by forming a self-aligned silicide, and the delay is reduced, thereby improving the performance of the semiconductor device.
[0082] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0083] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a metal ohmic contact of a semiconductor device, characterized in that: The steps include: providing a substrate; After forming a stress material layer on one side of the substrate, an annealing treatment is performed; Performing patterning to open the stress material layer in the target area; A metal layer is deposited and annealed to allow the metal layer to react with the substrate to form metal silicide.
2. The method for preparing a metal ohmic contact of a semiconductor device according to claim 1, characterized in that: Forming a stress material layer on one side of the substrate comprises the following steps: forming a first oxide layer on one side of the substrate; A stress material layer is formed on a side of the first oxide layer away from the substrate.
3. The method for preparing a metal ohmic contact of a semiconductor device according to claim 1, characterized in that: The stress material layer is a stress silicon nitride layer.
4. The method for preparing a metal ohmic contact of a semiconductor device according to claim 1, characterized in that: Before performing the patterning process to open the stress material layer in the target area, the following steps are also included: A second oxide layer is formed on a side of the stress material layer away from the substrate.
5. The method for preparing a metal ohmic contact of a semiconductor device according to claim 4, characterized in that: Forming a second oxide layer on a side of the stress material layer away from the substrate comprises the following steps: A second oxide layer is deposited on a side of the stress material layer away from the substrate, wherein the second oxide layer is a silicon dioxide layer.
6. The method for preparing a metal ohmic contact of a semiconductor device according to claim 2, characterized in that: The patterning process to open the stress material layer in the target area includes the following steps: A photolithography process is performed, and the stress material layer in the target area is opened by etching.
7. The method for preparing a metal ohmic contact of a semiconductor device according to claim 5, characterized in that: The step of opening the stress material layer in the target area by etching comprises the following steps: opening the second oxide layer and the photoresist layer in the target area by wet etching; opening the stress material layer in the target area by wet etching; The first oxide layer is opened in the target area by wet etching.
8. The method for preparing a metal ohmic contact of a semiconductor device according to claim 1, characterized in that: The metal layer is a nickel-platinum alloy layer.
9. A semiconductor structure, characterized in that: The method for preparing a metal ohmic contact of a semiconductor device according to any one of claims 1 to 8 is used for the preparation.