Stress memory technology implementation method in semiconductor manufacturing and semiconductor structure
By etching the active region surface in semiconductor manufacturing, it has a concave morphology, which solves the problem of small contact area between the stress memory layer and the substrate, improves the stress memory efficiency and improves the quality of the MOSFET device.
Patent Information
- Application Number
- CN202510014491.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2025-04-11
AI Technical Summary
In semiconductor manufacturing, the contact area between the stress memory layer and the substrate is small, which affects the stress memory efficiency, and the stress memory layer cannot effectively cover the active area.
Before depositing the stress memory layer, the surface of the active region is made to have a concave morphology by etching, thereby increasing the contact area between the stress memory layer and the substrate.
It improves stress memory efficiency, solves the problem of small contact area between the stress memory layer and the substrate and cannot cover the active area, thereby improving the product quality of MOSFET devices.
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Figure CN119811994A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for implementing stress memory technology in semiconductor manufacturing and a semiconductor structure. Background Art
[0002] Stress memory technology (SMT) is used in advanced manufacturing processes to enhance the carrier mobility of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The common method is to first deposit a silicon dioxide layer and a stress memory layer, then transfer the stress to the substrate through annealing, and finally remove the stress memory layer through etching.
[0003] In advanced processes, the spacing between MOSFETs is small, and the pre-deposited silicon dioxide layer will cause the stress memory layer to be unable to effectively cover the active area, resulting in limited stress memory efficiency.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0005] In view of the problems in the prior art, the purpose of the present application is to provide a method for implementing stress memory technology in semiconductor manufacturing and a semiconductor structure. Before depositing the stress memory layer, etching is performed to make the surface of the active area concave, thereby increasing the contact area between the stress memory layer and the substrate, solving the defects in the prior art that the contact area between the stress memory layer and the substrate is small and affects the stress memory efficiency, and solving the defects in the prior art that the stress memory layer cannot effectively cover the active area, which is conducive to improving the stress memory efficiency.
[0006] The present application provides a method for implementing stress memory technology in semiconductor manufacturing, including:
[0007] Providing a substrate having a MOSFET structure, wherein the MOSFET structure includes an active region;
[0008] Etching the substrate so that the surface of the active area has a concave morphology;
[0009] Depositing a stress memory layer on a side away from the substrate;
[0010] The substrate is subjected to an annealing treatment.
[0011] In some embodiments, the substrate is dry-etched to make the surface of the active region have a concave morphology.
[0012] In some embodiments, the MOSFET structure further includes a sidewall; when etching the substrate, the surface of the active region is made concave in shape and the height of the sidewall is reduced.
[0013] In some embodiments, when the substrate is etched, the height of the center of the surface of the active area is reduced by 5 nm to 30 nm.
[0014] In some embodiments, before etching the substrate so that the surface of the active area has a concave morphology, the following steps are also included:
[0015] An amorphous ion implantation is performed on the active region of the substrate.
[0016] In some embodiments, the stress memory layer is a stressed silicon nitride layer.
[0017] In some embodiments, depositing a stress memory layer on a side away from the substrate comprises the following steps:
[0018] depositing a silicon dioxide layer on a side facing away from the substrate;
[0019] The stress memory layer is deposited on a side of the silicon dioxide layer away from the substrate.
[0020] In some embodiments, the annealing process includes laser annealing or spike annealing.
[0021] Stress is transferred into the substrate by laser annealing or spike annealing.
[0022] In some embodiments, after the substrate is annealed, the following steps are further included:
[0023] The stress memory layer is removed by etching.
[0024] The embodiment of the present application also provides a semiconductor structure, which is prepared by using the above-mentioned method for implementing stress memory technology in semiconductor manufacturing.
[0025] The method for implementing stress memory technology in semiconductor manufacturing and the semiconductor structure provided by the present application have the following advantages:
[0026] By adopting the stress memory technology implementation method of the present application, before depositing the stress memory layer, etching is performed to make the surface of the active area have a concave morphology, thereby increasing the contact area between the stress memory layer and the substrate and reducing the contact distance between the stress memory layer and the substrate. This solves the defect in the prior art that the contact area between the stress memory layer and the substrate is small, which affects the stress memory efficiency, and the defect in the prior art that the stress memory layer cannot effectively cover the active area, which is beneficial to improving the stress memory efficiency and thus improving the product quality of MOSFET devices.
[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0029] Figure 1 is a flow chart of a method for implementing stress memory technology in semiconductor manufacturing according to an embodiment of the present application;
[0030] Figure 2 is a schematic diagram of providing a substrate having a MOSFET structure according to an embodiment of the present application;
[0031] Figure 3 is a schematic diagram of etching the substrate according to an embodiment of the present application;
[0032] Figure 4 is a schematic diagram of depositing a silicon dioxide layer on one side of a substrate according to an embodiment of the present application;
[0033] Figure 5 It is a schematic diagram of depositing a stress memory layer on a side away from a substrate during a oxidation process according to an embodiment of the present application. DETAILED DESCRIPTION
[0034] The example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as being limited to the embodiments set forth herein; on the contrary, these embodiments are provided so that the present application will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. "Or" and "or" in the specification may both represent "and" or "or". Spatial relationship terms such as "on..." and the like can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented to be "under..." other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptions used herein are interpreted accordingly.
[0035] When used herein, the singular forms "a", "an" and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items. Although "first" or "second" etc. are used in this specification to represent certain features, they are only used to represent the role, and are not used as a limitation on the number and importance of specific features.
[0036] In the prior art MOSFET manufacturing process, when the stress memory technology is implemented, there is a defect that the contact area between the stress memory layer and the substrate is small, which affects the stress memory efficiency. In order to solve the technical problems in the prior art, the embodiment of the present application provides a method for implementing the stress memory technology in semiconductor manufacturing, which aims to increase the contact area between the stress memory layer and the substrate, reduce the contact distance between the stress memory layer and the substrate, and thus improve the stress memory efficiency.
[0037] Figure 1 FIG. 1 is a flow chart of a method for implementing stress memory technology in semiconductor manufacturing according to an embodiment of the present application. Figure 1 As shown, the embodiment of the present application provides a method for implementing stress memory technology in semiconductor manufacturing, including the following steps:
[0038] S100: providing a substrate having a MOSFET structure, wherein the MOSFET structure includes an active region;
[0039] Here, the active region is the region on the semiconductor substrate that can effectively contribute to the electrical performance of the device, including the source region and the drain region; the substrate includes the MOSFET structure, the silicon substrate and other required film layers, the MOSFET structure includes the source, the drain, the gate, the sidewall and the channel, the gate is isolated from the active region by the sidewall, and the channel is the path for carrier transmission between the source and the drain;
[0040] S200: etching the substrate so that the surface of the active area has a concave morphology;
[0041] Here, the concave morphology means that the surface of each active area is at least partially sunken downward to form a groove, and the groove can be an arc-shaped groove or other concave shapes;
[0042] S300: depositing a stress memory layer on a side away from the substrate;
[0043] In this embodiment, the stress memory layer is a stressed silicon nitride layer. The stressed silicon nitride layer (Stressed Silicon Nitride Layer) is a silicon nitride layer formed during the manufacturing process of a semiconductor device. There is stress inside the stressed silicon nitride layer, and the nature and magnitude of the stress can be controlled by different manufacturing processes. The stress memory layer can be deposited by chemical vapor deposition or physical vapor deposition to deposit a layer of stressed silicon nitride layer with a high stress level on the surface of the entire substrate. In other alternative implementations, the stress memory layer can also be made of other materials as needed, such as metal materials, ceramic materials, shape memory polymer materials, etc.
[0044] In the manufacturing process of MOSFET devices, the stressed silicon nitride layer can be used as a stress source to improve carrier mobility. The stress can change the energy band structure of the semiconductor and reduce the effective mass of the carriers, making it easier for the carriers to move under the action of the electric field, thereby improving the driving current and speed of the device.
[0045] S400: performing annealing treatment on the substrate;
[0046] During the annealing process, the stress of the stress memory layer is transferred to the channel region and memorized in the channel region, which will not be affected even if the stress memory layer is removed later. At the same time, annealing can also activate the source and drain regions and repair the damage to the semiconductor material caused by ion implantation and other processes.
[0047] Stress Memorization Technique (SMT) is a technology that introduces stress into semiconductor devices to change the energy band structure and electron transport performance of semiconductors. Stress memory technology can effectively improve the performance of MOSFET devices without significantly increasing process complexity and cost, and is of great significance in promoting the development of semiconductor technology. It can make devices faster and consume less power, meeting the needs of modern electronic products for high-performance chips.
[0048] By adopting the stress memory technology implementation method of the present application, before depositing the stress memory layer through step S300, etching is performed through step S200 to make the surface of the active area have a concave morphology, thereby increasing the contact area between the stress memory layer and the substrate and reducing the contact distance between the stress memory layer and the substrate. This solves the defect in the prior art that the contact area between the stress memory layer and the substrate is small, which affects the stress memory efficiency, and the defect in the prior art that the stress memory layer cannot effectively cover the active area, which is beneficial to improving the stress memory efficiency and thus improving the product quality of MOSFET devices.
[0049] In this embodiment, the substrate is dry-etched to make the surface of the active area concave. Dry etching is a technology used to remove specific materials in the semiconductor manufacturing process. It is a patterning process in which plasma or gaseous chemicals react with the etched material in a gas phase environment, or remove material atoms from the surface by physical bombardment.
[0050] In this embodiment, the MOSFET structure also includes a spacer. In step S200, when etching the substrate, the surface of the active area is concave and the height of the spacer is reduced. In the MOSFET structure, the spacer is an insulating material structure located on both sides of the gate. It is formed by processes such as deposition and etching. The spacer is mainly used to isolate the gate from the source and drain. In subsequent ion implantation or other process steps, the injected ions are prevented from directly affecting the gate.
[0051] In this embodiment, when etching the substrate, the height of the center of the surface of the active area is lowered by 5nm to 30nm, specifically, for example, 10nm, 20nm, 25nm, etc. Only an example range of the height of the active area surface drop is shown here, and it is not used as a limitation on the scope of protection of this application. In practical applications, when etching the substrate, the height of the active area surface drop can be selected according to the specific size of the device, and the drop height needs to be less than the height of the active area itself to avoid penetrating the active area. Therefore, in different embodiments, the drop height of the active area can be within the range listed here, or it can be outside the range listed here.
[0052] In this embodiment, before the step S200 of etching the substrate to make the surface of the active area present a concave morphology, the following steps are also included:
[0053] The active area of the substrate is amorphized by ion implantation. By implanting amorphized ions into the source and drain, the crystal structure of the source and drain regions becomes amorphous so as to better withstand subsequent stress. During the ion implantation process, high-energy ions collide with atoms in the semiconductor lattice, causing the atoms to leave their original lattice positions, generating a large number of vacancies and interstitial atoms. As the implantation dose increases, these defects continue to accumulate, ultimately resulting in the destruction of the long-range order of the crystal structure and the formation of an amorphous structure. The amorphized ion implantation is performed after the sidewall structure of the MOSFET is completed, so that the atomic arrangement in the active area becomes disordered.
[0054] In this embodiment, the step S300 of depositing a stress memory layer on a side away from the substrate includes the following steps:
[0055] A silicon dioxide layer is deposited on the side away from the substrate; specifically, after the amorphization ion implantation, a very thin silicon dioxide buffer layer is grown, which can not only protect the structure below from damage during the subsequent process, but also help to transfer and distribute stress; the deposition thickness of the silicon dioxide layer is controlled according to specific use needs;
[0056] The stress memory layer is deposited on the side of the silicon dioxide layer away from the substrate; in this embodiment, the stress memory layer is a stress silicon nitride layer, and silicon nitride has a high tensile stress, which can apply stress to the transistor channel region below, thereby changing the electrical properties such as the mobility of carriers in the channel; the deposition thickness and stress level of the silicon nitride layer need to be precisely controlled according to the specific device requirements. In this embodiment, before depositing the silicon dioxide layer and the stress silicon nitride layer, the active area and the side wall are opened by dry etching, so that the surface of the active area has a concave morphology, the contact area between the stress memory layer and the substrate is increased, and the contact distance between the stress memory layer and the substrate is reduced, which solves the defects of the prior art that the stress memory layer and the substrate have a small contact area and affect the stress memory efficiency, and the defect that the stress memory layer in the prior art cannot effectively cover the active area, which is conducive to improving the stress memory efficiency.
[0057] In one embodiment, the step S400: annealing the substrate includes transferring stress to the substrate by laser annealing. Laser annealing is a technique that uses a high-energy-density laser beam to perform local heating annealing on semiconductor materials. When the laser beam irradiates the surface of the semiconductor material, the material absorbs the energy of the laser, and the light energy is converted into heat energy, so that the temperature of the surface of the material rises rapidly in a very short time, thereby achieving annealing. Since the laser beam can be focused to a very small spot size, it is possible to perform high-precision local processing on the material.
[0058] In another alternative embodiment, the step S400: annealing the substrate, including transferring stress to the substrate through spike annealing. Spike annealing is a rapid thermal annealing technology, which is characterized by heating the semiconductor material to a high temperature peak in a very short time and then rapidly cooling it. It achieves rapid heating through a special heating device, and the heating time is usually in the millisecond level. During the heating process, impurity atoms in the semiconductor material can be activated, lattice defects can be repaired, and the stress state can also change. Only two types of annealing processes that can be used are listed here as examples. The specific annealing method can be selected according to actual process requirements.
[0059] In this embodiment, after the step S400: annealing the substrate, the following steps are also included:
[0060] The stress memory layer is removed by etching. For example, the stress silicon nitride layer is removed by dry etching to avoid the high stress silicon nitride layer from having a negative impact on the semiconductor device. Then, the silicon dioxide layer can be removed by wet etching or other methods. The stress memory layer is a tensile layer of tensile stress. Although the tensile layer is removed, the stress is memorized through the annealing process, thereby ensuring that the channel still retains stress after the substrate is removed.
[0061] The embodiment of the present application also provides a semiconductor structure, which is used as a part of the structure in the MOSFET device. It is prepared by the above-mentioned method for implementing the stress memory technology in semiconductor manufacturing. Before depositing the stress memory layer, etching makes the surface of the active area concave, increases the contact area between the stress memory layer and the substrate, and reduces the contact distance between the stress memory layer and the substrate, which is conducive to improving the stress memory efficiency, thereby improving the product quality of the semiconductor structure and the MOSFET device having the semiconductor structure.
[0062] Combine the following Figures 2 to 5 The specific implementation process of the stress memory technology implementation method in a specific example is introduced. It is understandable that the structure shown in the drawings and the following description are only examples and are not intended to limit the scope of protection of this application. The shapes and sizes of the various film layers shown in the drawings are only examples and are not intended to limit the scope of protection of this application. In different implementations, the shapes and sizes of the various film layers can be adaptively selected and adjusted according to the structural requirements and process requirements of the MOSFET device, and all fall within the scope of protection of this application.
[0063] Figure 2 FIG. 1 is a schematic diagram of providing a substrate having a MOSFET structure according to an embodiment of the present application. Figure 2As shown, corresponding to step S100, a substrate 100 having a MOSFET structure 200 is provided, and the substrate 100 includes a silicon substrate and the MOSFET structure. The silicon substrate is the basic supporting material of the MOSFET, and is usually a piece of semiconductor material. For an N-channel MOSFET, the substrate is a P-type semiconductor; for a P-channel MOSFET, the substrate is an N-type semiconductor. The function of the substrate is to provide a basic semiconductor environment for the device and participate in forming the internal electric field and conductive structure of the device. The MOSFET structure 200 includes an active area 210, a gate and a sidewall 220. The active area 210 includes a source and a drain region. The source is the starting position for carriers to enter the channel. It is one of the electrodes from which current flows out of the MOSFET and is connected to the drain through a conductive channel. The source is usually highly doped to ensure that there is sufficient supply of carriers and to form a good ohmic contact with the substrate to reduce the contact resistance. The drain is the position where the carriers leave the channel and is the electrode into which the current flows. The doping concentration of the drain is also high so that it can smoothly receive the carriers transmitted through the channel. When a suitable voltage is applied to the gate to form a conductive channel, the carriers of the source will flow through the channel to the drain, thus forming a current between the drain and the source. The gate is the control electrode of the MOSFET, which is isolated from the source and drain by a sidewall.
[0064] The active area 210 of the substrate 100 is subjected to amorphization ion implantation. By implanting amorphization ions into the active area 210, the crystal structure of the active area 210 becomes amorphous so as to better withstand subsequent stress. During the ion implantation process, high-energy ions impact atoms in the semiconductor lattice, causing the atoms to leave their original lattice positions, generating a large number of vacancies and interstitial atoms. As the implantation dose increases, these defects continue to accumulate, eventually resulting in the destruction of the long-range order of the crystal structure and the formation of an amorphous structure.
[0065] Figure 3 FIG. 1 is a schematic diagram of etching the substrate according to an embodiment of the present application. Figure 3 As shown, corresponding to step S200, the substrate 100 is etched so that the surface of the active area 210 has a concave morphology. The active area with a concave morphology is marked as 210' here. At the same time, under the influence of dry etching, the sidewall 220 also drops to a certain height; in this embodiment, the substrate 100 is processed by photolithography and dry etching, and the surface of the active area 210 forms a concave morphology with an arc surface; when the substrate 100 is etched, the height of the center of the surface of the active area 210 is dropped, for example, by 5nm to 30nm, but it is not used as a limitation of the protection scope of the present application. The surface drop height of the active area 210 can be set according to the size and process requirements of the actual MOSFET device, and meet the requirement of being less than the initial height of the active area 210 to avoid penetrating the active area 210.
[0066] Figure 4 is a schematic diagram of depositing a silicon dioxide layer on one side of a substrate according to an embodiment of the present application; Figure 5 FIG. 1 is a schematic diagram of depositing a stress memory layer on the side away from the substrate during the oxidation process according to an embodiment of the present application. Figure 4 and Figure 5 As shown, corresponding to step S300, a silicon dioxide layer 300 is deposited on the side away from the substrate; specifically, after the amorphization ion implantation, a very thin silicon dioxide buffer layer is grown, which can not only protect the structure below from damage during the subsequent process, but also help the transmission and distribution of stress; the deposition thickness of the silicon dioxide layer 300 is controlled according to specific usage needs. The stress memory layer 400 is deposited on the side of the silicon dioxide layer 300 away from the substrate 100; in this embodiment, the stress memory layer 400 is a stress silicon nitride layer, which has a high tensile stress and can apply stress to the transistor channel region below, thereby changing the electrical properties such as the mobility of carriers in the channel; the deposition thickness and stress level of the silicon nitride layer need to be precisely controlled according to the specific device requirements. Because the surface of the active area 210 is made concave by etching before depositing the stress memory layer, the contact area between the stress memory layer 400 and the substrate 100 is increased, and the contact distance between the stress memory layer 400 and the substrate 100 is reduced, which solves the defect of the prior art that the contact area between the stress memory layer and the substrate is small and affects the stress memory efficiency, and the defect that the stress memory layer in the prior art cannot effectively cover the active area, which is conducive to improving the stress memory efficiency.
[0067] exist Figure 5 On the basis of, the substrate 100 is further annealed. In this embodiment, the stress is transferred to the substrate 100 by laser annealing or spike annealing. Laser annealing is a technology that uses a high-energy-density laser beam to perform local heating annealing on semiconductor materials. Spike annealing is a rapid thermal annealing technology, which is characterized by heating the semiconductor material to a high-temperature peak in a very short time and then cooling it rapidly. Here, only two types of annealing processes that can be used are listed as examples. The specific annealing method can be selected according to actual process requirements. The stress memory layer 400 is then removed by etching. For example, the stress silicon nitride layer is removed by photolithography and dry etching to avoid the high-stress silicon nitride layer from having a negative impact on the semiconductor device. Then, the silicon dioxide layer can be removed by wet etching or other methods. The stress memory layer is a tensile layer of tensile stress. Although the tensile layer is removed, the stress is memorized through the annealing process, thereby ensuring that the channel still retains stress after the substrate is removed.
[0068] The above content is a further detailed description of the present application in combination with specific preferred implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.
Claims
1. A method for implementing stress memory technology in semiconductor manufacturing, characterized in that: The steps include: Providing a substrate having a MOSFET structure, wherein the MOSFET structure includes an active region; Etching the substrate so that the surface of the active area has a concave morphology; Depositing a stress memory layer on a side away from the substrate; The substrate is subjected to an annealing treatment.
2. The method for implementing stress memory technology in semiconductor manufacturing according to claim 1, characterized in that: The substrate is dry-etched to make the surface of the active area present a concave morphology.
3. The method for implementing stress memory technology in semiconductor manufacturing according to claim 1, characterized in that: The MOSFET structure also includes a side wall; when the substrate is etched, the surface of the active area is made concave in shape and the height of the side wall is reduced.
4. The method for implementing stress memory technology in semiconductor manufacturing according to claim 1, characterized in that: When the substrate is etched, the height of the surface center of the active area is lowered by 5nm to 30nm.
5. The method for implementing stress memory technology in semiconductor manufacturing according to claim 1, characterized in that: Before etching the substrate so that the surface of the active area has a concave morphology, the following steps are also included: An amorphous ion implantation is performed on the active region of the substrate.
6. The method for implementing stress memory technology in semiconductor manufacturing according to claim 1, characterized in that: The stress memory layer is a stress silicon nitride layer.
7. The method for implementing stress memory technology in semiconductor manufacturing according to claim 1, characterized in that: Depositing a stress memory layer on a side away from the substrate comprises the following steps: depositing a silicon dioxide layer on a side facing away from the substrate; The stress memory layer is deposited on a side of the silicon dioxide layer away from the substrate.
8. The method for implementing stress memory technology in semiconductor manufacturing according to claim 1, characterized in that: The annealing process includes laser annealing or spike annealing, Stress is transferred into the substrate by laser annealing or spike annealing.
9. The method for implementing stress memory technology in semiconductor manufacturing according to claim 1, characterized in that: After the substrate is annealed, the method further comprises the following steps: The stress memory layer is removed by etching.
10. A semiconductor structure, characterized in that: The method for implementing stress memory technology in semiconductor manufacturing according to any one of claims 1 to 9 is used for preparation.