Frame substrate and manufacturing method

Abstract

The invention provides a frame substrate and a manufacturing method. Specifically, the frame substrate comprises a dielectric layer, a conduction copper column and a circuit layer. Wherein the dielectric layer comprises at least one cavity, and the cavity penetrates through the dielectric layer; the conduction copper column is located in the dielectric layer; and the circuit layer is positioned on the surface of the dielectric layer and is connected with the conducting copper columns. According to the technical scheme, the conducting copper columns in the frame substrate are connected with the circuit layer, and after the components are embedded subsequently, the conducting copper columns do not need to be connected through windowing again, so that the processing technology is saved.

Description

Technical Field

[0001] The present disclosure relates to the field of packaging technology, and in particular to a frame substrate and a manufacturing method thereof. Background Art

[0002] With the advancement of science and technology, electronic products are widely used in all aspects of production and life. At the same time, users not only require higher and higher performance of electronic products, but also require smaller and thinner sizes of electronic products. Such requirements lead to more and more complex circuits of electronic components and circuit substrates. Integration, miniaturization, systematization and multi-function are inevitable trends. In terms of improving the functions of electronic products and further miniaturization, more efficient and precise packaging of integrated circuits and components plays a key role, among which embedded packaging of components is a key breakthrough direction. Summary of the invention

[0003] In view of this, an object of the present disclosure is to provide a frame substrate and a manufacturing method thereof.

[0004] Based on the above objectives, the present disclosure provides a method for manufacturing a frame substrate, comprising:

[0005] (a) providing a carrier plate, wherein a metal layer is disposed on the carrier plate;

[0006] (b) forming a first photoresist pattern layer including a conductive copper pillar opening and a sacrificial copper wall opening on the metal layer of the carrier plate;

[0007] (c) forming a conductive copper pillar in the conductive copper pillar opening, forming a sacrificial copper wall in the sacrificial copper wall opening, and removing the first photoresist pattern layer;

[0008] (d) laminating a dielectric layer; wherein the thickness of the dielectric layer is greater than the height of the conductive copper pillar;

[0009] (e) opening windows in the dielectric layer to form conductive blind holes exposing the end faces of the conductive copper pillars and blind grooves exposing the end faces of the sacrificial copper walls;

[0010] (f) forming a circuit layer connected to the conductive copper pillar on the dielectric layer;

[0011] (g) removing the carrier plate;

[0012] (h) etching the sacrificial copper wall to form a frame substrate having a cavity, wherein the cavity penetrates the dielectric layer.

[0013] In some embodiments, the difference between the thickness of the dielectric layer and the height of the conductive copper pillar is 10-100 μm.

[0014] In some embodiments, the material of the dielectric layer includes at least one of free liquid crystal polymer, BT resin, semi-cured prepreg, ABF film, epoxy resin and polyimide resin.

[0015] In some embodiments, step (b) comprises:

[0016] The first photoresist pattern layer is obtained by laminating, exposing and developing on the carrier plate.

[0017] In some embodiments, step (c) forms the conductive copper pillar and the sacrificial copper wall by electroplating.

[0018] In some embodiments, step (d) further comprises:

[0019] A copper foil is laminated on the dielectric layer to form a third copper layer; wherein the third copper layer is located on a side of the dielectric layer away from the carrier board.

[0020] In some embodiments, step (f) comprises:

[0021] (f1) chemically depositing copper on the conductive blind vias;

[0022] (f2) laminating, exposing, and developing on the third copper layer to form a second photoresist pattern layer;

[0023] (f3) filling the hollowed-out area of ​​the second photoresist pattern layer with electroplating to form the circuit layer;

[0024] (f4) removing the second photoresist pattern layer;

[0025] (f5) Etching the third copper layer.

[0026] In some embodiments, step (e) opens windows in the dielectric layer by laser drilling.

[0027] In some embodiments, the metal layer of the carrier plate includes a first copper layer and a second copper layer sequentially disposed on the carrier layer; the first copper layer and the second copper layer are physically combined with each other;

[0028] Step (g) comprises:

[0029] separating the first copper layer and the second copper layer;

[0030] The dry film shields the circuit layer and etches the second copper layer.

[0031] Based on the same inventive concept, an embodiment of the present disclosure also provides a frame substrate, including a dielectric layer, a conductive copper pillar and a circuit layer; wherein the dielectric layer includes at least one cavity, and the cavity penetrates the dielectric layer; the conductive copper pillar is located in the dielectric layer and the height of the conductive copper pillar is less than the thickness of the dielectric layer; the circuit layer is located on the surface of the dielectric layer; the side of the dielectric layer close to the circuit layer includes a blind hole and the circuit layer is connected to the conductive copper pillar via the blind hole.

[0032] From the above description, it can be seen that the frame substrate and manufacturing method provided by the embodiment of the present disclosure, by opening windows in the dielectric layer to form a conductive blind hole exposing the end face of the conductive copper column and a blind groove exposing the end face of the sacrificial copper wall, can achieve the etching of the sacrificial copper wall without grinding and thinning, thereby achieving the technical effect of simplifying the process flow and reducing material costs. In addition, since the grinding and thinning process is omitted, the uniformity of the dielectric layer surface can be effectively guaranteed, which helps to improve the quality of subsequent embedded packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic diagram of the structure of a frame substrate provided by the related art is shown;

[0035] Figure 2 A schematic structural diagram of a frame substrate provided by an embodiment of the present disclosure is shown;

[0036] Figure 3(a) to Figure 3(k) A cross-sectional or top view schematic diagram showing an intermediate structure of each step of a method for manufacturing a frame substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0038] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. In the accompanying drawings, the thickness and shape of some layers and regions may be exaggerated for better understanding and ease of description.

[0039] When terms such as “on,” “above,” “below,” and “beside” are used to describe the positional relationship between two components, unless these terms are used together with the term “immediately” or “directly,” one or more components may be located between the two components.

[0040] When an element or layer is disposed “on” another element or layer, the other layer or element may be directly on the other element or interposed between them.

[0041] Figure 1 FIG. 1 is a schematic diagram showing a structure of a frame substrate provided by the related art. Figure 1 As shown, the frame substrate 10 may include a polymer frame 16 and through-hole copper pillars 14. The polymer frame 16 includes an array-arranged buried core frame 12, and the through-hole copper pillars 14 are located on the periphery of the buried core frame 12; wherein the buried core frame 12 is used to embed the chip.

[0042] The method for making the frame substrate 10 may include: a) obtaining a sacrificial carrier and applying a copper seed layer on the sacrificial carrier; b) applying a photolithography dry film on the carrier; c) patterning the dry film and forming sacrificial copper pillar through holes and copper through holes; d) depositing copper on the carrier to form sacrificial copper pillars and through-hole copper pillars; e) laminating the through-hole copper pillars and sacrificial copper pillars with polymer dielectrics; f) thinning and flattening the ends of the exposed copper pillars; g) removing the sacrificial carrier and the seed layer; h) applying an etch-resistant photolithography dry film and patterning to expose the sacrificial copper pillars; i) etching to remove the sacrificial copper pillars to form a buried core frame; j) removing the etch-resistant photolithography dry film.

[0043] With this technical solution, the processing process is long and the cost is high; step e) requires pressing thicker dielectric materials and then grinding the plate to thin it, which consumes a lot of materials and is costly; moreover, the thickness uniformity of the grinding plate is poor, which affects the quality of the subsequent embedded devices on the frame substrate.

[0044] In addition, after the device is set in the buried core frame 12, a dielectric layer is usually required to be laminated to achieve embedding, and the laminated dielectric layer often covers the through-hole copper pillar 14. In order to guide the through-hole copper pillar 14, it is also necessary to open a window in the dielectric layer to facilitate the connection between the circuit layer and the through-hole copper pillar 14. The whole process has many steps and a complicated flow.

[0045] In view of this, the embodiment of the present disclosure provides a frame substrate and a manufacturing method, which forms a conductive blind hole for exposing the end face of the conductive copper column and a blind groove for exposing the end face of the sacrificial copper wall by opening a window in the dielectric layer, and can achieve the etching of the sacrificial copper wall without grinding and thinning the plate, thereby achieving the technical effect of simplifying the process flow and reducing material costs. In addition, since the grinding and thinning process is omitted, the uniformity of the dielectric layer surface can be effectively guaranteed, which helps to improve the quality of subsequent embedded packaging.

[0046] In a first aspect, the present disclosure provides a frame substrate. Figure 2 As shown, the frame substrate includes a dielectric layer 700, a conductive copper pillar 301 and a circuit layer 600; wherein the dielectric layer 700 includes at least one cavity 701, and the cavity 701 penetrates the dielectric layer 700; the conductive copper pillar 301 is located in the dielectric layer 700 and its height is less than the thickness of the dielectric layer 700; the circuit layer 600 is located on the surface of the dielectric layer 700, and the side of the dielectric layer 700 close to the circuit layer 600 includes a blind hole, so that the circuit layer 600 is connected to the conductive copper pillar 301 via the blind hole. Here, the cavity 701 is used to embed components, including but not limited to active components (such as transistors, IC chips, logic circuit components, power amplifiers), passive components (capacitors, inductors, resistors) or combinations thereof.

[0047] With this technical solution, the conductive copper pillars 301 in the frame substrate are connected to the circuit layer 600 by means of blind holes. After the components are subsequently embedded, there is no need to open windows again to connect the conductive copper pillars 301, which helps to save processing technology.

[0048] In a second aspect, an embodiment of the present disclosure provides a method for manufacturing a frame substrate. Figure 3(a) to Figure 3(k) The cross-sectional schematic diagram shows the intermediate structure of each step of the method for manufacturing a frame substrate provided by an embodiment of the present disclosure. Figure 3(a) to Figure 3(k) As shown, the manufacturing method comprises:

[0049] First, a carrier plate 100 is provided—step (a), as shown in FIG. 3( a ).

[0050] In some embodiments, the carrier board 100 includes a carrier layer 101 and a first copper layer 102 and a second copper layer 103 sequentially disposed on the carrier layer 101; the first copper layer 102 and the second copper layer 103 are physically combined with each other. It should be noted that the first copper layer 102 and the second copper layer 103 can be physically separated.

[0051] Next, a first photoresist pattern layer 200 including a conductive copper pillar opening 201 and a sacrificial copper wall opening 202 is formed on the carrier board 100—step (b), as shown in FIG3(b) and FIG3(c). Here, FIG3(c) is a top view of FIG3(b).

[0052] Exemplarily, the first photoresist pattern layer 200 is obtained by laminating, exposing, and developing on the carrier board 100 .

[0053] Then, a conductive copper pillar 301 is formed in the conductive copper pillar opening 201, a sacrificial copper wall 302 is formed in the sacrificial copper wall opening 202, and the first photoresist pattern layer 200 is removed—step (c), as shown in Figures 3(d) and 3(e); wherein Figure 3(e) is a top view of Figure 3(d).

[0054] In some embodiments, the conductive copper pillar 301 and the sacrificial copper wall 302 are formed by electroplating. It should be noted that the second copper layer 103 can be used as a seed layer for electroplating.

[0055] Next, a dielectric layer 400 and a third copper layer 401 are laminated; wherein the thickness of the dielectric layer 400 is greater than the height of the conductive copper pillar 301 - step (d), as shown in FIG3(f). It should be noted that the third copper layer 401 can be a thin copper foil, and the third copper layer 401 is located on the side of the dielectric layer 400 away from the carrier board 100.

[0056] It should be understood that the height of the conductive copper pillar 301 and the height of the sacrificial copper wall 302 can be the same. In this case, when the thickness of the dielectric layer 400 is greater than the height of the conductive copper pillar 301 , the thickness of the dielectric layer 400 is also greater than the height of the sacrificial copper wall 302 .

[0057] Optionally, the material of the dielectric layer 400 includes one of the group consisting of free liquid crystal polymer, BT (bismaleimidetriazine) resin, semi-cured prepreg, ABF (Ajinomoto Build-up) film, epoxy resin and polyimide resin, but the present disclosure is not limited thereto.

[0058] Optionally, the material of the dielectric layer 400 may include glass fiber.

[0059] In some embodiments, the difference between the thickness of the dielectric layer 400 and the height 301 of the conductive copper pillar is 10-100 μm, for example, 20 μm, 40 μm, 50 μm, 55 μm, 70 μm, or 100 μm.

[0060] Laminating the third copper layer 401 on the dielectric layer 400 can make the dielectric layer be sandwiched between the upper and lower metal layers (for example, between the second copper layer 103 and the third copper layer 401). Since the metal layers have the same thermal expansion coefficient, when the dielectric layer 400 is thermally cured, the dielectric layer 400 can be rigidly constrained by the upper and lower metal layers to remain flat, and will not be warped or deformed due to heat due to the difference in thermal expansion coefficients.

[0061] Then, windows are opened in the dielectric layer 400 and the third copper layer 401 to form a conductive blind hole 501 exposing the end surface of the conductive copper pillar 301 and a blind groove 502 exposing the end surface of the sacrificial copper wall 302—step (e), as shown in FIG. 3( g).

[0062] Optionally, windows are opened in the dielectric layer 400 and the third copper layer 401 by laser drilling, laser drilling or mechanical drilling.

[0063] By opening a window to expose the end face of the sacrificial copper wall 302, the sacrificial copper wall 302 can be etched without grinding the plate, effectively shortening the processing flow, reducing dielectric material loss, and thus reducing the cost of making the frame substrate. At the same time, compared with grinding the plate, the thickness, thickness uniformity, and surface smoothness of the frame substrate are effectively controlled, improving the quality of the subsequent embedded devices on the frame substrate.

[0064] Next, a circuit layer 600 connected to the conductive copper pillars 301 is formed on the dielectric layer 400—step (f), as shown in FIG. 3( h ).

[0065] In some embodiments, step (f) comprises:

[0066] (f1) chemically depositing copper on the via blind hole 501;

[0067] (f2) laminating, exposing, and developing on the third copper layer 400 to form a second photoresist pattern layer;

[0068] (f3) filling the hollowed-out area of ​​the second photoresist pattern layer with electroplating to form a circuit layer 600;

[0069] (f4) removing the second photoresist pattern layer;

[0070] (f5) Etching the third copper layer.

[0071] Here, the third copper layer 401 is used as a seed layer, and the step of forming the seed layer can be omitted, which helps to save the process flow.

[0072] By opening a window to expose the end face of the conductive copper pillar 301, it is convenient for the circuit layer 600 to connect to the conductive copper pillar 301, and the step of opening a window to connect the circuit layer and the conductive copper pillar 301 after embedding the device is omitted, thereby achieving the technical effect of saving process. In other words, the technical solution of the embodiment of the present disclosure replaces the three steps of thinning, applying a dielectric layer and opening a window in the related technology by opening a window in one step, which significantly saves the process and cost.

[0073] Then, the carrier plate 100 is removed—step (g), as shown in FIG. 3( i ) and FIG. 3( j ).

[0074] In some embodiments, step (g) comprises:

[0075] Separating the first copper layer 102 and the second copper layer 103;

[0076] The dry film masks the circuit layer 600 and etches the second copper layer 103 .

[0077] Finally, the sacrificial copper wall 302 is etched to form a frame substrate 700 having a cavity 701 ; wherein the cavity 701 penetrates the dielectric layer 400 - step (h), as shown in FIG. 3( k ).

[0078] It should be noted that before etching the sacrificial copper wall 302 , the area outside the sacrificial copper wall 302 is shielded with a dry film for protection.

[0079] It should be understood that the number of cavities 701 may be one or more. According to the number of cavities 701, a corresponding number of sacrificial copper walls may be provided, which is not limited in the present disclosure.

[0080] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0081] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for manufacturing a frame substrate, characterized in that: include: (a) providing a carrier plate, wherein the carrier plate has a metal layer; (b) forming a first photoresist pattern layer including a conductive copper pillar opening and a sacrificial copper wall opening on the metal layer of the carrier plate; (c) forming a conductive copper pillar in the conductive copper pillar opening, forming a sacrificial copper wall in the sacrificial copper wall opening, and removing the first photoresist pattern layer; (d) laminating a dielectric layer; wherein the thickness of the dielectric layer is greater than the height of the conductive copper pillar; (e) opening windows in the dielectric layer to form conductive blind holes exposing the end faces of the conductive copper pillars and blind grooves exposing the end faces of the sacrificial copper walls; (f) forming a circuit layer connected to the conductive copper pillar on the dielectric layer; (g) removing the carrier plate; (h) etching the sacrificial copper wall to form a frame substrate having a cavity, wherein the cavity penetrates the dielectric layer.

2. The method according to claim 1, characterized in that: The difference between the thickness of the dielectric layer and the height of the conductive copper pillar is 10-100 μm.

3. The method according to claim 1, characterized in that: The material of the dielectric layer includes at least one of free liquid crystal polymer, BT resin, semi-cured prepreg, ABF film, epoxy resin and polyimide resin.

4. The method according to claim 1, characterized in that: Step (b) comprises: The first pattern layer is obtained by laminating, exposing and developing the film on the carrier plate.

5. The method according to claim 1, characterized in that: Step (c) forms the conductive copper pillar and the sacrificial copper wall by electroplating.

6. The method according to claim 1, characterized in that: Step (d) further comprises: The copper foil is laminated to form a third copper layer; wherein the third copper layer is located on a side of the dielectric layer away from the carrier board.

7. The manufacturing method according to claim 6, characterized in that: Step (f) comprises: (f1) chemically depositing copper on the conductive blind vias; (f2) laminating, exposing, and developing on the third copper layer to form a second photoresist pattern layer; (f3) filling the hollowed-out area of ​​the second photoresist pattern layer with electroplating to form the circuit layer; (f4) removing the second photoresist pattern layer; (f5) Etching the third copper layer.

8. The manufacturing method according to claim 1, characterized in that: Step (e) opening windows in the dielectric layer by laser drilling process.

9. The manufacturing method according to claim 1, characterized in that: The metal layer of the carrier plate includes a first copper layer and a second copper layer sequentially arranged on the carrier layer; the first copper layer and the second copper layer are physically combined with each other; Step (g) comprises: separating the first copper layer and the second copper layer; The dry film shields the circuit layer and etches the second copper layer.

10. A frame substrate, characterized in that: It includes a dielectric layer, a conductive copper pillar and a circuit layer; wherein the dielectric layer includes at least one cavity, and the cavity runs through the dielectric layer; the conductive copper pillar is located in the dielectric layer and the height of the conductive copper pillar is less than the thickness of the dielectric layer; the circuit layer is located on the surface of the dielectric layer; the side of the dielectric layer close to the circuit layer includes a blind hole, and the circuit layer is connected to the conductive copper pillar via the blind hole.

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