Semiconductor device and forming method thereof

Abstract

A method of forming a semiconductor device includes forming a bonding structure including thermally conductive vias (also referred to as thermal vias, thermally conductive pillars, or thermal pillars) on a semiconductor structure. The thermal vias have a material thermal conductivity of greater than about 10 W / m.K and are embedded into a bonding structure that provides a rapid heat dissipation path from the hot spot region to the substrate. The embodiment of the invention also discloses a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each smaller and more complex than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] This shrinkage has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances. The shrinking size and high integration density of semiconductor devices make heat dissipation challenging. For example, as the front-side and back-side interconnect structures become more compact as IC component sizes continue to shrink, heat generated in the IC device layers may be captured by the dielectric layers of the interconnect structures, which typically have poor thermal conductivity and result in sharp localized temperature peaks, sometimes referred to as hot spots. Hot spots caused by device-generated heat can negatively affect the electrical performance of the IC and often lead to electromigration and reliability issues for electronic components in the IC. Therefore, while existing semiconductor structures are generally adequate for their intended purposes, they are not completely satisfactory in all respects. Therefore, there is a need to address or mitigate the above-mentioned deficiencies and problems. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a first dielectric layer on a semiconductor structure, the semiconductor structure comprising a semiconductor device layer having a front side and a back side, a first substrate disposed on the back side of the semiconductor device layer, and a first interconnect structure disposed on the front side of the semiconductor device layer; forming a plurality of first through holes passing through the first dielectric layer and extending to the first interconnect structure, the first through holes having a first thermally conductive material having a thermal conductivity greater than about 10 W / m·K; forming a second dielectric layer on a second substrate; forming a plurality of second through holes passing through the second dielectric layer and extending to the second substrate, the second through holes having a second thermally conductive material having a thermal conductivity greater than about 10 W / m·K; bonding the second dielectric layer to the first dielectric layer, and bonding the second through holes to the first through holes; and forming a second interconnect structure on the back side of the semiconductor device layer.

[0005] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a first interconnect structure on a first side of a semiconductor device layer; forming a bonding structure connecting the first interconnect structure and a substrate, the bonding structure comprising a dielectric layer and an array of thermally conductive pillars extending through the dielectric layer, the thermally conductive pillars being electrically isolated from the semiconductor device layer; and forming a second interconnect structure on a second side of the semiconductor device layer, the second side of the semiconductor device layer being opposite to the first side of the semiconductor device layer.

[0006] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a semiconductor device layer; a front-side interconnect structure located above the semiconductor device layer; a back-side interconnect structure located below the semiconductor device layer; and a substrate bonded to the front-side interconnect structure via a bonding structure, wherein the bonding structure comprises: a dielectric layer; and a plurality of thermal pillars extending through the dielectric layer, the thermal pillars having a first end connected to the front-side interconnect structure and a second end connected to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A cross-sectional view of layers involved in a semiconductor device according to some embodiments of the present disclosure is shown.

[0009] Figure 2A , Figure 2B , Figure 2C and Figure 2D A top view of a thermal via in a bonding structure according to some embodiments of the present disclosure is shown.

[0010] Figure 3 Some embodiments of the present disclosure are shown Figure 1 A cross-sectional view of a region of a semiconductor device.

[0011] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Fig. 4I and Figure 4J-1 Some embodiments of the present disclosure are shown Figure 1 A cross-sectional view of a semiconductor device during formation of different layers.

[0012] Figure 4J-2 , Figure 4J-3and Figure 4J-4 Some alternative embodiments of the present disclosure are shown. Figure 1 A cross-sectional view of a semiconductor device.

[0013] Figure 5A , Figure 5B , Figure 5C and Figure 5D-1 Some alternative embodiments of the present disclosure are shown. Figure 1 A cross-sectional view of a semiconductor device during formation of different layers.

[0014] Figure 5D-2 , Figure 5D-3 and Figure 5D-4 Some alternative embodiments of the present disclosure are shown. Figure 1 A cross-sectional view of a semiconductor device. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] In addition, for ease of description, spacing relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spacing relationship terms are intended to include different orientations of the device in use or operating processes. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relationship descriptors used in this article can be interpreted accordingly. In addition, when "about", "approximately", etc. are used to describe a number or a range of numbers, unless otherwise stated, the term is intended to cover numbers within + / -10% of the described number. For example, the term "about 5nm" includes a size range of 4.5nm to 5.5nm.

[0017] Thermal energy in the form of heat may be generated during the operation of a circuit, and some types of circuits may generate more heat than other types of circuits. When heat-generating circuits are packed closely together in an IC structure, one or more hot spots may form. These hot spots may refer to areas / areas on the IC structure that generate more heat per unit area / volume per unit time than other areas of the IC structure. For example, during operation of the IC structure, the temperature of the hot spot area may be higher than the temperature of areas adjacent to the hot spot area.

[0018] Traditionally, semiconductor devices are built in a stacked manner, with transistors at the lowest level (semiconductor device layer) and front-side interconnect structures (contacts, vias, and metal lines) on top of the transistors to provide connections to the transistors. Power rails (e.g., metal lines for voltage sources and ground planes) are also above the transistors and can be part of the interconnect structure. As integrated circuits continue to shrink, the power rails are also shrinking. This inevitably leads to an increase in the voltage drop across the power rails and increased power consumption of the integrated circuits. In addition to the power rails, signal lines are also affected by this shrinkage, such as the continuous reduction in signal line spacing, resulting in increased parasitic capacitance and reduced circuit speed. To meet this challenge, a back-side interconnect structure including power rails and / or signal lines and vias formed on the back side of the IC structure can be implemented to relieve some of the metal wiring burden of the front-side interconnect structure and reduce its resistance and parasitic capacitance. In order to access the back side of the IC structure, the IC structure is usually bonded to a carrier substrate (e.g., a wafer) through a dielectric bonding layer. However, the dielectric bonding layer usually has poor thermal conductivity and blocks the heat dissipation path on the front side of the IC structure. At the same time, the backside interconnect structure usually uses low-k or ultra-low-k (ELK) dielectric materials, which may also have poor thermal conductivity. Therefore, the dielectric bonding layer on the front side of the IC structure combined with the backside interconnect structure will jointly reduce the thermal performance of the IC structure.

[0019] The present disclosure generally relates to a bonding structure that provides thermally conductive vias (also referred to as thermal vias, thermally conductive posts or thermal posts) that are embedded in the bonding structure to improve the overall thermal conductivity of the bonding structure, allowing heat to quickly dissipate from hot spot areas to a carrier substrate.

[0020] Figure 11 is a cross-sectional view showing a semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 may be any semiconductor device, such as but not limited to a logic device, a memory device, or any other semiconductor device. In some embodiments, the semiconductor device 100 may be a semiconductor device package. In the illustrated embodiment, the semiconductor device 100 includes a carrier substrate 102, a bonding structure 104 including a dielectric layer 106 and an array of thermal vias 108, a front-side interconnect structure 110, a back-side interconnect structure 114, and a semiconductor device layer 112 sandwiched between the front-side interconnect structure 100 and the back-side interconnect structure 114.

[0021] The carrier substrate 102 may be any suitable substrate. In some embodiments, the carrier substrate 102 may be a semiconductor wafer. In some embodiments, the carrier substrate 102 may be a single crystal silicon (Si) wafer, an amorphous silicon wafer, a gallium arsenide (GaAs) wafer, or any other semiconductor wafer. In some embodiments, the carrier substrate 102 may be a carrier wafer that may be substantially free of electrical components and may be used to bond to the semiconductor device 100 (e.g., bond to the front side interconnect structure 110 and the semiconductor device layer 112) during backside processing of the semiconductor device 100.

[0022] The semiconductor device layer 112 includes one or more semiconductor devices. In various embodiments, the semiconductor device included in the semiconductor device layer 112 may be any semiconductor device. In some embodiments, the semiconductor device layer 112 includes one or more transistors, which may include any suitable transistor structure, including, for example, FinFET, full-ring gate (GAA) transistors, etc. In some embodiments, the semiconductor device layer 112 includes one or more GAA transistors. In some embodiments, the semiconductor device layer 112 may be a logic layer including one or more semiconductor devices, and may also include their interconnect structures, which are configured and arranged to provide logic functions such as AND, OR, XOR, XNOR, or NOT, or storage functions such as flip-flops or latches.

[0023] In some embodiments, the semiconductor device layer 112 may include a memory device, which may be any suitable memory device, such as a static random access memory (SRAM) device. The memory device may include a plurality of memory cells configured in rows and columns, although other embodiments are not limited to such an arrangement. Each memory cell may include a plurality of transistors (e.g., six) connected between a first voltage source (e.g., VDD) and a second voltage source (e.g., VSS or ground) such that one of the two storage nodes may be occupied by the information to be stored, while complementary information is stored at the other storage node.

[0024] The semiconductor device layer 112 of the semiconductor device 100 may also include various circuits electrically coupled to the semiconductor device layer 122. For example, the semiconductor device layer 112 may include power management or other circuits electrically coupled to one or more semiconductor devices of the semiconductor device layer 122. The power management circuit may include any suitable circuit for controlling or otherwise managing communication signals (such as input power signals) to or from the semiconductor devices of the semiconductor device layer 112. In some embodiments, the power management circuit may include a power gating circuit that may reduce power consumption, for example, by cutting off current to unused blocks in the circuit (e.g., blocks or electrical components in the semiconductor device layer 112), thereby reducing standby or leakage power. In some embodiments, the semiconductor device layer 112 includes one or more switching devices, such as a plurality of transistors, for sending electrical signals to or receiving electrical signals from the semiconductor devices in the semiconductor device layer 112 to turn on and off the circuits (e.g., transistors, etc.) of the semiconductor device layer 122.

[0025] The front side interconnect structure 110 is disposed on the front side of the semiconductor device layer 112, for example, Figure 1 The upper side shown. The IC manufacturing process flow is generally divided into three categories: front-end process (FEOL), middle-end process (MEOL) and back-end process (BEOL). FEOL generally includes processes related to the manufacture of IC devices (such as transistors). For example, the FEOL process may include the formation of isolation components, gate structures, and source and drain components (commonly referred to as source / drain components). MEOL generally includes processes related to the manufacture of contacts of conductive components (or conductive regions) of IC devices, such as contacts with gate structures and / or source / drain components. BEOL generally includes processes related to the manufacture of multi-layer interconnect structures that interconnect IC components manufactured by FEOL and MEOL to achieve the operation of IC devices. The front-side interconnect structure 110 may be referred to as a BEOL structure 110. In some embodiments, the total thickness of the front-side interconnect structure 110 (e.g., between the semiconductor device layer 112 and the bonding structure 104) is less than 10 μm. In some embodiments, the total thickness of the front-side interconnect structure 110 is less than 5 μm, and in some embodiments, in the range of 0.1 μm to 5 μm. The front-side interconnect structures 110 may each include a dielectric layer having metallization features (e.g., vias, lines, traces, etc.) embedded therein. The dielectric layer may be a low-k dielectric layer, such as SiO2, SiON, SiOC, SiOCN, etc. The metallization features may be or include copper, tungsten, ruthenium, molybdenum, titanium, titanium nitride, other metals, alloys thereof, multi-layer combinations thereof, etc.

[0026] The backside interconnect structure 114 is disposed on the backside of the semiconductor device layer 112, for example, Figure 1The backside interconnect structure 114 may include any suitable electrical interconnect structure, circuit, wiring, etc., which is suitable for receiving electrical signals from the semiconductor device layer 112 or transmitting electrical signals from the semiconductor device layer 112. In some embodiments, the backside interconnect structure 114 includes a backside power rail. The backside power rail may be disposed, for example, between a backside power delivery network and a backside via, and the backside via may electrically couple the backside power rail to the semiconductor device in the semiconductor device layer 112. In some embodiments, the backside power rail of the backside interconnect structure 114 may include a plurality of wires or power rails, which may be operable to transmit electrical signals (e.g., power or voltage signals) to or receive electrical signals from the semiconductor device in the semiconductor device layer 112. The backside power rail may be formed by any suitable metallization component. The metallization component may be or include copper, tungsten, ruthenium, molybdenum, titanium, titanium nitride, other metals, alloys thereof, multilayer combinations thereof, etc.

[0027] The backside interconnect structure 114 may also include an insulating layer covering various components (e.g., conductive components) of the backside interconnect structure 114. For example, an insulating layer may be included that covers or substantially covers the backside power rails, the backside vias, and the metallization layer of the backside interconnect structure 114. The insulating layer may be formed of any suitable insulating material, and in some embodiments, the insulating layer electrically insulates or isolates the various electrical components within the backside interconnect structure 114 from each other. In some embodiments, the insulating layer may be formed of a dielectric material that may include one or more of SiO2, SiON, SiOC, and SiOCN or any other suitable insulating material. The insulating layer may be disposed on and in contact with the semiconductor device layer 112. In some embodiments, the thickness of the backside interconnect structure 114 is less than 10 μm. In some embodiments, the thickness of the backside interconnect structure 114 is less than 5 μm, and in some embodiments, is in the range of 0.1 μm to 5 μm.

[0028] In some embodiments, the semiconductor device 100 includes an electrical contact 116 that is electrically coupled to a metallization layer in the backside interconnect structure 114. The metallization layer extends between the electrical contact 116 and the semiconductor device layer 112 on the backside of the semiconductor device 100. In some embodiments, the metallization layer electrically connects the electrical contact 116 to one or more semiconductor devices in the semiconductor device layer 112. The metallization layers can be electrically coupled to each other through one or more conductive vias. In some embodiments, the electrical contact 116 can be a solder bump, a C4 (controlled collapse chip connection) bump, etc.

[0029] The bonding structure 104 bonds the carrier substrate 102 to the front side interconnect structure 110. The bonding structure 104 may also be referred to as a bonding layer 104. The bonding structure 104 may be formed of any material to properly bond the carrier substrate 102 and the front side interconnect structure 110. The bonding structure 104 includes a dielectric layer 106 and an array of thermal vias 108.

[0030] In some embodiments, the dielectric layer 106 is made of silicon oxide, silicon nitride, silicon carbide, a low-k dielectric (e.g., carbon-doped oxide), a low-k dielectric or an extremely low-k (ELK) dielectric (e.g., porous carbon-doped silicon dioxide), a polymer (e.g., epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), etc.), or a combination thereof. In yet other embodiments, the dielectric material in the dielectric layer 106 and the dielectric layer in the front-side interconnect structure 110 are different. For example, the dielectric layer in the front-side interconnect structure 110 may have a dielectric constant that is less than that of the dielectric layer 106. In some embodiments, the total thickness of the dielectric layer 106 is between about 1 μm and about 10 μm.

[0031] Thermal vias 108 extend from the front-side interconnect structure 110 to the carrier substrate 102. Thermal vias 108 provide a heat conduction path through the dielectric layer 106. In this way, heat generated by the underlying hot spot region can be quickly transferred to the thermal vias 108 and subsequently to the carrier substrate 102. In one embodiment, the carrier substrate 102 is made of single crystal silicon (Si), which has a thermal conductivity of approximately 148 W / m·K, and can quickly and effectively dissipate heat generated by the hot spot region in the semiconductor device layer 112. As a result, the device performance, reliability, and / or life of the IC structure can be improved.

[0032] The thermal via 108 is made of a high kappa (κ) material. In the context of the present disclosure, the term "high kappa material" refers to a material having a thermal conductivity of not less than 10 W / m·K (watts per meter Kelvin). High kappa materials are particularly effective in conducting heat and are also referred to as thermally conductive materials. This means that the thermal vias 108 made of high kappa materials allow heat to pass through them quickly and efficiently. As an example and not a limitation, the thermal vias 108 may include a conductive material, such as cobalt, titanium, tungsten, copper, aluminum, tantalum, titanium nitride, tantalum nitride, gold, silver, another metal, a metal alloy, or a combination thereof. Since the thermal via 108 does not conduct electrical signals or electricity, it is not necessarily conductive, so the thermal via 108 may include other high kappa materials, such as aluminum nitride (AlN), hexagonal boron nitride (h-BN), graphene, transition metal disulfide (TMD) (e.g., MoS2, MoSe2, WS2, or WSe2), or any other suitable high kappa material. For aluminum nitride, it exhibits a high thermal conductivity of about 370 W / m·K. For graphene, it exhibits a high thermal conductivity of more than 3500 W / m·K. For TMD, its thermal conductivity is typically more than 10 W / m·K. For h-BN, it is a layered structure in a crystalline form similar to graphite, exhibiting an in-plane thermal conductivity of more than 390 W / m·K at room temperature. In comparison, amorphous BN (a-BN) is in an amorphous form and only exhibits an in-plane thermal conductivity of about 3 W / m·K, and is not considered a high kappa material in the context of the present disclosure. In one example, the dielectric layer 106 is formed of a-BN, and the thermal via 108 is formed of h-BN.

[0033] In some embodiments, to further facilitate heat dissipation, dielectric layer 106 is also formed of a high kappa dielectric material. In some embodiments, dielectric layer 106 is a high kappa dielectric layer having a thermal conductivity greater than that of silicon dioxide but less than that of the material of thermal vias 108. In some embodiments, bonding layer 104 is a high kappa dielectric layer comprising one or more of a nitride, a metal oxide, or a carbide. In some embodiments, bonding layer 104 comprises one or more of AlN, BN, Y2O3, YAG, Al2O3, BeO, SiC, graphene, or any other suitable high kappa material.

[0034] In various embodiments, the high kappa material of dielectric layer 106 can be arranged in any suitable crystal structure, including, for example, cubic, hexagonal, tetragonal, orthorhombic, monoclinic, or triclinic crystal structures. In addition, the high kappa material of dielectric layer 106 can have any suitable crystallinity, including, for example, single crystal, polycrystalline, or amorphous.

[0035] Using a bonding structure 104 having a high kappa material in at least the thermal via 108 or in both the thermal via 108 and the dielectric layer 106 can help improve the thermal performance of the semiconductor device 100, for example, by preventing or reducing performance degradation of the semiconductor device (e.g., within the semiconductor device layer 112) due to heat. The high kappa material used in the bonding structure 104 can improve heat dissipation, which can protect the semiconductor device layer 112 from thermal degradation, and thus can improve the performance and reliability of the chip or semiconductor device 100.

[0036] Because the high capa joint structure 104 is disposed on the front side of the semiconductor device 100 for heat dissipation, in some embodiments, there is no need to have external electrical contacts on the front side of the semiconductor device 100 to transmit signals. Therefore, the front side of the semiconductor device 100 may be free of electrical contacts, such as solder bumps, C4 connectors, etc.

[0037] Figure 2A-2D Some embodiments of arrangements of arrays of thermal vias 108 are shown in top views of the bonding structure 104. Each figure shows a different configuration of thermal vias 108 within the bonding structure 104, providing different shape and spacing options to meet different thermal management requirements in semiconductor applications. Figure 2A An embodiment is shown of an array of circular thermal vias 108 embedded in a dielectric layer 106. The array is arranged in a uniform grid-like pattern with the thermal vias arranged in rows and columns. Figure 2B Another embodiment of an array of circular thermal vias 108 embedded in a dielectric layer 106 is shown. Figure 2A Unlike the uniform grid-like pattern in FIG. 1 , the array features an alternating arrangement with each subsequent row of thermal vias 108 shifted horizontally. This offset creates a staggered configuration. Figure 2C The thermal vias 108 are shown to be square (or rectangular) and are similar to Figure 2A The square through holes are closely packed, providing a high through hole area ratio, which can enhance the heat transfer capability of the bonding structure 104. Figure 2D Another square thermal via configuration is shown. Figure 2B similar, Figure 2D The array in has an alternating arrangement of features, wherein each subsequent row of thermal vias 108 is shifted horizontally. This offset creates a staggered configuration. In each of the illustrated embodiments, the thermal vias 108 can have a critical dimension (CD) ranging from about 1 μm to about 3 μm and a center-to-center distance (or pitch) P ranging from about 1 μm to about 10 μm.

[0038] Figure 3 According to some embodiments Figure 1 Detailed cross-sectional view of region 120 of semiconductor device 100. Figure 3As shown, the various layers in region 120 include a semiconductor device layer 112, a front-side interconnect structure 110 disposed above the semiconductor device layer 112, and a back-side interconnect structure 114 disposed below the semiconductor device layer 112. For clarity, Figure 3 It is simplified to better understand the inventive concepts of the present disclosure. Additional features may be added in various layers of the semiconductor device 100 , and some of the features described may be replaced, modified, or eliminated in other embodiments of the semiconductor device 100 .

[0039] The semiconductor device layer 112 includes devices (eg, transistors, resistors, capacitors, and / or inductors) and / or device components (eg, doped wells, gate structures, and / or source / drain features). Figure 3 In the illustrated embodiment, the semiconductor device layer 112 includes a substrate 160, a doped region 162 (e.g., an n-well and / or a p-well) disposed in the substrate 160, an isolation feature 164, and a transistor T. In the depicted embodiment, the transistor T includes a suspended channel layer (nanostructure) 166 and a gate structure 168 disposed between source / drain epitaxial features 170, wherein the gate structure 198 encapsulates and / or surrounds the suspended channel layer 166. Each gate structure 168 has a metal gate stack formed by a gate electrode 174 disposed on a gate dielectric layer 176, with gate spacers 178 disposed along sidewalls of the metal gate stack.

[0040] The interconnect structures 110 and 114 electrically couple various devices and / or components of the semiconductor device layer 112 so that the various devices and / or components can operate in accordance with the design requirements of the memory device. Each of the interconnect structures 110 and 114 may include one or more interconnect layers. In the depicted embodiment, the front-side interconnect structure 110 includes a contact interconnect layer (CO level), a via zero interconnect layer (V0 level), a metal zero interconnect layer (M0 level), a via 1 interconnect layer (V1 level), a metal 1 interconnect layer (M1 level), a via 2 interconnect layer (V2 level), a metal 2 interconnect layer (M2 level), and so on, up to a metal X-1 interconnect layer (M0 level). X-1 Layer), through hole X-1 interconnect layer (V X-1 level), and the metal X interconnect layer (M X In some embodiments, X is an integer from 1 to 10. V0 layer, V0 layer, M0 layer, V1 layer, M1 layer, V2 layer, M2 layer, ... M X Each of the levels may be referred to as a metal level. A metal line formed at the M0 level may be referred to as an M0 metal line. Similarly, metal lines formed at the V1 level, the M1 level, the V2 level, the M2 level, ... M X-1 Level, V X-1 Level and M XThe vias or metal lines formed at the level can be called V1 vias, M1 metal lines, V2 vias, M2 metal lines...M X-1 Metal wire, V X-1 Through hole and M X Metal lines. Each level of the front-side interconnect structure 110 includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., interlayer dielectric (ILD) layers or intermetal dielectric (IMD) layers). The dielectric layers of the front-side interconnect structure 110 are collectively referred to as dielectric structures 180. In some embodiments, conductive features at the same level (e.g., M0 level) of the front-side interconnect structure 110 are formed simultaneously. In some embodiments, the conductive features at the same level of the front-side interconnect structure 110 have top surfaces that are substantially flat to each other and / or bottom surfaces that are substantially planar to each other.

[0041] exist Figure 3 In the illustrated embodiment, the CO level includes a source / drain contact MD disposed in the dielectric structure 180. The source / drain contact MD may be formed on and in direct contact with a silicide layer disposed directly on the source / drain epitaxial component 170. The V0 level includes a gate via VG disposed on the gate structure and a source / drain contact via VD disposed on the source / drain contact MD, wherein the gate via VG connects the gate structure to the M0 metal line, and the source / drain contact via VD connects the source / drain contact MD to the M0 metal line. In some embodiments, the V0 level may further include a docking contact disposed in the dielectric structure 180. The V1 level includes a V1 via disposed in the dielectric structure 180, wherein the V1 via connects the M0 metal line to the M1 metal line. The M1 level includes an M1 metal line disposed in the dielectric structure 180. The V2 level includes a V2 via disposed in the dielectric structure 180, wherein the V2 via connects the M1 metal line to the M2 metal line. The M2 level includes the M2 metal lines disposed in the dielectric structure 180. Similarly, V X The level includes a V X Through hole, where V X Through hole M X-1 Metal wire connected to M X Metal lines. Not all metal lines in the front-side interconnect structure 110 are functional metal lines (represented as metal lines 182F) configured to carry electrical signals and / or power. The front-side interconnect structure 110 may also include non-functional metal lines (represented as metal lines 182D) configured as dummy metal lines. The dummy metal lines are electrically floating. In semiconductor structures, dummy metal lines help maintain uniform surface topography during chemical mechanical polishing (CMP) processes and also help distribute heat across the chip, thereby avoiding hot spots that affect the reliability and performance of semiconductor devices. Figure 3The schematic diagram shows that the metal lines in the same metal interconnect layer can have functional metal lines 182F and non-functional metal lines 182D. As discussed in further detail below, in some embodiments, some thermal vias 108 ( Figure 1 ) may extend downward to land on some non-functional metal lines 182D. In some further embodiments, some thermal vias 108 may extend downward to land on different metal interconnect layers (e.g., M X-1 Tier and M X The non-functional metal line 182D in the layer (level) is formed so that the bottom surfaces of different thermal vias 108 may be uneven.

[0042] In the depicted embodiment, the backside interconnect structure 114 includes a backside via zero interconnect layer (BV0 level), a backside metal zero layer (BM0 level), a backside via one interconnect layer (BV1 level), a backside metal one interconnect layer (BM1 level), and so on, all the way to a backside metal Y interconnect layer (BM Y In some embodiments, Y is an integer in the range of 1 to 10. BV0 level, BM0 level, BV1 level, BM1 level ... and BM Y Each of the levels may be referred to as a metal level. A metal line formed at the BM0 level may be referred to as a BM0 metal line. Similarly, metal lines formed at the BV0 level, the BV1 level, the BM1 level, ... BM Y The vias or metal lines formed at the levels may be referred to as BV0 vias, BV1 vias, BM1 metal lines, and BM Y Metal lines. Each layer of the backside interconnect structure 114 includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an ILD layer or an IMD layer). The dielectric layers of the backside interconnect structure 114 are collectively referred to as a backside dielectric structure 184. In some embodiments, the conductive features at the same level (e.g., the BM0 level) of the backside interconnect structure 114 may be formed simultaneously. In some embodiments, the top surfaces of the conductive features at the same level of the backside interconnect structure 114 are substantially coplanar with each other and / or the bottom surfaces of the conductive features at the same level of the backside interconnect structure 114 are substantially coplanar with each other. Figure 3In the illustrated embodiment, the BV0 level includes a via BV0 formed below the semiconductor device layer 112. For example, the via BV0 may include one or more backside source / drain vias formed directly below the source / drain epitaxial components 170 of the semiconductor device layer 112 and coupled to these source / drain epitaxial components 170 through the silicide layer. The BM0 level includes a BM0 metal line formed below the BV0 level. The backside source / drain via connects the source / drain epitaxial components 170 to the BM0 metal line. The BV1 level includes a BV1 via disposed in the backside dielectric structure 184, wherein the BV1 via connects the BM0 metal line to the BM1 metal line. The BM1 level includes a BM1 metal line formed below the BV1 level. Similarly, the BV Y-1 The level includes a BV disposed in the backside dielectric structure 184 Y-1 Through hole, where BV Y-1 Through hole will BM Y-1 Metal wire connected to BM Y Metal wire. Figure 3 Not shown, but BM Y The metal wire is also coupled to an electrical contact 116 ( Figure 1 ).

[0043] Figure 4A to Figure 4J-1 A method of manufacturing a semiconductor device 100 according to some embodiments is shown. Figure 4A As shown, the method includes forming a first dielectric layer 106-1 on a semiconductor device structure, which may be referred to as a device wafer 200. The device wafer 200 includes a semiconductor device layer 112 and a frontside interconnect structure 110, which may be the same or substantially the same as previously described herein.

[0044] The device wafer 200 also includes a substrate 202. The substrate 202 can be any suitable substrate. In some embodiments, the substrate 202 is a semiconductor substrate, such as a silicon substrate. The substrate 202 can be a semiconductor substrate, such as a bulk semiconductor, etc., which can be doped (for example, with a p-type or n-type dopant) or undoped. The semiconductor material of the substrate 202 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium phosphide and / or gallium indium arsenic phosphide; or combinations thereof. Other substrates, such as single-layer, multi-layer or gradient substrates can be used. The semiconductor device layer 112 can be formed on and / or in the substrate 202. The front-side interconnect structure 110 is formed on the semiconductor device layer 112 and can be Figure 3 Shown and referenced Figure 3 The structure to be described.

[0045] The first dielectric layer 106-1 may form a first portion or a first sublayer of the dielectric layer 104 of the bonding structure 104 of the semiconductor device 100. The first dielectric layer 106-1 may be formed by any suitable technique. For example, in some embodiments, the first dielectric layer 106-1 is formed by depositing a non-high kappa dielectric material or a high kappa dielectric material. In some embodiments, the first dielectric layer 106-1 is a dielectric layer deposited by physical vapor deposition (PVD), chemical vapor deposition, atomic layer deposition (ALD), plasma enhanced CVD (PECVD), or any suitable deposition technique. In some embodiments, the thickness of the first dielectric layer 106-1 is about half of the total thickness of the dielectric layer 106 of the bonding structure 104, for example, between about 0.5 μm and about 5 μm. In some other embodiments, the first dielectric layer 106-1 may have a thickness less than about half or more than about half of the total thickness of the dielectric layer 106 of the bonding structure 104. The exact thickness of the first dielectric layer 106 - 1 is to facilitate proper bonding between adjacent structures (eg, bonding with the second dielectric layer 106 - 2 which will be discussed in further detail below).

[0046] like Figure 4B As shown, the method includes forming a plurality of through-hole trenches 204 in the first dielectric layer 106-1. The through-hole trenches 204 extend through the first dielectric layer 106-1 and expose a portion of the top surface of the front-side interconnect structure 110. In some embodiments, forming the through-hole trenches 204 includes forming a patterned mask layer (not shown) having an opening therein, the opening exposing a portion of the top surface of the first dielectric layer 106-1, and using the patterned mask layer as an etching mask to etch the first dielectric layer 106-1. The patterned mask layer can be formed using a photolithography process, which can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), other suitable processes or combinations thereof. In some embodiments, the patterned mask layer is a patterned hard mask layer (e.g., a silicon nitride layer). In some embodiments, the patterned mask layer is a patterned photoresist layer. Etching can be a dry etching process, a wet etching process, other etching processes or combinations thereof. In some embodiments, the etching process is an isotropic dry etching. Due to the loading effect of the etching process, the via trench 204 may have a tapered sidewall, so that the top opening of the via trench 204 is larger than its bottom opening. After forming the via trench 204, the patterned mask layer may be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma, etc.).

[0047] like Figure 4CAs shown, the method includes depositing a high kappa material 206 to fill the via trench 204 and cover the top surface of the first dielectric layer 106-1. The high kappa material 206 can be a conductive material, such as cobalt, titanium, tungsten, copper, aluminum, tantalum, titanium nitride, tantalum nitride, gold, silver, another metal, a metal alloy, or a combination thereof. Alternatively, the high kappa material 206 can include a non-conductive high kappa material, such as aluminum nitride (AlN), hexagonal boron nitride (h-BN), graphene, transition metal disulfide (TMD) (e.g., MoS2, MoSe2, WS2, or WSe2), or any other suitable high kappa material. In some embodiments, a liner (not shown) is conformally deposited on the device wafer 200 before depositing the bulk high kappa material 206 that fills the remainder of the via trench 204. The liner acts as a barrier to separate the high kappa material 206 from the dielectric structure 180 ( Figure 3 ). Therefore, the liner is also called a barrier layer. The barrier layer prevents the material (e.g., copper) in the high kappa material 206 from diffusing into the dielectric structure 180 in the first dielectric layer 106-1 and the front-side interconnect structure 110. In some embodiments, the barrier layer can be made of TiN or TaN.

[0048] like Figure 4D As shown, the method includes performing a planarization process, such as a chemical mechanical planarization (CMP) process or a mechanical polishing process, to remove excess portions of the high kappa material 206, thereby forming a thermal via in the first dielectric layer 106-1. The thermal via formed in the first dielectric layer 106-1 is represented as a first thermal via 108-1. The first thermal via 108-1 inherits the shape of the via trench 204. Due to the larger top opening and smaller bottom opening of the via trench 204, the first thermal via 108-1 has a tapered sidewall and a larger top width and a smaller bottom width. In the illustrated embodiment, the top surface of the first dielectric layer 106-1 is exposed.

[0049] like Figure 4EAs shown, the method includes forming a second dielectric layer 106-2 on a carrier substrate 102 (such as a semiconductor wafer). In some embodiments, the carrier substrate 102 can be a single crystal silicon (Si) wafer, an amorphous Si wafer, a gallium arsenide (GaAs) wafer, or any other semiconductor wafer. The second dielectric layer 106-2 can form a second portion or a second sublayer of the dielectric layer 106 of the bonding structure 104 of the semiconductor device 100. The second dielectric layer 106-2 can be formed by any suitable technique. For example, in some embodiments, the second dielectric layer 106-2 is formed by depositing a non-high kappa dielectric material or a high kappa dielectric material. In some embodiments, the second dielectric layer 106-2 is a dielectric layer deposited by physical vapor deposition (PVD), chemical vapor deposition, atomic layer deposition (ALD), plasma enhanced CVD (PECVD), or any suitable deposition technique. In some embodiments, the material composition in the first dielectric layer 106-1 and the second dielectric layer 106-2 is the same. Alternatively, for certain specific application requirements, the material composition in the first dielectric layer 106-1 and the second dielectric layer 106-2 may be different. In some embodiments, the thickness of the second dielectric layer 106-2 is about half of the total thickness of the dielectric layer 106 of the bonding structure 104, for example, between about 0.5 μm and about 5 μm. In some other embodiments, the thickness of the second dielectric layer 106-2 may be greater than the thickness of the first dielectric layer 106-1 or less than the thickness of the first dielectric layer 106-1. The exact thickness of the second dielectric layer 106-2 is to promote proper bonding between the first dielectric layer 106-1 and the second dielectric layer 106-2.

[0050] like Figure 4FAs shown, the method includes forming a plurality of through-hole trenches 208 in the second dielectric layer 106-2. The through-hole trenches 208 extend through the second dielectric layer 106-2 and expose a portion of the top surface of the carrier substrate 102. In some embodiments, forming the through-hole trenches 208 includes forming a patterned mask layer (not shown) having an opening therein, the opening exposing a portion of the top surface of the second dielectric layer 106-2, and etching the second dielectric layer 106-2 using the patterned mask layer as an etching mask. The patterned mask layer can be formed using a photolithography process, which can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), other suitable processes or combinations thereof. In some embodiments, the patterned mask layer is a patterned hard mask layer (e.g., a silicon nitride layer). In some embodiments, the patterned mask layer is a patterned photoresist layer. Etching can be a dry etching process, a wet etching process, other etching processes or combinations thereof. In some embodiments, the etching process is an isotropic dry etch. Due to the loading effect of the etching process, the via trench 208 may have a tapered sidewall, so that the top opening of the via trench 208 is larger than its bottom opening. After the via trench 208 is formed, the patterned mask layer may be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma, etc.).

[0051] like Figure 4GAs shown, the method includes depositing a high kappa material 210 to fill the via trench 208 and cover the top surface of the second dielectric layer 106-2. The high kappa material 210 can be a conductive material, such as cobalt, titanium, tungsten, copper, aluminum, tantalum, titanium nitride, tantalum nitride, gold, silver, another metal, a metal alloy, or a combination thereof. Alternatively, the high kappa material 210 may include a non-conductive high kappa material, such as aluminum nitride (AlN), hexagonal boron nitride (h-BN), graphene, transition metal disulfide (TMD) (e.g., MoS2, MoSe2, WS2, or WSe2), or any other suitable high kappa material. In some embodiments, a liner (not shown) is conformally deposited on the workpiece before depositing the bulk high kappa material 210 that fills the remainder of the via trench 208. The liner serves as a barrier that separates the high kappa material 210 from direct contact with the second dielectric layer 106-2 and the carrier substrate 102. Therefore, the liner is also referred to as a barrier layer. The barrier layer prevents the material in the high kappa material 210 from diffusing into the second dielectric layer 106-2 and the carrier substrate 102. In some embodiments, the barrier layer can be made of TiN or TaN. In some embodiments, the material composition in the high kappa material 206 and the high kappa material 210 is the same. Alternatively, the material composition in the high kappa material 206 and the high kappa material 210 can be different according to some specific application requirements. For example, if you don't care too much about the material composition in the high kappa material 210 diffusing into the carrier substrate 102, the selection restrictions on the high kappa material 210 can be less. In some embodiments, since you don't care too much about the material composition in the high kappa material 210 diffusing into the carrier substrate 102, there is no barrier layer under the high kappa material 210, but there is a barrier layer under the high kappa material 206.

[0052] like Figure 4H As shown, the method includes performing a planarization process, such as a chemical mechanical planarization (CMP) process or a mechanical polishing process, to remove excess portions of the high kappa material 210, thereby forming a thermal via in the second dielectric layer 106-2. The thermal via formed in the second dielectric layer 106-2 is represented as a second thermal via 108-2. The second thermal via 108-2 inherits the shape of the via trench 208. Due to the larger top opening and smaller bottom opening of the via trench 208, the second thermal via 108-2 has a tapered sidewall and a larger top width and a smaller bottom width. In the illustrated embodiment, the top surface of the second dielectric layer 106-2 is exposed.

[0053] like Fig. 4IAs shown, a carrier substrate 102 is bonded to a device wafer 200 to form a semiconductor device 100. During backside processing of the device wafer 200, the carrier substrate 102 protects the frontside interconnect structure 110. The device wafer 200 and the carrier substrate 102 can be bonded to each other by any suitable technique. In some embodiments, the carrier substrate 102 is bonded to the device wafer 200 by an ambient bonding process (e.g., using ambient temperature or pressure process parameters in a bonding tool). In some embodiments, the carrier substrate 102 is bonded to the device wafer 200 by a vacuum bonding process (e.g., in a bonding tool with vacuum pressure). However, the embodiments are not limited thereto, and in various embodiments, the bonding of the carrier substrate 102 to the device wafer 200 can be performed by any suitable bonding process. In the bonding process, the second dielectric layer 106-2 on the carrier substrate 102 is bonded to the first dielectric layer 106-1 formed on the device wafer 200, and the second thermal via 108-2 formed in the second dielectric layer 106-2 is bonded to the first thermal via 108-1 formed in the first dielectric layer 106-1. Since the bonding interface between the dielectric layer and the thermal via is different, the bonding process is also called a hybrid bonding process.

[0054] After the bonding process, the first dielectric layer 106-1 and the second dielectric layer 106-2 together form the dielectric layer 106, the pair of the first thermal vias 108-1 and the second thermal vias 108-2 together form the thermal vias 108, and the array of the dielectric layer 106 and the thermal vias 108 together form the bonding structure 104. As described above, the thickness H1 of the first dielectric layer 106-1 (or the height of the first thermal via 108-1) can be equal to the thickness H2 of the second dielectric layer 106-2 (or the height of the second thermal vias 108-2). Alternatively, the thickness H1 can be greater than or less than the thickness H2, depending on the specific performance requirements. Typically, in the bonding process, the center lines of the first thermal vias 108-1 and the second thermal vias 108-2 in the corresponding pairs are aligned. Due to the tapered sidewalls of the first thermal vias 108-1 and the second thermal vias 108-2, each thermal via has a middle portion that is wider than the top and bottom portions. If the joint overlap offset occurs, the center lines of the first thermal via 108-1 and the second thermal via 108-2 in the corresponding pair may be horizontally offset and produce a step profile along the sidewalls of the thermal vias, such as Fig. 4I The enlarged area 188 is shown.

[0055] like Figure 4J-1 As shown, the semiconductor device 100 is further formed by forming a backside interconnect structure 114 on the back side of the semiconductor device layer 112. The backside interconnect structure 114 can be connected to the backside of the semiconductor device layer 112. Figure 3The backside interconnect structure 114 may be the same or similar as described above. In some embodiments, the formation of the backside interconnect structure 114 includes forming a plurality of conductive features that are operable to transmit electrical signals to or receive electrical signals from semiconductor devices in the semiconductor device layer 112. For example, the backside interconnect structure 114 may include one or more backside power rails, metallization layers, conductive vias, etc. In some embodiments, the formation of the backside interconnect structure 114 includes forming an insulating layer on or around the conductive features of the backside interconnect structure 114. In some embodiments, one or more portions of the substrate 202 may be at least partially removed, for example, as part of forming the backside interconnect structure 114. In some embodiments, the backside interconnect structure 114 is formed in or at least partially includes a portion of the substrate 202. For example, in some embodiments, the conductive features of the backside interconnect structure 114 (e.g., backside power rails, metallization layers, conductive vias, etc.) may be formed within the substrate 202. The conductive features of the backside interconnect structure 114 may be formed to extend through the substrate 202 or insulating layer and may contact conductive regions or semiconductor regions of semiconductor devices in the semiconductor device layer 112 (eg, gate contacts of transistors, source / drain regions of transistors, etc.).

[0056] In addition, if Figure 4J-1 As shown, the semiconductor device 100 is further formed by forming an electrical contact 116. The electrical contact 116 can be formed by any suitable technique, including by deposition, welding, placing solder balls, etc. The electrical contact 116 can be formed on or in contact with a metallization layer of the backside interconnect structure 114, which can include power contacts, input / output contacts, or any other contacts for receiving or providing electrical signals and / or power. In various embodiments, any number of electrical contacts can be included in the semiconductor device 100, and the electrical contacts can be coupled to a variety of different conductive features or metallization paths, for example, to electrically couple to semiconductor devices in the semiconductor device layer 112.

[0057] In such Figure 4J-1 In the illustrated embodiment, the thermal vias 108 each extend from a top surface of the frontside interconnect structure 110 to a surface of the carrier substrate 102 facing the frontside interconnect structure 100 , thereby facilitating heat dissipation from the semiconductor device layer 112 and the frontside interconnect structure 110 to the carrier substrate 102 . Figure 4J-2 , Figure 4J-3 and Figure 4J-4 Some alternative embodiments of thermal vias 108 in semiconductor device 100 are shown. Figure 4J-2 As shown, the second thermal vias 108-2 each extend further upward into the carrier substrate 102, which is formed by etching in the process ( Figure 4F) during the thermal via trench 208 is extended into the carrier substrate 102. By partially embedding the second thermal via 108-2 into the carrier substrate 102, the contact area between the second thermal via 108-2 and the carrier substrate 102 is enlarged, thereby more effectively dissipating heat into the carrier substrate 102. Since the additional portion extends into the carrier substrate 102, the second thermal via 108-2 may have a greater height than the first thermal via 108-1. The portion extending in the carrier substrate 102 may have a height H3 that is about 10% to about 30% of the total height of the thermal via 108.

[0058] like Figure 4J-3 As shown, the first thermal vias 108-1 each further extend downward into the front side interconnect structure 110, which is formed by etching in the process ( Figure 4B ) during which the via trench 204 is extended to the dielectric structure 180 of the front-side interconnect structure 110 ( Figure 3 ). By partially embedding the first thermal via 108-1 in the front-side interconnect structure 110, the contact area between the first thermal via 108-1 and the front-side interconnect structure 110 is enlarged, so that heat is more effectively dissipated from the semiconductor device layer 112 and the front-side interconnect structure 110. The portion extending in the front-side interconnect structure 110 may have a height H4, which is about 10% to about 30% of the total height of the thermal via 108. In various embodiments, the height H4 may be equal to, less than, or greater than the height H3 according to specific application requirements.

[0059] like Figure 4J-4 As shown, the non-functional metal line 182D ( Figure 3 ) can extend downward to directly contact the corresponding non-functional metal line 182D below, which is achieved by etching the first thermal vias 108-1 directly above the first thermal vias 108-1 in the etching process ( Figure 4B ) during the thermal conduction process. The direct contact between the non-functional metal line 182D and the first thermal via 108-1 allows heat to be dissipated more efficiently from the semiconductor device layer 112 and the front-side interconnect structure 110. Depending on the depth of the non-functional metal line 182D (e.g., Figure 3 As shown, the top non-functional metal line 182D can be X and / or M X-1 In the metal layer), some first thermal vias 108-1 may extend deeper into the front-side interconnect structure 110 than some other first thermal vias 108-1 (for example, H4-2>H4-1). In addition, the front-side interconnect structure 110 is located at the functional metal line 182F ( Figure 3) may land on the top surface of the front-side interconnect structure 100 without extending into it. Therefore, the bottom surfaces of the thermal vias 108 may be non-coplanar. In contrast, the top surfaces of the thermal vias 108 are substantially coplanar.

[0060] Figure 5A-5D-1 An alternative method of manufacturing semiconductor device 100 is shown. In addition to removing excess portions of high kappa material 206 to expose first dielectric layer 106-1 ( Figure 4D ) Figure 5A , after the planarization process, a thin layer of high kappa material 206 remains to cover the first dielectric layer 106-1. The thin layer is represented as the first thermal sheet 109-1. Similarly, except that the excess portion of the high kappa material 210 is removed to expose the second dielectric layer 106-2 ( Figure 4H ) Figure 5B , a thin layer of high kappa material 210 remains after the planarization process to cover the second dielectric layer 106-2. The thin layer is denoted as second thermal sheet 109-2.

[0061] like Figure 5C As shown, the carrier substrate 102 is bonded to the device wafer 200 to form the semiconductor device 100. The first heat slug 109-1 is bonded to the second heat slug 109-2 to form the heat slug 109. The heat slug 109 is interposed between the first dielectric layer 106-1 and the second dielectric layer 106-2, and separates the first dielectric layer 106-1 from the second dielectric layer 106-2 to prevent direct contact. The heat slug 109 provides a larger thermally conductive interface than the bonded thermal vias, and promotes heat dissipation from the semiconductor device layer 112 and the front-side interconnect structure 110 to the carrier substrate 102.

[0062] like Figure 5D-1 As shown, the semiconductor device 100 is further formed by forming a backside interconnect structure 114 on the back side of the semiconductor device layer 112. The backside interconnect structure 114 can be connected to the backside of the semiconductor device layer 112. Figure 3 The semiconductor device 100 is further formed by forming an electrical contact 116. The electrical contact 116 may be formed by any suitable technique, including by deposition, soldering, placing solder balls.

[0063] Figure 5D-2 , Figure 5D-3 and Figure 5D-4 is similar to Figure 4J-2 , Figure 4J-3 and Figure 4J-4 An alternative embodiment as shown in , but with an additional heat sheet 109. Figure 5D-2 As shown, the second thermal vias 108-2 each extend further upward into the carrier substrate 102, which is formed by etching in the process ( Figure 4F) during the process of extending the through-hole trench 208 into the carrier substrate 102. By partially embedding the second thermal via 108-2 into the carrier substrate 102, the contact area between the second thermal via 108-2 and the carrier substrate 102 is enlarged, thereby more effectively dissipating heat into the carrier substrate 102. Since the additional portion extends into the carrier substrate 102, the second thermal via 108-2 may have a greater height than the first thermal via 108-1. The portion extending in the carrier substrate 102 may have a height H3 that is about 10% to about 30% of the total height of the first thermal via 108-1 and the second thermal via 108-2.

[0064] like Figure 5D-3 As shown, the first thermal vias 108-1 each further extend downward into the front side interconnect structure 110, which is formed by etching in the process ( Figure 4B ) during the process of extending the through-hole trench 204 into the dielectric layer of the front-side interconnect structure 110. By partially embedding the first thermal via 108-1 into the front-side interconnect structure 110, the contact area between the first thermal via 108-1 and the front-side interconnect structure 110 is increased, thereby more effectively dissipating heat from the semiconductor device layer 112 and the front-side interconnect structure 110. The portion extending in the front-side interconnect structure 110 may have a height H4, which is about 10% to about 30% of the total height of the first thermal via 108-1 and the second thermal via 108-2. In various embodiments, the height H4 may be equal to, less than, or greater than the height H3 according to specific application requirements.

[0065] like Figure 5D-4 As shown, the non-functional metal line 182D ( Figure 3 ) can extend downward to directly contact the corresponding non-functional metal line 182D below, which is achieved by etching in the process ( Figure 4B ) during the thermal conduction process. The direct contact between the non-functional metal line 182D and the first thermal via 108-1 allows heat to be dissipated more efficiently from the semiconductor device layer 112 and the front-side interconnect structure 110. Depending on the depth of the non-functional metal line 182D (e.g., Figure 3 As shown, the top non-functional alloy wire 182D can be X and / or M X-1 In the metal layer), some first thermal vias 108-1 may extend deeper into the front-side interconnect structure 110 than some other first thermal vias 108-1 (e.g., H4-2>H4-1). In addition, in the front-side interconnect structure 110, the functional metal line 182F ( Figure 3) may land on the top surface of the front-side interconnect structure 110 without extending into it. Therefore, the bottom surfaces of the first thermal vias 108-1 may be non-coplanar. In comparison, the bottom surfaces of the second thermal vias 108-2 (placed upside down) are substantially coplanar.

[0066] Embodiments of the present disclosure have several advantageous features: By forming a bonding structure that provides a thermally conductive via, the thermal performance of a semiconductor device is improved, thereby preventing potential overheating, helping to extend the life of the device and maintaining the operating efficiency of the device.

[0067] In one exemplary aspect, the present disclosure relates to a method for forming a semiconductor device. The method includes forming a first dielectric layer on a semiconductor structure, the semiconductor structure including a semiconductor device layer having a front side and a back side, a first substrate disposed on the back side of the semiconductor device layer, and a first interconnect structure disposed on the front side of the semiconductor device layer, forming a plurality of first through holes through the first dielectric layer and extending to the first interconnect structure, the first through holes having a first thermally conductive material having a thermal conductivity greater than about 10 W / m·K, forming a second dielectric layer on a second substrate, forming a plurality of second through holes through the second dielectric layer and extending to the second substrate, the second through holes having a second thermally conductive material having a thermal conductivity greater than about 10 W / m·K, bonding the second dielectric layer to the first dielectric layer, bonding the second through holes to the first through holes, and forming a second interconnect structure on the back side of the semiconductor device layer. In some embodiments, the formation of the second interconnect structure includes thinning or removing the first substrate. In some embodiments, the formation of the first through hole includes: patterning the first dielectric layer to form a plurality of first through hole trenches; depositing a first thermally conductive material in the first through hole trenches and on the first dielectric layer; and performing a first planarization process to partially remove the first thermally conductive material, so that the portion of the first thermally conductive material remaining in the first through hole trench forms the first through hole. In some embodiments, the formation of the second through hole includes: patterning the second dielectric layer to form a plurality of second through hole trenches; depositing a second thermally conductive material in the second through hole trenches and on the second dielectric layer; and performing a second planarization process to partially remove the second thermally conductive material, so that the portion of the second thermally conductive material remaining in the second through hole trench forms the second through hole. In some embodiments, the first thermally conductive material and the second thermally conductive material are conductive materials. In some embodiments, the first thermally conductive material and the second thermally conductive material are non-conductive materials. In some embodiments, the first thermally conductive material and the second thermally conductive material have different material compositions. In some embodiments, the first dielectric layer and the second dielectric layer are made of a dielectric material having a thermal conductivity greater than about 10 W / m·K. In some embodiments, the first dielectric layer and the second dielectric layer are made of a dielectric material having a thermal conductivity less than about 10 W / m·K. In some embodiments, the second via is partially embedded in the second substrate.

[0068] In another exemplary aspect, the present disclosure relates to a method for forming a semiconductor device. The method includes forming a first interconnect structure on a first side of a semiconductor device layer, forming a bonding structure connecting the first interconnect structure and a substrate, the bonding structure including a dielectric layer and an array of thermally conductive pillars extending through the dielectric layer, the thermally conductive pillars being electrically isolated from the semiconductor device layer, and forming a second interconnect structure on a second side of the semiconductor device layer, the second side of the semiconductor device layer facing away from the first side of the semiconductor device layer. In some embodiments, the thermally conductive pillars each have a middle portion that is wider than the top and bottom portions. In some embodiments, the thermally conductive pillars each have a circular cross-section. In some embodiments, the thermally conductive pillars each have a square cross-section. In some embodiments, the bonding structure also includes a heat sheet that divides the dielectric layer into an upper portion that is thermally coupled to the substrate and a lower portion that is thermally coupled to the first interconnect structure. In some embodiments, the dielectric layer is made of a thermally conductive dielectric material having a thermal conductivity greater than about 10 W / m·K.

[0069] In another exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor device layer, a front-side interconnect structure above the semiconductor device layer, a back-side interconnect structure below the semiconductor device, and a substrate bonded to the front-side interconnect structure by a bonding structure. The bonding structure includes a dielectric layer and a plurality of thermal pillars extending through the dielectric layer. The thermal pillars have a first end connected to the front-side interconnect structure and a second end connected to the substrate. In some embodiments, the thermal pillars are arranged in rows and columns to form an array. In some embodiments, the bonding structure also includes a thermal sheet that divides the dielectric layer into an upper portion thermally coupled to the substrate and a lower portion thermally coupled to the front-side interconnect structure. In some embodiments, the thermal pillars each have a sidewall, the sidewall having a first tapered portion and a second tapered portion, the second tapered portion gradually narrowing in an opposite direction relative to the first tapered portion.

[0070] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a first dielectric layer on a semiconductor structure, the semiconductor structure comprising a semiconductor device layer having a front side and a back side, a first substrate disposed on the back side of the semiconductor device layer, and a first interconnect structure disposed on the front side of the semiconductor device layer; forming a plurality of first vias through the first dielectric layer and extending to the first interconnect structure, the first vias having a first thermally conductive material having a thermal conductivity greater than about 10 W / m·K; forming a second dielectric layer on a second substrate; forming a plurality of second vias through the second dielectric layer and extending to the second substrate, the second vias having a second thermally conductive material having a thermal conductivity greater than about 10 W / m·K; bonding the second dielectric layer to the first dielectric layer and bonding the second via to the first via; as well as A second interconnect structure is formed on the backside of the semiconductor device layer.

2. The method according to claim 1, wherein: Forming the second interconnect structure includes thinning or removing the first substrate.

3. The method according to claim 1, wherein: Forming the first through hole includes: patterning the first dielectric layer to form a plurality of first via trenches; depositing a first thermally conductive material in the first via trench and on the first dielectric layer; and A first planarization process is performed to partially remove the first thermally conductive material, so that a portion of the first thermally conductive material remaining in the first via trench forms the first via.

4. The method according to claim 3, wherein: Forming the second through hole includes: patterning the second dielectric layer to form a plurality of second via trenches; depositing a second thermally conductive material in the second via trench and over the second dielectric layer; and A second planarization process is performed to partially remove the second thermally conductive material, so that a portion of the second thermally conductive material remaining in the second via trench forms the second via.

5. The method according to claim 1, wherein: The second through hole is partially embedded in the second substrate.

6. A method of forming a semiconductor device, comprising: forming a first interconnect structure on a first side of the semiconductor device layer; forming a bonding structure connecting the first interconnect structure and a substrate, the bonding structure comprising a dielectric layer and an array of thermally conductive pillars extending through the dielectric layer, the thermally conductive pillars being electrically isolated from the semiconductor device layer; as well as A second interconnect structure is formed on a second side of the semiconductor device layer, the second side of the semiconductor device layer facing away from the first side of the semiconductor device layer.

7. The method according to claim 6, wherein: The thermally conductive pillars each have a middle portion that is wider than a top portion and a bottom portion.

8. The method according to claim 6, wherein: The engagement structure further comprises: A heat sheet divides the dielectric layer into an upper portion thermally coupled to the substrate and a lower portion thermally coupled to the first interconnect structure.

9. A semiconductor device comprising: Semiconductor device layer; A front-side interconnect structure located above the semiconductor device layer; a backside interconnect structure, located below the semiconductor device layer; as well as a substrate bonded to the front-side interconnect structure via a bonding structure, Wherein, the bonding structure comprises: a dielectric layer; and A plurality of thermal pillars extend through the dielectric layer, the thermal pillars having a first end coupled to the front-side interconnect structure and a second end coupled to the substrate.

10. The semiconductor device according to claim 9, wherein The thermal pillars each have a sidewall having a first tapered portion and a second tapered portion that tapers in an opposite direction relative to the first tapered portion.

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