Semiconductor processing method and semiconductor structure

Abstract

The invention provides a semiconductor processing method and a semiconductor structure. The semiconductor processing method comprises the following steps: providing a substrate, and forming a base material layer on the substrate; forming a first photoresist layer on the substrate material layer, and exposing and developing the first photoresist layer to form a first patterned photoresist layer; performing curing treatment on the first patterned photoresist layer to form a first transfer pattern; forming a second photoresist layer on the substrate material layer, at least filling the second photoresist layer between the adjacent first transfer patterns, and exposing and developing the second photoresist layer to form a second transfer pattern; and etching the substrate material layer by taking the first transfer pattern and the second transfer pattern as masks so as to transfer the patterns in the masks to the substrate material layer. The semiconductor processing method is beneficial to improving the precision and efficiency of pattern transfer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor processing method and a semiconductor structure. Background Art

[0002] With the continuous development of integrated circuit technology, semiconductor manufacturing processes have gradually entered a stage of smaller critical dimensions (≤45nm). In this process, the accuracy and efficiency of pattern transfer technology have become key factors that cannot be ignored in the process.

[0003] However, although the traditional single-exposure pattern transfer method can achieve a certain degree of pattern accuracy, it is difficult to meet the precise transfer requirements of higher density and smaller size patterns when facing smaller process nodes.

[0004] Therefore, how to improve the efficiency of pattern transfer technology and maintain high precision has become a technical problem that needs to be solved urgently in the current semiconductor manufacturing field.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the invention

[0006] Based on this, the embodiments of the present application provide a semiconductor processing method and a semiconductor structure, which are beneficial to improving the accuracy and efficiency of pattern transfer.

[0007] According to some embodiments, the present application provides a semiconductor processing method, including:

[0008] Providing a substrate, and forming a base material layer on the substrate;

[0009] forming a first photoresist layer on the base material layer, and exposing and developing the first photoresist layer to form a first patterned photoresist layer;

[0010] Curing the first patterned photoresist layer to form a first transfer pattern;

[0011] forming a second photoresist layer on the base material layer, wherein the second photoresist layer is at least filled between adjacent first transfer patterns, and exposing and developing the second photoresist layer to form a second transfer pattern;

[0012] The base material layer is etched using the first transfer pattern and the second transfer pattern as masks to transfer the pattern in the mask to the base material layer.

[0013] In some embodiments, forming a base material layer on the substrate includes:

[0014] A silicon oxide layer is formed on the substrate by a chemical vapor deposition process as the base material layer.

[0015] In some embodiments, forming a first photoresist layer on the base material layer includes:

[0016] A first photoresist is spin-coated on the base material layer to form the first photoresist layer.

[0017] In some embodiments, curing the first patterned photoresist layer includes:

[0018] The first patterned photoresist layer is cured by using deep ultraviolet light.

[0019] In some embodiments, the wavelength range of the deep ultraviolet light includes 100 nm to 300 nm.

[0020] In some implementations, the first patterned photoresist layer is cured using deep ultraviolet light with a wavelength of 172 nm.

[0021] In some embodiments, curing the first patterned photoresist layer includes:

[0022] The first patterned photoresist layer is cured by using reactive gas plasma.

[0023] In some embodiments, curing the first patterned photoresist layer includes:

[0024] A heat treatment process is performed on the first patterned photoresist layer to solidify the first patterned photoresist layer.

[0025] In some embodiments, forming a second photoresist layer on the base material layer includes:

[0026] A second photoresist is spin-coated on the base material layer to form the second photoresist layer.

[0027] According to some embodiments, the present application further provides a semiconductor structure on the other hand, wherein the semiconductor structure comprises the steps of the semiconductor processing method in the aforementioned embodiment during the preparation process.

[0028] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.

[0029] The embodiments of the present application may or at least have the following advantages:

[0030] The embodiment of the present application adopts double pattern transfer, first forms a first patterned photoresist layer on the base material layer, performs a curing process based on the first patterned photoresist layer to form a first transfer pattern, and then further forms a second transfer pattern on the base material layer on the basis of retaining the first transfer pattern, thereby obtaining a mask with higher density and smaller size. The base material layer is etched based on the mask formed by the double pattern transfer, and the pattern in the mask is transferred to the base material layer, which can achieve more accurate pattern transfer, such as pattern transfer with a critical size of ≤45nm.

[0031] Furthermore, by double pattern transfer, i.e., the first transfer pattern obtained after the first photoresist layer is exposed, developed and cured, and the second transfer pattern obtained after the second photoresist layer is exposed, developed and used together as a mask for pattern transfer, a single etching operation is performed on the substrate material layer, which can reduce the number of etching steps in the semiconductor process, help simplify the process flow, improve production efficiency and reduce production costs. Reducing multiple independent etching steps can also avoid precision deviations and error accumulation caused by multiple operations, improve the process consistency of the semiconductor processing process, and thus achieve high-quality pattern transfer.

[0032] Other advantages, objectives and features of the present application will be described in the following description to some extent, and will be apparent to those skilled in the art based on the following examination and study, or can be taught from the practice of the present application to some extent. The objectives and other advantages of the present application can be achieved and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.

[0034] Figure 1 A schematic flow chart of a semiconductor processing method in some embodiments of the present application;

[0035] Figure 2 A schematic diagram of a cross-sectional structure of a structure obtained after a base material layer is formed in a semiconductor processing method provided in some embodiments of the present application;

[0036] Figure 3 A schematic cross-sectional view of a structure obtained after forming a first photoresist layer in a semiconductor processing method provided in some embodiments of the present application;

[0037] Figure 4 A schematic cross-sectional view of a structure obtained after forming a first patterned photoresist layer in a semiconductor processing method provided in some embodiments of the present application;

[0038] Figure 5A schematic diagram of a cross-sectional structure of a structure obtained after forming a first transfer pattern in a semiconductor processing method provided in some embodiments of the present application;

[0039] Figure 6 A schematic diagram of a cross-sectional structure of a structure obtained after forming a second photoresist layer in a semiconductor processing method provided in some embodiments of the present application;

[0040] Figure 7 A schematic diagram of a cross-sectional structure of a structure obtained after forming a second transfer pattern in a semiconductor processing method provided in some embodiments of the present application;

[0041] Figure 8 A schematic diagram of the cross-sectional structure of a structure obtained after transferring a pattern in a mask to a base material layer in a semiconductor processing method provided in some embodiments of the present application.

[0042] Description of reference numerals:

[0043] 110, substrate; 120, base material layer;

[0044] 210, first photoresist layer; 210', first mask; 220, first patterned photoresist layer;

[0045] 310, first transfer pattern;

[0046] 410, a second photoresist layer; 410', a second mask; 420, a second transfer pattern. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0049] It should be understood that when an element or layer is referred to as "on..." or "adjacent...", it may be directly on or adjacent to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, a first photoresist layer may be referred to as a second photoresist layer, and similarly, a second photoresist layer may be referred to as a first photoresist layer.

[0050] Spatially relative terms such as "on..." may be used herein to describe the relationship of one layer or feature shown in the figures to other layers or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, a description as "on other layers" would be oriented as "below" the other layers or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the semiconductor structure may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0051] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] The traditional single-exposure pattern transfer method is difficult to meet the requirements of accurate transfer of higher density and smaller size patterns when facing smaller process nodes. Therefore, how to improve the efficiency of pattern transfer technology and maintain high accuracy has become a technical problem that needs to be solved urgently in the current semiconductor manufacturing field.

[0053] Based on this, the present application hopes to provide a solution that can solve the above technical problems, which is conducive to improving the accuracy and efficiency of graphic transfer. The details will be described in the subsequent embodiments.

[0054] According to some embodiments, the present application provides a semiconductor processing method. Figure 1The semiconductor processing method may specifically include the following steps S100 to S500:

[0055] S100: providing a substrate, and forming a base material layer on the substrate.

[0056] S200: forming a first photoresist layer on the base material layer, and exposing and developing the first photoresist layer to form a first patterned photoresist layer.

[0057] S300: curing the first patterned photoresist layer to form a first transfer pattern.

[0058] S400: forming a second photoresist layer on the base material layer, wherein the second photoresist layer at least fills between adjacent first transfer patterns, and exposing and developing the second photoresist layer to form a second transfer pattern.

[0059] S500: using the first transfer pattern and the second transfer pattern as masks, etching the base material layer to transfer the pattern in the mask to the base material layer.

[0060] The semiconductor processing method provided by the present application adopts double pattern transfer, first forms a first patterned photoresist layer on the base material layer, performs a curing process based on the first patterned photoresist layer to form a first transfer pattern, and then further forms a second transfer pattern on the base material layer on the basis of retaining the first transfer pattern, thereby obtaining a mask with higher density and smaller size. The base material layer is etched based on the mask formed by the double pattern transfer, and the pattern in the mask is transferred to the base material layer, which can achieve more accurate pattern transfer, such as pattern transfer with a critical size of ≤45nm.

[0061] Furthermore, by double pattern transfer, i.e., the first transfer pattern obtained after the first photoresist layer is exposed, developed and cured, and the second transfer pattern obtained after the second photoresist layer is exposed, developed and used together as a mask for pattern transfer, a single etching operation is performed on the substrate material layer, which can reduce the number of etching steps in the semiconductor process, help simplify the process flow, improve production efficiency and reduce production costs. Reducing multiple independent etching steps can also avoid precision deviations and error accumulation caused by multiple operations, improve the process consistency of the semiconductor processing process, and thus achieve high-quality pattern transfer.

[0062] The following combination Figures 2 to 8 The semiconductor processing method provided in the present application is described in more detail.

[0063] In step S100, Figure 2 As shown, a substrate 110 is provided, and a base material layer 120 is formed on the substrate 110 .

[0064] As an example, the substrate 110 may be made of semiconductor material, insulating material, conductor material or any combination of these material types. For example, the substrate 110 may include but is not limited to any one or more of a silicon (Si) substrate, a sapphire (Diamond) substrate, a glass substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate or a gallium arsenide (GaAs) substrate, etc.

[0065] The present embodiment of the present application does not specifically limit the material of the base material layer 120. As an example, the base material layer 120 may include silicon oxide (SiO x ) layer. The silicon oxide layer has good optical contrast, which can make the pattern transfer clearer and the details more accurate, and is helpful to achieve high-precision pattern transfer, such as pattern transfer with a critical size of ≤45nm. In addition, the silicon oxide layer has good chemical stability and is not easy to react with the photoresist required in the subsequent steps. It can provide a stable etching environment and help ensure that the base material layer 120 is not affected by the subsequent etching process.

[0066] The embodiment of the present application does not specifically limit the method for forming the base material layer 120 on the substrate 110. In some embodiments, a chemical vapor deposition process can be used to form silicon oxide (SiO x ) layer, as the base material layer 120.

[0067] As an example, a chemical vapor deposition process such as plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) may be used to form silicon oxide (SiO) on the substrate 110. x ) layer, but is not limited to this.

[0068] Compared with other chemical vapor deposition processes, the PECVD process not only has a higher deposition rate, but also can grow a uniform silicon oxide film at a lower temperature. The density and thickness of the silicon oxide film are easy to control, and the plasma enhancement effect can also make the silicon oxide film have better adhesion and compactness. Therefore, using the PECVD process to form a silicon oxide layer on the substrate 110 is conducive to improving the performance of the base material layer 120.

[0069] In step S200, Figure 3 As shown, a first photoresist layer 210 is formed on the base material layer 120; then Figure 4 As shown, the first photoresist layer 210 is exposed and developed to form a first patterned photoresist layer 220 .

[0070] The embodiment of the present application does not specifically limit the manner in which the first photoresist layer 210 is formed on the base material layer 120. In some embodiments, the first photoresist may be spin-coated (spin-coated for short) on the base material layer 120 to form the first photoresist layer 210. The spin-coating process can accurately control the thickness of the first photoresist layer 210, reduce process defects, form a more uniform first photoresist layer 210, and avoid processing problems caused by subsequent non-uniformity or other process defects of the first photoresist layer 210 in the subsequent exposure and development process, thereby facilitating the improvement of the overall production yield of the semiconductor processing method.

[0071] For example, Figure 4 As shown, a first mask 210 ′ may be used to define a pattern to be transferred to the first photoresist layer 210 , and the first photoresist layer 210 may be exposed and developed to form a first patterned photoresist layer 220 .

[0072] In step S300, Figure 5 As shown, the first patterned photoresist layer 220 is cured to form a first transfer pattern 310 .

[0073] It should be noted that, in the above steps, it is allowed to perform full-layer curing treatment on the first patterned photoresist layer 220 or perform only surface curing treatment on the first patterned photoresist layer 220 .

[0074] The embodiment of the present application does not specifically limit the method for curing the first patterned photoresist layer 220. In some embodiments, Figure 5 As shown, deep ultraviolet (DUV) can be used to cure the first patterned photoresist layer 220. Using deep ultraviolet for curing is not only faster, but also reduces thermal damage to the base material layer 120 because deep ultraviolet curing can be completed at a lower temperature.

[0075] As an example, the wavelength range of the deep ultraviolet light may specifically include 100nm to 300nm. For example, the first patterned photoresist layer 220 may be cured by using deep ultraviolet light with a wavelength of 172nm. The deep ultraviolet light with a wavelength of 172nm can efficiently excite the chemical components in the first patterned photoresist layer 220, causing a more thorough cross-linking reaction, thereby enhancing the mechanical strength of the first patterned photoresist layer 220 and transforming it into the first transfer pattern 310.

[0076] In some embodiments, reactive gas plasma may be used to cure the first patterned photoresist layer 220. Plasma treatment can provide more uniform energy distribution, and is particularly suitable for curing tiny first patterned photoresist layer 220 structures, ensuring that the first patterned photoresist layer 220 is uniformly cured over the entire surface. Furthermore, the use of reactive gas plasma can not only cure and freeze the surface of the first patterned photoresist layer 220, but also cure the deep layer of the first patterned photoresist layer 220, ensuring that the first patterned photoresist layer 220 is cured over the entire thickness range.

[0077] In some other implementations, the first patterned photoresist layer 220 may be subjected to a heat treatment process to solidify the first patterned photoresist layer 220 .

[0078] In step S400, Figure 6 As shown, a second photoresist layer 410 is formed on the base material layer 120, and the second photoresist layer 410 is at least filled between adjacent first transfer patterns 310; then as shown in FIG. Figure 7 As shown, the second photoresist layer 410 is exposed and developed to form a second transfer pattern 420 .

[0079] For example, Figure 7 As shown, a second mask 410 ′ may be used to define a pattern to be transferred to the second photoresist layer 410 , and the second photoresist layer 410 may be exposed and developed to form a second transfer pattern 420 .

[0080] The embodiment of the present application does not specifically limit the method for forming the second photoresist layer 410 on the base material layer 120. In some embodiments, the second photoresist can be spin-coated on the base material layer 120 to form the second photoresist layer 410. Similar to the spin-coating of the first photoresist, the use of the spin-coating process in step S400 is also conducive to improving the overall production yield of the semiconductor processing method, which will not be described in detail herein.

[0081] In step S500, Figure 8 As shown, the base material layer 120 is etched using the first transfer pattern 310 and the second transfer pattern 420 as masks to transfer the pattern in the mask to the base material layer 120 .

[0082] Based on the same inventive concept, the present application also provides a semiconductor structure. Figure 8 It is understood that the semiconductor structure includes the steps of the semiconductor processing method in the above embodiment during the preparation process. Therefore, the technical effects that can be achieved by the above semiconductor processing method can also be achieved by the semiconductor structure, which will not be described in detail here.

[0083] It should be noted that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application, which is obvious to those skilled in the art. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0084] In the description of this specification, the description with reference to the terms "some embodiments", "as an example", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0085] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor processing method, characterized in that: include: Providing a substrate, and forming a base material layer on the substrate; forming a first photoresist layer on the base material layer, and exposing and developing the first photoresist layer to form a first patterned photoresist layer; Curing the first patterned photoresist layer to form a first transfer pattern; forming a second photoresist layer on the base material layer, wherein the second photoresist layer is at least filled between adjacent first transfer patterns, and exposing and developing the second photoresist layer to form a second transfer pattern; The base material layer is etched using the first transfer pattern and the second transfer pattern as masks to transfer the pattern in the mask to the base material layer.

2. The semiconductor processing method according to claim 1, characterized in that: Forming a base material layer on the substrate, comprising: A silicon oxide layer is formed on the substrate by a chemical vapor deposition process as the base material layer.

3. The semiconductor processing method according to claim 1, characterized in that: Forming a first photoresist layer on the base material layer, comprising: A first photoresist is spin-coated on the base material layer to form the first photoresist layer.

4. The semiconductor processing method according to claim 1, characterized in that: The first patterned photoresist layer is cured, comprising: The first patterned photoresist layer is cured by using deep ultraviolet light.

5. The semiconductor processing method according to claim 4, characterized in that: The wavelength range of the deep ultraviolet light includes 100nm to 300nm.

6. The semiconductor processing method according to claim 5, characterized in that: The first patterned photoresist layer is cured using deep ultraviolet light with a wavelength of 172 nm.

7. The semiconductor processing method according to claim 1, characterized in that: The first patterned photoresist layer is cured, comprising: The first patterned photoresist layer is cured by using reactive gas plasma.

8. The semiconductor processing method according to claim 1, characterized in that: The first patterned photoresist layer is cured, comprising: A heat treatment process is performed on the first patterned photoresist layer to solidify the first patterned photoresist layer.

9. The semiconductor processing method according to claim 1, characterized in that: Forming a second photoresist layer on the base material layer, comprising: A second photoresist is spin-coated on the base material layer to form the second photoresist layer.

10. A semiconductor structure, characterized in that: The semiconductor structure comprises the steps of the semiconductor processing method according to any one of claims 1 to 9 during the preparation process.

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