Manufacturing method of semiconductor structure

Abstract

The invention discloses a manufacturing method of a semiconductor structure, which belongs to the technical field of semiconductors, and comprises the following steps: providing a substrate, and sequentially forming a pad oxide layer and a pad nitride layer on the substrate; etching a part of the pad oxide layer, the pad nitride layer and the substrate to form a shallow trench; an insulating medium is deposited in the shallow trench, the insulating medium is planarized for the first time, and the insulating medium is flush with the pad nitride layers on the two sides; performing micro-etching treatment on the pad nitriding layer to form a micro-structure layer, and performing micro-etching by adopting a weak physical sputtering mode; oxidizing the pad nitride layer to form an intermediate oxide layer; equivalently removing the intermediate oxide layer and part of the insulating medium; repeating the micro-etching treatment, the oxidation treatment and the equivalent removal step until the pad nitride layer is removed; and removing the pad oxide layer and a part of the insulating medium. According to the manufacturing method of the semiconductor structure provided by the invention, the phenomenon that the corner edge of the shallow trench isolation structure is sunken can be avoided, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a method for manufacturing a semiconductor structure. Background Art

[0002] A shallow trench isolation (STI) structure is an important structure in integrated circuits. It is disposed between semiconductor devices to prevent current leakage between adjacent semiconductor devices and reduce the area of the isolation region. During the formation of the shallow trench isolation structure, after removing the pad nitride layer, the shallow trench isolation structure is higher than the pad oxide layer. When removing the pad oxide layer, the protruding shallow trench isolation structure is etched from multiple directions, and it is easy to over-etch the filled oxide layer at the corner edge of the interface between the STI and the substrate to form a divot. This "divot" phenomenon causes the polysilicon that forms the gate to fill the divot area when the semiconductor device crosses the STI and the active region, thereby generating a parasitic device at this location, resulting in additional leakage current when the normal semiconductor device operates. It also causes the electric field intensity at the upper corner of the substrate to be too large, leading to leakage problems. Summary of the Invention

[0003] An object of the present invention is to provide a method for manufacturing a semiconductor structure. By the method for manufacturing a semiconductor structure provided by the present invention, the occurrence of a concave phenomenon at the corner edge of the shallow trench isolation structure can be avoided, the occurrence of leakage current in the semiconductor structure can be avoided, the semiconductor structure has a good isolation effect, and the performance of the semiconductor structure is improved.

[0004] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor structure, which at least includes the following steps: Provide a substrate, and sequentially form a pad oxide layer and a pad nitride layer on the substrate; Etch a part of the pad oxide layer, the pad nitride layer, and the substrate to form a shallow trench; Deposit an insulating medium in the shallow trench, and perform a first planarization treatment on the insulating medium so that the insulating medium is flush with the pad nitride layers on both sides; Perform a micro-etching treatment on the pad nitride layer to form a micro-structure layer, and the micro-etching uses a weak physical sputtering method; Oxidize the pad nitride layer to form an intermediate oxide layer; Remove an equal amount of the intermediate oxide layer and a part of the insulating medium; Repeat the micro-etching treatment, the oxidation treatment, and the equal-amount removal step until the pad nitride layer is removed; and Remove the pad oxide layer and a part of the insulating medium.

[0005] In an embodiment of the present invention, the manufacturing method further includes: Putting the substrate after the first planarization treatment into a sputtering device; and Introducing a mixed gas of hydrogen and an inert gas under a preset power and a preset pressure, and processing for a preset time.

[0006] In an embodiment of the present invention, the preset power is 1000W - 3000W, and the preset pressure is 0.1 Torr - 10 Torr.

[0007] In an embodiment of the present invention, the total flow rate of the hydrogen and the inert gas is 300 sccm - 900 sccm, and the flow rate ratio of the hydrogen to the inert gas is 2:1 - 4:1.

[0008] In an embodiment of the present invention, the manufacturing method further includes: Putting the substrate forming the micro - structure layer into a plasma device; and Introducing an oxygen - containing gas for oxidation treatment.

[0009] In an embodiment of the present invention, the working power of the plasma device is 4000W - 8000W, the chamber pressure is 0.1 Torr - 10 Torr, and the processing time is 120s - 150s.

[0010] In an embodiment of the present invention, the thickness of the intermediate oxide layer obtained by a single oxidation treatment is 90 Å - 110 Å.

[0011] In an embodiment of the present invention, chemical - mechanical polishing is used to equally remove the intermediate oxide layer and part of the insulating dielectric, and the polishing rate of the intermediate oxide layer is equal to that of the insulating dielectric.

[0012] In an embodiment of the present invention, after removing the pad nitride layer, the insulating dielectric is flush with the pad oxide layers on both sides.

[0013] In an embodiment of the present invention, after removing the pad oxide layer, the insulating dielectric is flush with the substrates on both sides or the insulating dielectric is lower than the substrates on both sides, and the surface of the insulating dielectric is flat.

[0014] In summary, the present invention provides a method for manufacturing a semiconductor structure. By improving the method for manufacturing the semiconductor structure, the unexpected technical effects of the present application are as follows: it can avoid the occurrence of recesses at the corner edges of the shallow trench isolation structure, can avoid the occurrence of leakage in the semiconductor structure, the semiconductor structure has good isolation effect, and the performance of the semiconductor structure is improved. It can accelerate the oxidation rate of the pad nitride layer, accelerate the removal rate of the pad nitride layer, and improve the manufacturing efficiency. It can control the relative position between the shallow trench isolation structure and the substrate, and has high controllability. Different shallow trench isolation structures can be manufactured according to manufacturing requirements, meeting the manufacturing requirements of different semiconductor devices, and improving the performance of semiconductor devices including the semiconductor structure.

[0015] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 It is a schematic diagram of forming a pad oxide layer, a pad nitride layer, and a patterned photoresist layer on a substrate in an embodiment.

[0018] Figure 2 It is a schematic diagram of the formed shallow trench in an embodiment.

[0019] Figure 3 It is a schematic diagram of the deposited insulating medium in an embodiment.

[0020] Figure 4 It is a schematic diagram after the first planarization treatment of the insulating medium in an embodiment.

[0021] Figure 5 It is a schematic diagram after forming a microstructural layer in an embodiment.

[0022] Figure 6 It is a schematic diagram after forming an intermediate oxide layer in an embodiment.

[0023] Figure 7 It is a schematic diagram after planarization treatment of the intermediate oxide layer and the microstructural layer in an embodiment.

[0024] Figure 8 It is a schematic diagram after forming the microstructural layer again in an embodiment.

[0025] Figure 9 It is a schematic diagram after removing the pad nitride layer in an embodiment.

[0026] Figure 10 It is a schematic diagram of a semiconductor structure in an embodiment.

[0027] Label description: 100, substrate; 110, pad oxide layer; 120, pad nitride layer; 130, patterned photoresist layer; 131, first opening; 140, shallow trench; 150, insulating medium; 160, microstructure layer; 170, intermediate oxide layer; 180, shallow trench isolation structure. Detailed implementation manners

[0028] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0030] In the present invention, it should be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, so it cannot be understood as a limitation to this application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes, and cannot be understood as indicating or implying relative importance.

[0031] Please refer to Figure 1As shown, in an embodiment of the present invention, the substrate 100 provided by the present invention is any applicable semiconductor material, such as a sapphire, a silicon wafer, a silicon carbide (SiC), a gallium nitride (GaN), an aluminum nitride (AlN), an indium nitride (InN), or a silicon germanium (GeSi) substrate, etc., and also includes a stacked structure composed of these semiconductor materials, etc., or is silicon on insulator, silicon-on-insulator germanium, silicon-on-insulator germanium carbide, germanium-on-insulator, and germanium-on-insulator, etc. Specifically, it can be selected according to the manufacturing requirements of semiconductor devices. In this embodiment, the substrate 100 is, for example, a silicon wafer semiconductor substrate, and the substrate 100 can be an undoped substrate or a doped substrate, and can also be, for example, an N-type substrate or a P-type substrate. The thickness of the substrate 100 is not specifically limited and is selected according to the manufacturing requirements.

[0032] Please refer to Figure 1 As shown, in an embodiment of the present invention, a pad oxide layer 110 is formed on the substrate 100, and the pad oxide layer 110 is, for example, a material such as dense silicon oxide. The pad oxide layer 110 is prepared, for example, by thermal oxidation or in-situ steam generation (ISSG) methods to obtain dense silicon oxide, etc. In this embodiment, the pad oxide layer 110 is prepared, for example, by in-situ steam generation. Specifically, the substrate 100 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen mixed with a small amount of hydrogen is introduced. The silicon on the surface of the substrate 100 reacts with oxygen at high temperature to form a dense pad oxide layer 110, and the quality of the formed pad oxide layer 110 is good. Among them, the thickness of the pad oxide layer 110 is, for example, 10 nm to 40 nm, specifically, for example, 10 nm, 20 nm, 30 nm, or 40 nm, etc.

[0033] Please refer to Figure 1As shown, in an embodiment of the present invention, after forming the pad oxide layer 110, a pad nitride layer 120 is formed on the pad oxide layer 110. The pad nitride layer 120 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. Among them, the pad oxide layer 110 can improve the stress between the substrate 100 and the pad nitride layer 120 as a buffer layer. In this embodiment, the pad nitride layer 120 is, for example, silicon nitride, and the pad nitride layer 120 can be formed by methods such as Low Pressure Chemical Vapor Deposition (LPCVD). Specifically, for example, the substrate 100 with the pad oxide layer 110 is placed in a furnace tube filled with dichlorosilane and ammonia gas, and the reaction is carried out at a pressure of, for example, 2 Torr to 10 Torr and a temperature of, for example, 700 °C to 900 °C to deposit the pad nitride layer 120, and the thickness of the pad nitride layer 120 can be adjusted by controlling the heating time. In this embodiment, the thickness of the pad nitride layer 120 is, for example, 50 nm to 120 nm. By providing the pad nitride layer 120, the substrate 100 can be protected from the influence of planarization processes such as Chemical Mechanical Polishing (CMP) involved in the fabrication process of the shallow trench isolation structure. And the pad nitride layer 120 can be used as a mask during the formation of the shallow trench, protecting other parts of the substrate 100 from damage when etching the substrate 100. Since the pad nitride layer 120 has high stress, the provided pad oxide layer 110 can be used to buffer the stress in the pad nitride layer 120, avoiding defects caused by stress to the substrate 100. At the same time, the pad oxide layer 110 also serves as a stop layer when etching to remove the pad nitride layer 120.

[0034] Please refer to Figures 1 to 2 As shown, in an embodiment of the present invention, after forming the pad nitride layer 120, a photoresist layer is formed on the pad nitride layer 120. After processes such as exposure and development, a patterned photoresist layer 130 is formed. The patterned photoresist layer 130 includes a plurality of first openings 131, and the first openings 131 expose a part of the pad nitride layer 120 to define the position of the shallow trench. Using the patterned photoresist layer 130 as a mask, etching is carried out, for example, using dry etching, in the direction of the substrate 100 to form the shallow trench 140. Among them, the etching gas includes, for example, one or several mixtures of chlorine gas (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr), etc., or their mixtures with oxygen gas (O2). In this embodiment, after forming the shallow trench 140, the patterned photoresist layer 130 is removed by wet cleaning or ashing treatment.

[0035] Please refer to Figures 2 to 3As shown, in an embodiment of the present invention, after forming the shallow trench 140, an insulating medium 150 is deposited in the shallow trench 140 until the insulating medium 150 covers the surface of the pad nitride layer 120. Before depositing the insulating medium 150, the shallow trench 140 can be thermally oxidized to form a liner oxide layer (not shown in the figure) to round off the bottom corner of the shallow trench 140, reduce the tip leakage phenomenon, and repair the etching damage during the formation of the shallow trench. The present invention does not limit the deposition method of the insulating medium 150. For example, the insulating medium 150 can be formed in the shallow trench 140 by deposition methods such as Chemical Vapor Deposition (CVD) or High Aspect Ratio Process CVD (HARP-CVD). In this embodiment, the insulating medium 150 is obtained, for example, by depositing Tetraethyl Orthosilicate (TEOS). Specifically, in a temperature range of, for example, 300°C to 500°C and a pressure of, for example, 30 Torr to 700 Torr, tetraethyl orthosilicate and an oxygen-containing precursor are introduced. The oxygen-containing precursor includes, for example, one of O2 or O3, etc., and the deposition time is controlled to obtain the insulating medium 150. Among them, through chemical vapor deposition, the deposition rate of the insulating medium 150 is fast and it can be deposited at a low temperature. The hole filling ability of the deposited silicon dioxide is good, and problems such as voids are not likely to occur, so as to improve the performance of the shallow trench isolation structure formed subsequently.

[0036] Please refer to Figures 3 to 4 As shown, in an embodiment of the present invention, after preparing the insulating medium 150, a first planarization process is performed on the insulating medium 150. For example, the insulating medium 150 is planarized by processes such as chemical mechanical polishing until the insulating medium 150 on the pad nitride layer 120 is removed. During the first planarization process, the pad nitride layer 120 is used as the polishing stop layer. During the polishing process, when it is detected that the polishing reaches the pad nitride layer 120, the polishing is stopped. In this embodiment, after the first planarization process, the insulating medium 150 is, for example, flush with the pad nitride layers 120 on both sides.

[0037] Please refer to Figures 4 to 5As shown, in an embodiment of the present invention, after planarizing the insulating dielectric 150, for example, micro-etching the pad nitride layer 120 to form a micro-structure layer 160 to increase the specific surface area of the pad nitride layer 120. Among them, the thickness of the micro-structure layer 160 is, for example, 5 Å to 20 Å. In this embodiment, for example, the pad nitride layer 120 is micro-etched by a weak physical sputtering method. Specifically, the substrate 100 after the first planarization of the insulating dielectric 150 is placed in a sputtering device, such as a magnetron sputtering device or an ion sputtering instrument, etc., and the preset power of the sputtering device is controlled to be, for example, 1000 W to 3000 W, the preset pressure in the cavity is, for example, 0.1 Torr to 10 Torr, and a mixed gas of hydrogen and an inert gas is introduced, and the treatment preset time is, for example, 5 s to 30 s. Among them, the inert gas is, for example, helium, etc., and the total flow rate of hydrogen and the inert gas is, for example, 300 sccm to 900 sccm, and the flow rate ratio of hydrogen and the inert gas is, for example, 2:1 to 4:1. By micro-etching the pad nitride layer 120, the surface of the pad nitride layer 120 can be roughened, and a plurality of fine recesses are formed on the surface of the pad nitride layer 120, thereby increasing the specific surface area of the pad nitride layer 120. Therefore, in the subsequent oxidation process, the oxidation amount of the pad nitride layer 120 can be increased, the removal rate of the pad nitride layer 120 can be accelerated, and the manufacturing efficiency can be improved.

[0038] Please refer to Figures 5 to 6 As shown, in an embodiment of the present invention, after forming the micro-structure layer 160, an oxidation treatment is performed to oxidize a part of the pad nitride layer 120 to form an intermediate oxide layer 170. In this embodiment, for example, the intermediate oxide layer 170 is formed by a method such as high-density plasma oxidation. Specifically, the substrate 100 on which the micro-structure layer 160 is formed is placed in a plasma device, such as a high-density plasma enhanced chemical vapor deposition device, etc., the working power of the plasma device is, for example, 4000 W to 8000 W, the pressure in the cavity is, for example, 0.1 Torr to 10 Torr, and an oxygen-containing gas is introduced, and the treatment time is, for example, 120 s to 150 s. Among them, the oxygen-containing gas includes, for example, at least one of oxygen or ozone, etc., and the flow rate of the oxygen-containing gas is, for example, 5000 sccm to 9000 sccm. Among them, due to the limitation of the oxidation process, the thickness of the intermediate oxide layer 170 obtained by single oxidation is, for example, 90 Å to 110 Å. By oxidizing a part of the pad nitride layer 120 to form the intermediate oxide layer 170, the polishing rate of the intermediate oxide layer 170 is close to the polishing rate of the insulating dielectric 150, and synchronous removal can be performed.

[0039] Please refer to Figures 6 to 7As shown, in an embodiment of the present invention, after the intermediate oxide layer 170 is formed, the intermediate oxide layer 170 and the insulating dielectric 150 are planarized. For example, processes such as chemical mechanical polishing are used to planarize the intermediate oxide layer 170 and the insulating dielectric 150 until the intermediate oxide layer 170 on the pad nitride layer 120 is removed. During the planarization process, for example, a cerium oxide-based polishing slurry is used for polishing. The polishing rate of the intermediate oxide layer 170 is, for example, the same as that of the insulating dielectric 150, and the intermediate oxide layer 170 and the insulating dielectric 150 can be removed synchronously in equal amounts. Therefore, during the polishing process, the pad nitride layer 120 is used as the polishing stop layer. During the polishing process, when it is detected that the polishing reaches the pad nitride layer 120, the polishing is stopped. In this embodiment, after polishing, the insulating dielectric 150 is, for example, flush with the pad nitride layers 120 on both sides.

[0040] Please refer to Figures 7 to 9 As shown, in an embodiment of the present invention, after the intermediate oxide layer 170 and a part of the insulating dielectric 150 are removed, the micro-etching process, the oxidation process, and the equal-amount removal step are repeated until the pad nitride layer 120 is completely removed. Among them, the methods and conditions for forming the micro-structure layer, forming the intermediate oxide layer, and removing the intermediate oxide layer and a part of the insulating dielectric are the same as those above. The number of repetitions is set according to the thickness of the pad nitride layer 120 after the first planarization of the insulating dielectric 150. In this application, through the first planarization process, the insulating dielectric is made flush with the pad nitride layers on both sides, and then through multiple micro-etching, oxidation, and planarization, the pad nitride layer and the insulating dielectric after the treatment can be removed synchronously. After the pad nitride layer is removed, the insulating dielectric is flush with the pad oxide layers on both sides, so that during the process of removing the pad oxide layer, the insulating dielectric 150 does not protrude above the pad oxide layer, thus avoiding depressions at the edges of the substrate and the shallow trench isolation structure.

[0041] Please refer to Figures 9 to 10As shown, in an embodiment of the present invention, after removing the pad nitride layer and a part of the insulating dielectric 150, the pad oxide layer 110 is removed to form a shallow trench isolation structure 180. Among them, the pad oxide layer 110 is removed, for example, by wet etching, dry etching, or a combination of wet etching and dry etching. When dry etching is used, the etching gas includes, for example, one or several mixtures of trifluoromethane, difluoromethane, sulfur hexafluoride, etc., or a mixture of them and oxygen. When wet etching is used, the etching solution for wet etching is, for example, dilute hydrofluoric acid or buffered oxide etch (BOE). The dilute hydrofluoric acid is prepared by mixing a 49wt% hydrofluoric acid solution and deionized water in a volume ratio of 1:20 to 50 to etch the pad oxide layer 110 while controlling the etching rate of the insulating dielectric 150 to prevent problems such as over-etching of the insulating dielectric 150 due to too fast an etching rate. In this embodiment, for example, wet etching is used for etching. When etching the pad oxide layer 110, since the material of the insulating dielectric 150 is the same as that of the pad oxide layer 110, therefore, the pad oxide layer 110 and the insulating dielectric 150 are etched synchronously, and the surfaces of the pad oxide layer 110 and the insulating dielectric 150 are flush before etching. There is no large contact angle between the edge and the etching solution. Therefore, the overall contact angle between the pad oxide layer 110 and the insulating dielectric 150 and the etching solution is the same, both being 180°. Therefore, during the etching process, the insulating dielectric 150 will be removed with equal thickness, and no depression will be formed at the interface between the substrate 100 and the shallow trench isolation structure 180, and the top of the shallow trench isolation structure 180 is flush. In this embodiment, the shallow trench isolation structure 180 is, for example, flush with the substrate 100. In other embodiments, by controlling the etching time, the shallow trench isolation structure 180 is, for example, lower than the surface of the substrate 100, and the surface of the shallow trench isolation structure 180 is flush. That is, in the present application, the height of the shallow trench isolation structure 180 can be controlled to be flush with or lower than the surface of the substrate 100, and no depression is generated at the edge, which can reduce leakage and meet the manufacturing requirements of different semiconductor devices.

[0042] Please refer to Figures 9 to 10As shown, in another embodiment of the present invention, for example, after removing the pad nitride layer, using the pad oxide layer 110 as an ion implantation buffer layer, ions are implanted into the substrate 100 to form structures such as well regions, or after forming a gate structure on the pad oxide layer 110, etc., the redundant pad oxide layer 110 and a part of the insulating dielectric 150 are removed. That is, in the present application, according to the manufacturing requirements of semiconductor devices, the pad oxide layer 110 and a part of the insulating dielectric 150 can be selectively removed in different steps. When removing the pad oxide layer 110, the insulating dielectric 150 is flush with the pad oxide layer 110. During the wet etching process, since the angle of contact between the insulating dielectric 150 and the etching solution is equal to the angle of contact between the pad oxide layer 110 and the etching solution, a shallow trench isolation structure 180 with a flat surface is formed, which can avoid the depression phenomenon at the corner edges of the shallow trench isolation structure 180 caused by the difference in etching rates. When forming a gate on the substrate, it can avoid the polysilicon forming the gate from filling in the depression, and can avoid the leakage phenomenon of the semiconductor structure. The semiconductor structure has a good isolation effect. It can ensure the morphology of the shallow trench isolation structure 180, improve the performance of the semiconductor structure, and thus improve the performance of the semiconductor device including the semiconductor structure.

[0043] In summary, the present invention provides a method for manufacturing a semiconductor structure. By improving the method for manufacturing the semiconductor structure, the unexpected technical effects of the present application are that it can avoid the depression phenomenon at the corner edges of the shallow trench isolation structure, can avoid the leakage phenomenon of the semiconductor structure, the semiconductor structure has a good isolation effect, and can improve the performance of the semiconductor structure. It can accelerate the oxidation rate of the pad nitride layer, accelerate the removal rate of the pad nitride layer, and improve the manufacturing efficiency. It can control the relative position between the shallow trench isolation structure and the substrate, and has high controllability. It can manufacture different shallow trench isolation structures according to the manufacturing requirements, meet the manufacturing requirements of different semiconductor devices, and improve the performance of the semiconductor device including the semiconductor structure.

[0044] References throughout this specification to "one embodiment", "an embodiment", or "a specific embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention and not necessarily in all embodiments. Thus, appearances of the phrases "in one embodiment", "in an embodiment", or "in a specific embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It should be understood that other variations and modifications of the embodiments of the invention described and shown herein may be made in accordance with the teachings herein and will be considered part of the spirit and scope of the present invention.

[0045] It should also be understood that the embodiments of the present invention disclosed above are only for helping to explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, At least include the following steps: Provide a substrate, and sequentially form a pad oxide layer and a pad nitride layer on the substrate; Etch a part of the pad oxide layer, the pad nitride layer and the substrate to form a shallow trench; Deposit an insulating medium in the shallow trench, and perform a first planarization process on the insulating medium so that the insulating medium is flush with the pad nitride layers on both sides; Perform a micro-etching process on the pad nitride layer to form a micro-structure layer, and the micro-etching adopts a weak physical sputtering method; Oxidize the pad nitride layer to form an intermediate oxide layer; Remove the intermediate oxide layer and a part of the insulating medium in equal amounts; Repeat the micro-etching process, the oxidation process and the equal-amount removal step until the pad nitride layer is removed; And Remove the pad oxide layer and a part of the insulating medium.

2. The manufacturing method of a semiconductor structure according to claim 1, wherein, The manufacturing method further includes: Put the substrate after the first planarization process into a sputtering device; and Under a preset power and a preset pressure, introduce a mixed gas of hydrogen and an inert gas and process for a preset time.

3. The manufacturing method of a semiconductor structure according to claim 2, wherein The preset power is 1000W - 3000W, and the preset pressure is 0.1 Torr - 10 Torr.

4. The manufacturing method of a semiconductor structure according to claim 2, characterized in that, The total flow rate of the hydrogen and the inert gas is 300 sccm - 900 sccm, and the flow rate ratio of the hydrogen and the inert gas is 2:1 - 4:

1.

5. The manufacturing method of a semiconductor structure according to claim 1, characterized in that, The manufacturing method further includes: Put the substrate forming the micro-structure layer into a plasma device; and Introduce an oxygen-containing gas for oxidation treatment.

6. The manufacturing method of a semiconductor structure according to claim 5, characterized in that, The working power of the plasma device is 4000W - 8000W, the pressure in the cavity is 0.1 Torr - 10 Torr, and the treatment time is 120s - 150s.

7. The manufacturing method of a semiconductor structure according to claim 1, characterized in that, The thickness of the intermediate oxide layer obtained by a single oxidation treatment is 90 Å - 110 Å.

8. The manufacturing method of a semiconductor structure according to claim 1, characterized in that Adopt chemical mechanical polishing to remove the intermediate oxide layer and a part of the insulating medium in equal amounts, and the polishing rate of the intermediate oxide layer is equal to that of the insulating medium.

9. The manufacturing method of a semiconductor structure according to claim 1, characterized in that, After removing the pad nitride layer, the insulating medium is flush with the pad oxide layers on both sides.

10. The manufacturing method of a semiconductor structure according to claim 1, wherein, After removing the pad oxide layer, the insulating medium is flush with the substrates on both sides or the insulating medium is lower than the substrates on both sides, and the surface of the insulating medium is flush.

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