Preparation method of shallow trench structure and semiconductor device

Abstract

The invention provides a preparation method of a shallow trench structure and a semiconductor device, and the preparation method comprises the following steps: providing a substrate which is provided with a plurality of first trenches extending to a substrate; growing a second oxide layer on the substrate; depositing a stress covariant layer on the substrate; etching to remove the stress covariant layer on the surface of the first nitride layer and the side walls of the first nitride layer and the first oxide layer of the first groove; generating a third oxide layer on the substrate; and filling the plurality of first grooves of the substrate to form a plurality of shallow groove structures. According to the preparation method, after the oxide layer is grown in the shallow trench structure, the nitride layer is additionally deposited to serve as the stress covariant layer, and the technological parameters of the stress covariant layer can be adjusted and deposited according to the target performance of the semiconductor structure, so that the required stress type is obtained, the effect of adjusting the stress of the active region of the semiconductor device is achieved, and the reliability of the semiconductor device is improved. The current transmission characteristic of the semiconductor device is improved, and the response speed and other electrical properties of the device are improved.

Description

Technical Field

[0001] The present invention relates to the technical field related to semiconductor devices, and in particular to a method for preparing a shallow trench structure and a semiconductor device. Background Art

[0002] In advanced process technology, there is inherent internal stress in silicon nitride (SiN) film. By controlling the RF power and other process parameters during the deposition process, tensile stress or compressive stress can be applied. When silicon nitride film is deposited at lower power and temperature, it shrinks after cooling to produce tensile stress; when silicon nitride film is deposited at higher power and temperature, compressive stress will be generated after cooling.

[0003] Shallow Trench Isolation (STI) isolates each transistor to prevent electrical interference by etching shallow trenches on the surface of the wafer and filling them with insulating materials. Applying tensile stress to the active area in shallow trench isolation can improve electron mobility, which helps to improve the mobility of N-type metal-oxide-semiconductor (NMOS) transistors; while applying compressive stress to the active area in shallow trench isolation can improve hole mobility and enhance the mobility of P-type metal-oxide-semiconductor (PMOS) transistors. This will cause changes in the electrical parameters of the device, mainly affecting the device's response speed, saturation current (Idsat) and threshold voltage (Vth).

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0005] In view of the problems in the prior art, the purpose of the present invention is to provide a method for preparing a shallow trench structure and a semiconductor device. The preparation method adds a stress covariant layer in the shallow trench structure so that shallow trench structures of different types of semiconductor structures can apply different target stresses to their active areas, thereby improving the carrier mobility of the active area, thereby improving the response speed and other electrical properties of the device.

[0006] Specifically, the first aspect of the present invention provides a method for preparing a shallow trench structure, the method comprising the following steps:

[0007] Providing a substrate, the substrate comprising a base plate, a first oxide layer and a first nitride layer stacked in sequence, the substrate being formed with a plurality of first trenches, the first trenches penetrating the first nitride layer and the first oxide layer and extending to the base plate;

[0008] growing a second oxide layer on the substrate;

[0009] depositing a stress-covariant layer on the substrate;

[0010] Etching and removing the surface of the first groove on the first nitride layer and the stress-compatible layer of the first groove;

[0011] generating a third oxide layer on the substrate;

[0012] The plurality of first trenches of the substrate are filled to form a plurality of shallow trench structures.

[0013] According to the first aspect of the present invention, when the structure type of the substrate is an NMOS structure, the stress covariant layer is a tensile stress layer;

[0014] When the structure type of the substrate is a PMOS structure, the stress-covariant layer is a compressive stress layer.

[0015] According to a first aspect of the present invention, the stress-compatible layer is deposited on a substrate using a chemical vapor deposition process.

[0016] According to the first aspect of the present invention, the stress-compatible layer is a silicon nitride layer.

[0017] According to the first aspect of the present invention, the thickness of the stress-compatible layer is between 100 angstroms and 200 angstroms.

[0018] According to the first aspect of the present invention, the second oxide layer is grown on the substrate using an in-situ steam oxidation process; and / or

[0019] The third oxide layer is grown on the stress-compatible layer on the sidewall of the first trench at the substrate by an in-situ steam oxidation process.

[0020] According to the first aspect of the present invention, a dry etching process is used to etch and remove the surface of the first nitride layer in the first trench and the stress-compatible layer in the first trench.

[0021] According to a first aspect of the present invention, filling the plurality of first trenches of the substrate comprises the following steps:

[0022] depositing a fill layer on the substrate;

[0023] The filling layer is planarized.

[0024] According to the first aspect of the present invention, before the step of planarizing the filling layer, the preparation method further comprises the following steps:

[0025] The substrate on which the filling layer is deposited is subjected to an annealing process.

[0026] A second aspect of the present invention provides a semiconductor device, comprising a plurality of the shallow trench structures, wherein the shallow trench structures are obtained by using the preparation method.

[0027] Compared with the prior art, in the preparation method of the shallow trench structure of the present invention, a nitride layer is deposited as a stress-covariant layer after an oxide layer is grown in the shallow trench structure. The process parameters for depositing the stress-covariant layer can be adjusted according to the target performance of the semiconductor structure, thereby obtaining the required stress type, achieving the function of adjusting the stress in the active area of ​​the semiconductor device, improving the current transmission characteristics of the complementary metal oxide semiconductor (CMOS) device, and enhancing the response speed and other electrical properties of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more apparent. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same figure numbers in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0029] Figure 1 A flowchart of a method for preparing a shallow trench structure according to an embodiment of the present invention; and

[0030] Figures 2 to 7 It is a schematic structural diagram after each step of a method for preparing a shallow trench structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the details in the present invention can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0032] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0033] In the representation of the present invention, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present invention and the features of different embodiments or examples, unless they are contradictory.

[0034] In order to clearly describe the present invention, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0035] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0036] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.

[0037] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0038] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present invention. The singular form used herein also includes the plural form as long as the sentence does not clearly indicate the opposite meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0039] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the content of relevant technical literature and current disclosures, and unless defined, shall not be overly interpreted as ideal or very formal meanings.

[0040] In order to overcome the above technical problems, the present invention provides a method for preparing a shallow trench structure and a semiconductor device, the preparation method comprising the following steps: providing a substrate, the substrate comprising a base plate, a first oxide layer and a first nitride layer stacked in sequence, the substrate being formed with a plurality of first grooves, the first grooves penetrating the first nitride layer and the first oxide layer and extending to the substrate; growing a second oxide layer on the substrate; depositing a stress-conforming layer on the substrate; etching and removing the surface of the first nitride layer and the stress-conforming layer of the first groove; generating a third oxide layer on the substrate; and filling the plurality of first grooves of the substrate.

[0041] In the preparation method of the shallow trench structure of the present invention, a nitride layer is deposited as a stress-covariant layer after an oxide layer is grown in the shallow trench structure. The process parameters for depositing the stress-covariant layer can be adjusted according to the target performance of the semiconductor structure to obtain the required stress type, thereby achieving the function of adjusting the stress in the active area of ​​the semiconductor device, improving the current transmission characteristics of the complementary metal oxide semiconductor (CMOS) device, and enhancing the response speed and other electrical properties of the device.

[0042] The following further describes the method for preparing the shallow trench structure and the semiconductor device of the present invention in conjunction with the accompanying drawings and specific embodiments. It should be understood that the various specific embodiments are not intended to limit the protection scope of the present invention.

[0043] Figure 1 The flowchart of the method for preparing the shallow trench structure according to one embodiment of the present invention is as follows. Specifically, the method for preparing the shallow trench structure includes the following steps:

[0044] A first aspect of the present invention provides a method for preparing a shallow trench structure, the method comprising the following steps:

[0045] Step S100: providing a substrate, the substrate comprising a base plate 10, a first oxide layer 20 and a first nitride layer 30 stacked in sequence, a plurality of first grooves C are formed on the substrate, the first grooves C penetrate the first nitride layer 30 and the first oxide layer 20 and extend to the base plate 10, Figure 2 . As an example, the substrate 10 can be made of semiconductor materials, insulating materials, conductive materials or any combination of their material types. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 10 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator. The substrate 10 can be an N-type or a P-type. In step S100, the substrate can be prepared by the following steps: depositing a first oxide layer 20 and a first nitride layer 30 on a substrate 10 in sequence as hard mask layers, the thickness of the first oxide layer 20 can be between 100 angstroms and 200 angstroms, and the thickness of the first nitride layer can be between 1000 angstroms and 2000 angstroms; then patterning the hard mask layer; and finally etching the substrate using the patterned hard mask layer as a mask to form a plurality of first trenches C in the substrate. The structure of the first trenches C is determined according to the structure of the target semiconductor device.

[0046] Step S200: growing a second oxide layer on the substrate. The second oxide layer may be a silicon oxide layer. In actual operation, the in-situ steam oxidation (ISSG) process may be used to grow the second oxide layer on the substrate, that is, the ISSG process is used to grow the STI liner oxide (Liner Oxide). The in-situ steam oxidation process is a micro-nano processing process. The process mainly utilizes the strong oxidizing effect of atomic oxygen generated in the ISSG reaction to generate an ultra-thin, high-quality oxide film layer on the surface of the substrate. The second oxide layer grown by this process covers the side wall surface of the first trench C in the substrate 10 (second oxide layer 40a), the side wall surface of the first trench C in the first nitride layer 30 and the first oxide layer 20 (second oxide layer 40b), and the surface of the first nitride layer 30 (second oxide layer 40c), see Figure 3 The oxide film layer grown by ISSG fully repairs the surface, so that the defects in the final oxide film layer are reduced and has good optical, electrical and mechanical properties. Preferably, the thickness of the second oxide layer is between 40 angstroms and 150 angstroms.

[0047] Step S300: depositing a stress-compatible layer on the substrate after step S200. In one embodiment, the stress-compatible layer is a silicon nitride layer. Preferably, the thickness of the stress-compatible layer is between 100 angstroms and 200 angstroms, such as 100 angstroms, 120 angstroms, 150 angstroms, 160 angstroms or 180 angstroms. In step S300, a chemical vapor deposition (CVD) process with a high deposition rate and capable of ensuring uniformity and compactness of the thin film may be used to deposit the stress-compatible layer. The stress-compatible layer covers the sidewall surface of the first groove C in the substrate 10 (stress-compatible layer 50a), the sidewall surface of the first groove C in the first nitride layer 30 and the first oxide layer 20 (stress-compatible layer 50b), and the surface of the first nitride layer 30 (stress-compatible layer 50c), see Figure 4 .

[0048] It should be noted that the stress type of the stress covariant layer of the present invention is determined according to the type of the target semiconductor device or the structural type of the substrate. When the structural type of the substrate is an NMOS structure, the stress covariant layer is a tensile stress layer; at this time, the stress covariant layer of the shallow trench structure applies tensile stress to the active area of ​​the semiconductor device, and the tensile stress increases the electron mobility of the N-type active area, thereby enhancing the mobility of the NMOS transistor. When the structural type of the substrate is a PMOS structure, the stress covariant layer is a compressive stress layer. At this time, the stress covariant layer of the shallow trench structure applies compressive stress to the active area of ​​the semiconductor device, and the compressive stress increases the hole mobility of the P-type active area, thereby enhancing the mobility of the PMOS transistor.

[0049] The stress type of the stress covariant layer can be regulated by controlling the process parameters when depositing the stress covariant layer using the chemical vapor deposition process. The process parameters of chemical vapor deposition include RF power, gas, and flow spacing. For example, by adjusting the RF power, the density and energy of the plasma can be controlled, thereby affecting the deposition rate and quality of the film. Appropriate RF power can ensure the uniformity and density of the film.

[0050] In practice, for a target semiconductor device (a substrate structure), different stress-covariant layers can be obtained under different chemical vapor deposition process parameters, and the substrate offline pressure (Offline Stress) of these stress-covariant layers with different deposition processes can be detected, so as to obtain the stress type of the stress-covariant layer deposited by different chemical vapor deposition processes on the substrate structure. For example, if the offline pressure is a positive value, the stress-covariant layer is a tensile stress layer; if the offline pressure is a negative value, the stress-covariant layer is a compressive stress layer. Generally, a relatively low (lower than an RF power threshold) RF power obtains a tensile stress-covariant layer, at which time, the NH bond breaks during the deposition of the silicon nitride layer, causing the film to shrink and bring about internal tensile stress; and a relatively high (higher than the RF power threshold) RF power obtains a compressive stress-covariant layer, but the RF power thresholds of different substrate structures are different. After obtaining the mapping data of the chemical vapor deposition process parameters of the stress-covariant layer on the above-mentioned substrate structure and the stress type of the stress-covariant layer, the chemical vapor deposition process parameters can be determined according to the type of the target semiconductor device.

[0051] Step S400: etching and removing the surface of the first nitride layer 30 and the stress-cooperative layer on the sidewalls of the first nitride layer 30 and the first oxide layer 20 of the first trench C, that is, etching and removing the stress-cooperative layer 50b and the stress-cooperative layer 50c, and the stress-cooperative layer 50a is retained on the sidewalls of the first trench. Figure 5 . In step S400, a dry etching (DryEtch) process can be used to etch and remove the stress covariant layer 50b and the stress covariant layer 50c. The dry etching process can be a reactive ion etching (Reactive Ion Etch, RIE) process. Compared with the wet etching process, the dry etching process can provide higher selectivity. Specifically, the substrate with a patterned photoresist layer after step S300 can be placed in a plasma reaction chamber, and then the etching reaction gas is introduced. At the same time, the radio frequency power generated by the radio frequency power supply is fed between the upper and lower electrodes of the plasma reaction chamber to ionize the reaction gas to generate plasma. The more commonly used reaction gases include mixed gases such as SF6, CF4, O2 and / or Ar. Different reaction gases can be selected according to the parameters of the device to obtain the desired etching speed and etching depth.

[0052] Step S500: generating a third oxide layer on the substrate after step S400; similarly, in step S500, an in-situ water vapor oxidation process can be used to generate a third oxide layer on the stress covariant layer of the side wall of the first trench at the substrate. The third oxide layer can be a silicon oxide layer. Preferably, the thickness of the third oxide layer is between 20 angstroms and 50 angstroms. The third oxide layer is not shown in the figure.

[0053] Step S600: Filling a plurality of first trenches C of a substrate with a plurality of shallow trench structures. Specifically, filling a plurality of first trenches C of a substrate with a plurality of shallow trench structures includes the following steps:

[0054] Step S610: depositing a filling layer 60 on the substrate after step S500, see Figure 6 ;as well as

[0055] Step S620: Planarize the filling layer 60, see Figure 7 .

[0056] The material of the filling layer 60 may be amorphous silicon oxide. The amorphous silicon oxide filling may be carried out by using a HARP (High Aspect Ratio Process) process, that is, using sub-atmospheric pressure chemical vapor deposition (SACVD). 3 / The thermochemical reaction of TEOS has a high deposition rate and is suitable for high aspect ratio structures. Accordingly, the shallow trench structure formed by the subatmospheric pressure chemical vapor deposition SACVD process has better isolation performance, and the above-mentioned shallow trench structure can achieve the effect of high voltage isolation. The planarization filling layer 60 can be implemented by a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process. In some other embodiments, in order to improve the quality of the filling layer 60, after the filling layer 60 is deposited on the substrate after step S500, or before the step of planarizing the filling layer, the preparation method also includes the following steps:

[0057] Step S611: Annealing the substrate with the filling layer deposited thereon. The annealing temperature of step S611 can be 1000°C for 30 minutes. Hydrogen and nitrogen are introduced during the annealing process, wherein hydrogen is used to repair the interface and nitrogen is used as a protective gas. Annealing can increase the density of the gap fill while transferring the stress applied by the stress covariant layer to the active area of ​​the substrate.

[0058] The present invention also provides a semiconductor device, which includes a plurality of shallow trench structures, and the shallow trench structures are obtained by the preparation method. The semiconductor device can be an NMOS or PMOS device, and in the NMOS device, tensile stress is applied to the active region of the NMOS device through the stress covariant layer in the shallow trench structure, thereby improving the electron mobility of the active region of the NMOS device. Similarly, in the PMOS device, compressive stress is applied to the active region of the NMOS device through the stress covariant layer in the shallow trench structure, thereby improving the hole mobility of the active region of the PMOS device.

[0059] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

[0060] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a shallow trench structure, characterized in that: The preparation method comprises the following steps: Providing a substrate, the substrate comprising a base plate, a first oxide layer and a first nitride layer stacked in sequence, the substrate being formed with a plurality of first trenches, the first trenches penetrating the first nitride layer and the first oxide layer and extending to the base plate; growing a second oxide layer on the substrate; depositing a stress-covariant layer on the substrate; Etching and removing the surface of the first nitride layer and the stress-compatible layer on the sidewalls of the first nitride layer and the first oxide layer of the first trench; generating a third oxide layer on the substrate; The plurality of first trenches of the substrate are filled to form a plurality of shallow trench structures.

2. The method for preparing a shallow trench structure according to claim 1, characterized in that: When the structure type of the substrate is an NMOS structure, the stress covariant layer is a tensile stress layer; When the structure type of the substrate is a PMOS structure, the stress-covariant layer is a compressive stress layer.

3. The method for preparing a shallow trench structure according to claim 1, characterized in that: The stress-compatible layer is deposited on the substrate by using a chemical vapor deposition process.

4. The method for preparing a shallow trench structure according to claim 1, characterized in that: The stress-compatible layer is a silicon nitride layer.

5. The method for preparing a shallow trench structure according to claim 1, characterized in that: The thickness of the stress-compatible layer is between 100 angstroms and 200 angstroms.

6. The method for preparing a shallow trench structure according to claim 1, characterized in that: growing the second oxide layer on the substrate using an in-situ steam oxidation process; and / or The third oxide layer is grown on the stress-compatible layer on the sidewall of the first trench at the substrate by an in-situ steam oxidation process.

7. The method for preparing a shallow trench structure according to claim 1, characterized in that: A dry etching process is adopted to etch and remove the surface of the first nitride layer and the stress-compatible layer in the first trench.

8. The method for preparing a shallow trench structure according to claim 1, characterized in that: The step of filling the first plurality of trenches of the substrate comprises the following steps: depositing a fill layer on the substrate; The filling layer is planarized.

9. The method for preparing a shallow trench structure according to claim 8, characterized in that: Before the step of planarizing the filling layer, the preparation method further comprises the following steps: The substrate on which the filling layer is deposited is subjected to an annealing process.

10. A semiconductor device, characterized in that: The semiconductor device comprises a plurality of the shallow trench structures, and the shallow trench structures are obtained by using the preparation method described in any one of claims 1 to 9.

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