Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A method for manufacturing a semiconductor device includes: forming a first semiconductor structure including a logic transistor; forming a second semiconductor structure; the first semiconductor structure is bonded to the second semiconductor structure, and the step of forming the first semiconductor structure comprises the steps that a first substrate is formed; forming a first wiring layer on the first substrate, wherein the first wiring layer comprises a plurality of first metal wires and a plurality of first through holes; a first bonding isolation layer is formed on the first wiring layer, and the step of forming the second semiconductor structure comprises the substeps of forming a second substrate; forming a second wiring layer on the second substrate, wherein the second wiring layer comprises a plurality of second metal wires and a plurality of second through holes; forming a plurality of dummy plugs in the second wiring layer; forming a plurality of holes vertically through the second substrate to portions where the plurality of dummy plugs are formed, where the plurality of holes are formed after bonding the first semiconductor structure to the second semiconductor structure; and removing the plurality of dummy plugs.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Application No. 10-2023-0133059, filed on October 6, 2023, which is incorporated herein by reference in its entirety as a part of the disclosure of this application. Technical Field

[0003] Various embodiments of the disclosed technology relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method of manufacturing the same in which a lower wafer and an upper wafer are bonded to each other. Background Art

[0004] In order to increase the integration density of semiconductor devices, technical development of stacked semiconductor devices is underway, which reduces chip area by integrating required circuits or components on two substrates (ie, an upper substrate and a lower substrate) and bonding the two substrates to each other.

[0005] Components on the upper substrate and the lower substrate bonded to each other should be electrically connected, and dielectric bonding or hybrid bonding is used for such electrical connection. Summary of the invention

[0006] The disclosed technology may be implemented in some embodiments to provide a semiconductor device and a method of manufacturing the same that can minimize size limitations when connecting metal wirings between upper and lower wafers.

[0007] One embodiment is a method for manufacturing a semiconductor device, comprising: forming a first semiconductor structure including a logic transistor; forming a second semiconductor structure; bonding the first semiconductor structure to the second semiconductor structure, wherein forming the first semiconductor structure comprises: forming a first substrate; forming a first wiring layer including a plurality of first metal wirings and a plurality of first vias on the first substrate; forming a first bonding isolation layer on the first wiring layer, wherein forming the second semiconductor structure comprises: forming a second substrate; forming a second wiring layer including a plurality of second metal wirings and a plurality of second vias on the second substrate; forming a plurality of dummy plugs in the second wiring layer, forming a plurality of holes vertically passing through the second substrate to a portion where the plurality of dummy plugs are formed, wherein the plurality of holes are formed after the first semiconductor structure is bonded to the second semiconductor structure; and removing the plurality of dummy plugs.

[0008] Forming the plurality of dummy plugs may include forming the plurality of dummy plugs from an upper portion of the second wiring layer to an upper portion of the second substrate in a vertical direction.

[0009] The method for manufacturing a semiconductor device may also include: forming a plurality of second metal wirings in an upper portion of a second wiring layer, the second wiring layer including an upper region of a plurality of dummy plugs; and forming a plurality of punching holes vertically passing through the plurality of second metal wirings formed in the upper region of the dummy plugs.

[0010] The method for manufacturing a semiconductor device may further include: additionally forming a plurality of dummy plugs in an inner space of the punched hole of the second semiconductor structure.

[0011] The method for manufacturing a semiconductor device may further include forming a second bonding isolation layer on the second wiring layer after additionally forming a plurality of dummy plugs in the inner space of the through-hole of the second semiconductor structure.

[0012] Bonding the first semiconductor structure to the second semiconductor structure may include bonding a first bonding isolation layer to a second bonding isolation layer.

[0013] The method for manufacturing a semiconductor device may further include forming a plurality of third vias by etching a first capping nitride layer, a first bonding isolation layer, and a second bonding isolation layer formed on the plurality of first metal wirings after removing the plurality of dummy plugs.

[0014] The method for manufacturing a semiconductor device may further include forming a spacer oxide layer on sidewalls of the plurality of third through holes.

[0015] The method for manufacturing a semiconductor device may further include etching a spacer oxide layer formed on a boundary surface between the plurality of third vias and the plurality of first metal wirings.

[0016] The method for manufacturing a semiconductor device may further include forming a barrier metal layer on the second substrate, the spacer oxide layer, and the plurality of first metal wirings.

[0017] The method of manufacturing a semiconductor device may further include forming an amorphous carbon layer on the barrier metal layer.

[0018] The method of manufacturing a semiconductor device may further include: after forming the amorphous carbon layer, forming a plurality of contact plugs within the plurality of third via holes.

[0019] The method of manufacturing a semiconductor device may further include removing the amorphous carbon layer after forming the plurality of contact plugs.

[0020] The method for manufacturing a semiconductor device may further include removing a portion of the barrier metal layer formed in an upper region of the second substrate after removing the amorphous carbon layer.

[0021] The method for manufacturing a semiconductor device may further include forming a pixel array on the second substrate after removing the barrier metal layer.

[0022] Forming a pixel array on the second substrate includes forming photodiodes, isolation layers, color filters, and microlenses.

[0023] Another embodiment is a semiconductor device. The semiconductor device may include: a first semiconductor structure, the first semiconductor structure including a first substrate, a first isolation layer formed on the first substrate and embedded with a first wiring structure, and a first bonding isolation layer formed on the first isolation layer; a second semiconductor structure, the second semiconductor structure including a second substrate, a second isolation layer formed below the second substrate and embedded with a second wiring structure, and a second bonding isolation layer formed below the second isolation layer and bonded to the first bonding isolation layer; a through electrode formed to pass through the second substrate, the second isolation layer, the second bonding isolation layer, and the first bonding isolation layer, and connected to a first conductive pattern formed on top of the first isolation layer; and a metal pattern formed to surround at least a portion of the sidewall of a portion of the through electrode formed between the second substrate and the second bonding isolation layer.

[0024] The first wiring structure may include a plurality of first conductive patterns and a plurality of first vias.

[0025] The second wiring structure may include a plurality of second conductive patterns and a plurality of second vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a block diagram of an image sensing device according to an embodiment of the present disclosure.

[0027] Figures 2 to 15 is a view for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Features and certain advantages associated with specific embodiments of the technology disclosed in this application are described by way of example embodiments with reference to the accompanying drawings.

[0029] When a dielectric bonding process is used, a film accumulated during the formation of a metal line, a transistor (TR), and a through silicon via (TSV) through an upper wafer should be etched, and thus, there is a problem of limitation on contact size and layout.

[0030] The use of a hybrid bonding process can overcome the arrangement limitations. However, there are also problems of increased cost and yield. In some embodiments, by providing a dummy plug in an area of ​​the upper wafer where the upper wafer and the lower wafer need to be connected, removing the dummy plug during wafer bonding and TSV processes, and performing additional etching to form a butt contact, the size limitations when connecting the metal wiring of the upper wafer and the lower wafer can be minimized. In some embodiments, by applying dielectric bonding, costs can be reduced compared to hybrid bonding.

[0031] In some embodiments, by providing a dummy plug in an area of ​​the upper wafer where the upper wafer and the lower wafer need to be connected, removing the dummy plug during wafer bonding and TSV processes, and performing additional etching to form a butt contact, the size limitation in metal wiring connecting the upper wafer and the lower wafer can be minimized. In some embodiments, by applying dielectric bonding, the cost can be reduced compared to hybrid bonding.

[0032] Figure 1 is a block diagram of an image sensing device according to an embodiment of the present disclosure.

[0033] refer to Figure 1 , an image sensing device according to an embodiment may include a pixel array 1100, a row driver 1200, a correlated double sampler (CDS) 1300, an analog-to-digital converter (ADC) 1400, an output buffer 1500, a column driver 1600, a timing controller 1700, and a bias generator 1800. The components of the image sensing device shown are discussed only by way of example, and the present application includes addition or omission of components when necessary.

[0034] The pixel array 1100 may include a plurality of pixels arranged in a plurality of rows and a plurality of columns. In an embodiment, a plurality of pixels may be arranged in a two-dimensional pixel array including rows and columns. In another example, a plurality of unit imaging pixels may be arranged in a three-dimensional pixel array. A plurality of pixels may convert an optical signal into an electrical signal based on a unit pixel or based on a pixel group, and the pixels in the pixel group share at least some internal circuits. The pixel array 1100 may receive a drive signal from a row driver 1200, the drive signal including a row selection signal, a pixel reset signal, and a transfer signal. Upon receiving the drive signal, the corresponding pixel in the pixel array 1100 may be activated to perform operations corresponding to the row selection signal, the pixel reset signal, and the transfer signal.

[0035] The row driver 1200 may activate the pixel array 1100 based on the command and control signals provided by the timing controller 1700 to perform certain operations on the pixels in the corresponding row. In an embodiment, the row driver 1200 may select at least one pixel arranged in at least one row of the pixel array 1100. The row driver 1200 may generate a row selection signal to select at least one row of the plurality of rows. The row driver 1200 may sequentially enable a pixel reset signal and a transmission signal for pixels corresponding to at least one selected row. Therefore, a reference signal and an image signal as an analog signal generated by each pixel of the selected row may be sequentially transmitted to a correlated double sampler (CDS) 1300. At this time, the reference signal may be an electrical signal provided to the correlated double sampler (CDS) 1300 when a sensing node (e.g., a floating diffusion node) of a pixel is reset, and the image signal may be an electrical signal provided to the correlated double sampler (CDS) 1300 when a photocharge generated by a pixel is accumulated in a sensing node. The reference signal representing the reset noise inherent in the pixel and the image signal representing the incident light intensity may be collectively referred to as a pixel signal.

[0036] A complementary metal oxide semiconductor (CMOS) image sensor may use correlated double sampling (CDS) to remove an undesired offset value of a pixel, called fixed pattern noise, by sampling the pixel signal twice to remove the difference between the two samples. In some embodiments, correlated double sampling (CDS) may remove an undesired offset value of a pixel by comparing the pixel output voltage obtained before and after the photocharge generated by the incident light is accumulated in the sensing node, so that only the pixel output voltage based on the incident light may be measured. In one embodiment, correlated double sampling (CDS) 1300 may sequentially sample and hold a reference signal and an image signal provided to each of a plurality of column lines from the pixel array 1100. That is, correlated double sampling (CDS) 1300 may sample and hold a reference signal and an image signal corresponding to each column of the pixel array 1100.

[0037] The correlated double sampling (CDS) 1300 may transmit a reference signal and an image signal of each column as a correlated double sampling signal to an analog-to-digital converter (ADC) 1400 based on a control signal from the timing controller 1700 .

[0038] The analog-to-digital converter (ADC) 1400 is used to convert the correlated double sampling (CDS) signal for each column into a digital signal and output the digital signal. In one embodiment, the analog-to-digital converter (ADC) 1400 can be implemented as a ramp comparison type analog-to-digital converter (ADC). The ramp comparison type analog-to-digital converter (ADC) may include a comparator circuit and a counter, the comparator circuit is used to compare the analog pixel signal with a ramp signal that ramps up or ramps down over time, and the counter counts until the ramp signal matches the analog pixel signal. In one embodiment, the analog-to-digital converter (ADC) 1400 can convert the correlated double sampling signal generated by the correlated double sampling (CDS) 1300 for each column into a digital signal and output the digital signal.

[0039] The analog-to-digital converter (ADC) 1400 may include a plurality of column counters corresponding to each column of the pixel array 1100. Each column of the pixel array 1100 is coupled to the column counter, and image data may be generated by converting a correlated double sampling signal corresponding to each column into a digital signal using the column counter. In another embodiment of the disclosed technology, the analog-to-digital converter (ADC) 1400 may include a global counter to convert a correlated double sampling signal corresponding to each column into a digital signal using a global code provided from the global counter.

[0040] The output buffer 1500 may temporarily hold the column-based image data provided from the analog-to-digital converter (ADC) 1400 to output the image data. The output buffer 1500 may temporarily store the image data output from the analog-to-digital converter (ADC) 1400 based on a control signal of the timing controller 1700. The output buffer 1500 may be used as an interface to compensate for a data rate difference or a transmission (or processing) rate difference between the image sensing apparatus and other devices.

[0041] The column driver 1600 may select a column of the output buffer 1500 based on a control signal from the timing controller 1700, and sequentially output the image data temporarily stored in the selected column of the output buffer 1500. In one embodiment, when receiving an address signal from the timing controller 1700, the column driver 1600 may generate a column selection signal based on the address signal and select a column of the output buffer 1500, and output the image data from the selected column of the output buffer 1500 as an output signal.

[0042] The timing controller 1700 may control at least one of the row driver 1200 , the correlated double sampling (CDS) 1300 , the analog-to-digital converter (ADC) 1400 , the output buffer 1500 , the column driver 1600 , and the bias generator 1800 .

[0043] The timing controller 1700 may provide a clock signal required for the operation of the corresponding components of the image sensing device, a control signal for timing control, an address signal for selecting a row or column, and a signal for controlling the level of a bias voltage applied to the pixel array 1100, etc. to at least one of the row driver 1200, the correlated double sampling (CDS) 1300, the analog-to-digital converter (ADC) 1400, the output buffer 1500, the column driver 1600, and the bias generator 1800. In an embodiment of the present disclosure, the timing controller 1700 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, etc.

[0044] The bias generator 1800 may generate a bias voltage for suppressing a dark current generated in pixels of the pixel array 1100 , and provide the generated bias voltage to the pixel array 1100 .

[0045] The bias voltage may be determined during wafer probe testing of the image sensing device and stored in a one-time programmable (OTP) memory. For example, the bias voltage may be experimentally determined to be a value that can maximize the dark current suppression effect and minimize unnecessary power consumption without impairing the performance of the image sensing device.

[0046] The bias generator 1800 may generate a voltage corresponding to a bias voltage stored in a one-time programmable (OTP) memory. According to an embodiment, the one-time programmable (OTP) memory may be included in the image sensing device, and in particular, may be included in the bias generator 1800.

[0047] According to an embodiment, the bias voltage may include a plurality of values.

[0048] For example, the plurality of values ​​may correspond to a plurality of operating modes of the image sensing device, respectively. The dark current generated under weak light and the dark current generated under strong light may be different from each other, and the bias voltage provided by the bias generator 1800 for effectively suppressing the dark current in each environment may vary according to the mode.

[0049] Alternatively, the plurality of values ​​may respectively correspond to a plurality of regions of the pixel array 1100. The generated dark currents may be different from each other according to the positions of the pixels in the pixel array 1100, and the bias voltage provided by the bias generator 1800 to effectively suppress the dark current regardless of the position of the pixel may vary according to the region.

[0050] The bias voltage may be a negative voltage having a negative sign, but the present disclosure is not limited thereto.

[0051] Figures 2 to 15 is a view for describing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0052] A method for manufacturing a semiconductor device according to an embodiment of the present disclosure may include: forming a first semiconductor structure 100 including a logic transistor; forming a second semiconductor structure 200 to be bonded to the first semiconductor structure 100; and bonding the first semiconductor structure 100 and the second semiconductor structure 200 to each other.

[0053] In an embodiment of the present disclosure, the first semiconductor structure 100 may be a logic chip including logic transistors such as a row driver, a correlated double sampler (CDS), an analog-to-digital converter (ADC), an output buffer, a column driver, a timing controller, and a bias generator.

[0054] In an embodiment of the present disclosure, the second semiconductor structure 200 may be a pixel wafer including a pixel array.

[0055] Figure 2 is a cross-sectional view schematically showing a first semiconductor structure. Figure 2 , forming the first semiconductor structure 100 may include: forming a first substrate 110; forming a first wiring layer (or a first isolation layer) 120 on the first substrate 110, the first wiring layer (or a first isolation layer) 120 including a plurality of first metal wirings (or a first conductive pattern) 121 and a plurality of first through holes 122; and forming a first bonding isolation layer 130 on the first wiring layer 120.

[0056] The first substrate 110 may include a semiconductor substrate. The semiconductor substrate may be in a single crystal state and may include a silicon-containing material.

[0057] The first substrate 110 may be a substrate that has been thinned by a thinning process (wafer thinning process). In an embodiment of the present disclosure, the first substrate 110 may be a bulk silicon substrate that has been thinned by a thinning process. In an embodiment of the present disclosure, the first substrate 110 may include p-type impurities (or n-type impurities).

[0058] The first wiring layer 120 may be formed on the first substrate 110 , and may include a device isolation layer 11 , a plurality of junction regions (not shown) and gate electrodes 12 , a plurality of first metal wirings 121 , and a plurality of first vias 122 .

[0059] The device isolation layer 11 may electrically isolate adjacent transistors from each other and may include an insulating material.

[0060] The junction region (not shown) may include one of an n-type region including n-type impurity ions such as phosphorus (P) or arsenic (As) and a p-type region including p-type impurity ions such as boron (B).

[0061] The gate electrode 12 may include a conductive material such as metal or doped polysilicon.

[0062] A plurality of junction regions (not shown) may function as drain electrodes and / or source electrodes of the logic transistors.

[0063] Various logic transistors may be formed by a plurality of junction regions (not shown) and the gate electrode 12. A plurality of logic transistors may form various logic circuits.

[0064] The plurality of first metal wirings 121 and the plurality of first vias 122 may include a conductive material such as a metal, or doped polysilicon. In an embodiment of the present disclosure, the plurality of first metal wirings 121 and the plurality of first vias 122 may include: a metal such as tungsten (W), copper (Cu), aluminum (Al), and titanium (Ti), a metal compound such as titanium nitride (TiN), or a metal silicide such as tungsten silicide (WSi) or titanium silicide (TiSi).

[0065] Electrical signals may be transmitted between vertical layers through the plurality of first vias 122 .

[0066] A first bonding isolation layer 130 may be formed on the first wiring layer 120 .

[0067] The first bonding isolation layer 130 may be formed by oxide deposition and chemical mechanical polishing (CMP) processes.

[0068] Figure 3 is a cross-sectional view schematically showing a second semiconductor structure. Figure 3 , forming the second semiconductor structure 200 may include: forming a second substrate 210; forming a second wiring layer (or a second isolation layer) 220 on the second substrate 210, the second wiring layer (or a second isolation layer) 220 including a plurality of second metal wirings (or a second conductive pattern) 221 and a plurality of second through holes 222; and forming a dummy plug D in a region of the second wiring layer 220.

[0069] The second substrate 210 may include a semiconductor substrate. The semiconductor substrate may be in a single crystal state and may include a silicon-containing material.

[0070] The second substrate 210 may be a substrate that has been thinned by a thinning process. In an embodiment of the present disclosure, the second substrate 210 may be a bulk silicon substrate that has been thinned by a thinning process. In an embodiment, the second substrate 210 may include p-type impurities (or n-type impurities).

[0071] The plurality of second metal wirings 221 and the plurality of second vias 222 may include a conductive material such as a metal, or doped polysilicon. In an embodiment, the plurality of second metal wirings 221 and the plurality of second vias 222 may include a metal such as tungsten (W), copper (Cu), aluminum (Al), and titanium (Ti), a metal compound such as titanium nitride (TiN), or a metal silicide such as tungsten silicide (WSi) or titanium silicide (TiSi).

[0072] Electrical signals may be transmitted between vertical layers through the plurality of second vias 222 .

[0073] refer to Figure 3 , a dummy plug D may be formed in one region of the second wiring layer 220 by a process of forming a pattern using a contact mask, etching, and deposition. The dummy plug D may include a conductive metal material. The dummy plug D may be formed from the upper portion of the one region of the second wiring layer 220 to the upper portion of the second substrate 210 in a vertical direction.

[0074] Figure 4 and Figure 5 is a top view of a lower layer according to an embodiment of the present disclosure.

[0075] refer to Figures 4 to 6 , the second metal wiring 221 may be formed in the upper region of the second wiring layer 220 by a process of forming a pattern using a metal mask, etching, and deposition.

[0076] refer to Figure 4 , Figure 4 The formation of a plurality of punch holes H1 vertically penetrating the second metal wiring 221 in the upper region of the dummy plug D formed in the second wiring layer 220 is shown.

[0077] refer to Figure 5 and Figure 6 After forming the punch hole H1 , a dummy plug D may be additionally formed in the inner space of the punch hole H1 through the process of forming a barrier metal BM and depositing a conductive metal material.

[0078] refer to Figure 7 After forming the dummy plug D, a second bonding isolation layer 230 may be formed on the second wiring layer 220 .

[0079] The second bonding isolation layer 230 may be formed by oxide deposition and chemical mechanical polishing (CMP) processes.

[0080] refer to Figure 7 , after forming the second bonding isolation layer 230 , the first bonding isolation layer 130 of the first semiconductor structure 100 and the second bonding isolation layer 230 of the second semiconductor structure 200 may be dielectrically bonded to each other.

[0081] By applying dielectric bonding, the cost can be reduced compared to the case where hybrid bonding is applied.

[0082] refer to Figure 7 After the first bonding isolation layer 130 and the second bonding isolation layer 230 are bonded to each other, a hole H2 from the photoresist layer 250 to a portion where the dummy plug D is formed may be formed by an etching process using a TSV (Through Silicon Via) mask.

[0083] The hole H2 may be formed to vertically penetrate the passivation layer 240 and the second substrate 210 .

[0084] refer to Figure 4 , 5 7, a dummy plug D may be formed in the second wiring layer 220, and may be formed in a vertical direction from a second metal wiring 221 adjacent to the second bonding isolation layer 230 among the plurality of second metal wirings 221 to a region adjacent to the second substrate 210. In the second metal wiring 221 adjacent to the second bonding isolation layer 230, a punch hole H1 may be formed to vertically pass therethrough, and the dummy plug D may be formed in an inner space of the punch hole H1.

[0085] refer to Figure 8 After forming the hole H2 vertically passing through the second substrate 210 , the photoresist layer 250 and the dummy plug D may be removed by photoresist stripping and etching processes.

[0086] In subsequent processing, an oxide dip-out may be performed to connect the butt contacts.

[0087] refer to Fig. 9 After removing the dummy plug D, a third through hole H3 may be formed by etching the first capping nitride layer 123 , the first bonding isolation layer 130 , and the second bonding isolation layer 230 formed on the first metal wiring 121 .

[0088] refer to Fig.10 After forming the third through hole H3 , a spacer oxide layer 224 may be formed on the sidewall of the third through hole H3 .

[0089] After forming the spacer oxide layer 224 , the spacer oxide layer 224 formed on the boundary surface between the third via H3 and the first metal wiring 121 may be etched.

[0090] refer to Fig.11 After etching the spacer oxide layer 224 below the third through hole H3 , a barrier metal layer (or metal pattern) 225 may be formed on the passivation layer 240 , the spacer oxide layer 224 , and the first metal wiring 121 .

[0091] refer to Fig.12 After forming the barrier metal layer 225, an amorphous carbon layer (ACL) 260 may be formed on the barrier metal layer 225, and the amorphous carbon layer 260 on the sidewall of the third through hole H3 and the amorphous carbon layer 260 under the third through hole H3 may be removed.

[0092] refer to Fig.13 After the amorphous carbon layer 260 is removed, a contact plug (or through electrode) 226 may be formed inside the third through hole H3.

[0093] In an embodiment, contact plug 226 may include copper (Cu). Copper (Cu) may be deposited only in regions where the seed copper (Cu) is exposed.

[0094] By forming butting contacts by removing dummy plugs and performing additional etching when performing wafer bonding and TSV, size limitations during metal wiring connecting the first semiconductor structure (or upper wafer) and the second semiconductor structure (or lower wafer) may be minimized.

[0095] refer to Fig.14 After the contact plug 226 is formed, the amorphous carbon layer 260 may be removed, and the barrier metal layer 225 formed in the upper region of the second substrate 210 among the seed copper (Cu) and the barrier metal layer 225 may be removed.

[0096] refer to Fig.15 After removing the barrier metal layer 225 , a pixel array including a photodiode (not shown), an isolation layer (deep trench isolation layer, DTI) 270 , a color filter 280 , and a microlens 290 may be formed on the second substrate 210 .

[0097] refer to Figure 2 , Figure 4 , Figure 5 , Figure 6 and Fig.15 , a semiconductor device according to an embodiment may include a first semiconductor structure 100 and a second semiconductor structure 200 .

[0098] The first semiconductor structure 100 may be formed on a first substrate 110 and may include a first wiring layer 120 including a plurality of first metal wirings 121 and a plurality of first vias 122 , and a first bonding isolation layer 130 formed on the first wiring layer 120 .

[0099] Before bonding to the first semiconductor structure 100, the second semiconductor structure 200 may form a dummy plug D in a vertical direction in a region of the second wiring layer 220, form a punch hole H1 vertically passing through the second metal wiring 221 (the second metal wiring 221 is formed on the dummy plug D), and further form a dummy plug D in the internal space of the punch hole H1.

[0100] The second semiconductor structure 200 may include: a second bonding isolation layer 230 bonded to the first bonding isolation layer 130, a second wiring layer 220 formed on the second bonding isolation layer 230 and including a plurality of second metal wirings 221 and a plurality of second vias 222, and a second substrate 210 formed on the second wiring layer 220. The second semiconductor structure 200 may include a contact plug 226 formed to pass through the second substrate 210, the second wiring layer 220, the second bonding isolation layer 230, and the first bonding isolation layer 130.

[0101] Descriptions about each configuration of the first semiconductor structure 100 and the second semiconductor structure 200 are the same as described above, and thus descriptions thereof will be omitted.

[0102] refer to Figure 2 , Figure 4 , Figure 5 , Figure 6 and Fig.15 , the semiconductor device according to the embodiment of the present disclosure may include a first semiconductor structure 100 , a second semiconductor structure 200 , a through electrode 226 , and a metal pattern 225 .

[0103] The first semiconductor structure 100 may include a first substrate 110 , a first isolation layer 120 formed on the first substrate 110 and embedded with a plurality of first wiring structures 121 and 122 , and a first bonding isolation layer 130 formed on the first isolation layer 120 .

[0104] The second semiconductor structure 200 may include a second substrate 210 , a second isolation layer 220 formed under the second substrate 210 and embedded with a plurality of second wiring structures 221 and 222 , and a second bonding isolation layer 230 formed under the second isolation layer 220 and bonded to the first bonding isolation layer 130 .

[0105] The through electrode 226 may be formed to pass through the second substrate 210 , the second isolation layer 220 , the second bonding isolation layer 230 , and the first bonding isolation layer 130 , and the through electrode 226 may be connected to the first conductive pattern 121 formed on the top of the first isolation layer 120 .

[0106] The metal pattern 225 may be formed to surround at least a portion of a sidewall of a portion of the through electrode 226 formed between the second substrate 210 and the second bonding isolation layer 230 .

[0107] The first wiring structure may include a plurality of first conductive patterns 121 and a plurality of first vias 122 .

[0108] The second wiring structure may include a plurality of second conductive patterns 221 and a plurality of second vias 222 .

[0109] The descriptions about the first semiconductor structure 100 , the second semiconductor structure 200 , the through-electrode 226 , and the metal pattern 225 are the same as above, and thus descriptions thereof will be omitted.

[0110] According to the present disclosure, by arranging a dummy plug in an area of ​​the upper wafer (the area where the upper wafer and the lower wafer are required to be connected), removing the dummy plug during wafer bonding and TSV processes, and forming a butt contact by additional etching, the size restriction when connecting the metal wiring of the upper wafer and the lower wafer can be minimized. In addition, by applying dielectric bonding, the cost can be reduced compared to the case of applying hybrid bonding.

[0111] Although the present application contains many details, these details should not be interpreted as limitations on the scope of any subject matter or the scope of what may be claimed, but rather as descriptions of features of specific embodiments that may be specific to a particular technology. Certain features described in the present application in the context of different embodiments may also be implemented in a single embodiment in combination. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable sub-combination. In addition, although the above-mentioned features may be described as acting in a particular combination and even initially claimed as such, one or more features in the claimed combination may be deleted from the combination in some cases, and the claimed combination may involve sub-combinations or variations of sub-combinations.

[0112] Only a few implementations and examples of the disclosed technology are described, and other implementations, enhancements, and variations may be made based on what is described and illustrated in this application.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first semiconductor structure, the first semiconductor structure comprising a logic transistor; forming a second semiconductor structure; bonding the first semiconductor structure to the second semiconductor structure, Wherein, forming the first semiconductor structure comprises: forming a first substrate; forming a first wiring layer on the first substrate, the first wiring layer comprising a plurality of first metal wirings and a plurality of first vias; forming a first bonding isolation layer on the first wiring layer, Wherein, forming the second semiconductor structure comprises: forming a second substrate; forming a second wiring layer on the second substrate, the second wiring layer comprising a plurality of second metal wirings and a plurality of second vias; forming a plurality of dummy plugs in the second wiring layer, forming a plurality of holes that vertically penetrate the second substrate to a portion where the plurality of dummy plugs are formed, wherein the plurality of holes are formed after bonding the first semiconductor structure to the second semiconductor structure; and The plurality of dummy plugs are removed.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming the plurality of dummy plugs includes forming the plurality of dummy plugs from an upper portion of the second wiring layer to an upper portion of the second substrate in a vertical direction.

3. The method for manufacturing a semiconductor device according to claim 2, further comprising: forming a plurality of second metal wirings in an upper portion of the second wiring layer, the second wiring layer including an upper region of the plurality of dummy plugs, and A plurality of punch holes are formed that vertically penetrate the plurality of second metal wirings formed in an upper region of the dummy plug.

4. The method for manufacturing a semiconductor device according to claim 3, further comprising: A plurality of dummy plugs are additionally formed in the inner space of the punched hole of the second semiconductor structure.

5. The method for manufacturing a semiconductor device according to claim 4, further comprising: After the plurality of dummy plugs are additionally formed in the inner space of the punched hole of the second semiconductor structure, a second bonding isolation layer is formed on the second wiring layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: Bonding the first semiconductor structure to the second semiconductor structure includes bonding the first bonding isolation layer to the second bonding isolation layer.

7. The method for manufacturing a semiconductor device according to claim 6, further comprising: After removing the plurality of dummy plugs, a plurality of third vias are formed by etching the first capping nitride layer, the first bonding isolation layer, and the second bonding isolation layer formed on the plurality of first metal wirings.

8. The method for manufacturing a semiconductor device according to claim 7, further comprising: A spacer oxide layer is formed on sidewalls of the plurality of third through holes.

9. The method for manufacturing a semiconductor device according to claim 8, further comprising: The spacer oxide layer formed on the boundary surfaces between the plurality of third vias and the plurality of first metal wirings is etched.

10. The method for manufacturing a semiconductor device according to claim 9, further comprising: A barrier metal layer is formed on the second substrate, the spacer oxide layer, and the plurality of first metal wirings.

11. The method for manufacturing a semiconductor device according to claim 10, further comprising: An amorphous carbon layer is formed on the barrier metal layer.

12. The method for manufacturing a semiconductor device according to claim 11, further comprising: After forming the amorphous carbon layer, a plurality of contact plugs are formed in the plurality of third via holes.

13. The method for manufacturing a semiconductor device according to claim 12, further comprising: The amorphous carbon layer is removed after forming the plurality of contact plugs.

14. The method for manufacturing a semiconductor device according to claim 13, further comprising: A portion of the barrier metal layer formed in an upper region of the second substrate is removed after removing the amorphous carbon layer.

15. The method for manufacturing a semiconductor device according to claim 14, further comprising: A pixel array is formed on the second substrate after removing the barrier metal layer.

16. The method for manufacturing a semiconductor device according to claim 15, in, Forming the pixel array on the second substrate includes forming photodiodes, isolation layers, color filters, and microlenses.

17. A semiconductor device comprising: A first semiconductor structure, comprising: a first substrate, a first isolation layer and a first bonding isolation layer, wherein the first isolation layer is formed on the first substrate and embedded with a first wiring structure, and the first bonding isolation layer is formed on the first isolation layer; A second semiconductor structure, comprising: a second substrate, a second isolation layer and a second bonding isolation layer, wherein the second isolation layer is formed below the second substrate and embedded with a second wiring structure, and the second bonding isolation layer is formed below the second isolation layer and bonded to the first bonding isolation layer; a through electrode formed to pass through the second substrate, the second isolation layer, the second bonding isolation layer, and the first bonding isolation layer, and connected to a first conductive pattern formed on top of the first isolation layer; and A metal pattern is formed to surround at least a portion of a side wall of a portion of the through electrode formed between the second substrate and the second bonding isolation layer.

18. The semiconductor device according to claim 17, in, The first wiring structure includes a plurality of first conductive patterns and a plurality of first vias.

19. The semiconductor device according to claim 17, in, The second wiring structure includes a plurality of second conductive patterns and a plurality of second vias.

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