High-performance chip package implementation method

Abstract

The invention discloses a high-performance chip packaging implementation method, and belongs to the technical field of chip packaging, and the method comprises the steps: carrying out the preprocessing of a plurality of chips, including the manufacturing of TSVs in the chips, and the deposition of a layer of dielectric material in the region, where metal is distributed, of the surface of each chip; the substrate is pretreated, wherein a layer of dielectric material is deposited on the face, provided with the bonding pad, of the substrate; bonding the pre-treated chip and the pre-treated substrate together, and bonding the pre-treated chip and the pre-treated substrate together; then, bonding another chip which is subjected to pretreatment on the chip which is subjected to bonding, so as to form a chip module; wherein information interaction is formed between the chiplets which are bonded together by means of TSVs (through silicon vias); according to the invention, high-density interconnection can be realized, time delay is reduced, heterogeneous integration is supported, and a heat dissipation function is considered.

Description

Technical Field

[0001] The invention relates to a high-performance chiplet packaging implementation method, belonging to the technical field of chip packaging. Background Art

[0002] Driven by the growing demand for artificial intelligence, high-performance computing, and large-scale simulation, improving chip performance has become an urgent problem to be solved. Increasing the chip area can integrate more transistors, thereby improving chip performance. However, as the chip size increases, the chip yield decreases, the cost increases, and the process requirements of different modules of the integrated circuit (such as logic and storage modules) are not consistent. Therefore, a large-size SOC chip with all the functions of multiple modules can be disassembled into chiplets (core particles), and each module selects a different process as needed, and finally packaged and integrated together. Among them, to ensure that the performance of each chiplet after packaging is equivalent to that of the original SOC chip, the packaging link needs to shoulder the function of improving chip performance. How to achieve high-density packaging, reduce latency, support heterogeneous integration and take into account heat dissipation are all problems that need to be solved. Summary of the invention

[0003] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a high-performance chiplet packaging implementation method that can achieve high-density interconnection, reduce latency, support heterogeneous integration, and take into account heat dissipation function.

[0004] To achieve the above object, the present invention is implemented by adopting the following technical solutions: In a first aspect, the present invention provides a high-performance chiplet packaging implementation method, comprising: Pre-processing multiple chiplets, including making TSVs inside the chiplets and depositing a layer of dielectric material on the chiplet surface where metal is distributed; Pre-treating the substrate, including depositing a layer of dielectric material on a side of the substrate having a pad; Bonding the pre-processed chiplet to the pre-processed substrate; then bonding another pre-processed chiplet to the bonded chiplet to form a chiplet module; Among them, the chiplets bonded together rely on TSV to form information exchange.

[0005] Furthermore, the method also includes: treating the surface of the chiplet and the substrate to remove surface impurities.

[0006] Furthermore, the height of the metal on the surface of the chip is lower than the height of a layer of deposited dielectric material.

[0007] Furthermore, during the alignment process before bonding, the distance between the chiplet and the substrate and between the chiplets is kept within 50um.

[0008] Furthermore, a plurality of TSVs are fabricated in the chiplet.

[0009] Furthermore, the method also includes: mounting a heat dissipation cover on the surface of the chiplet module.

[0010] Furthermore, the top of the heat dissipation cover cavity is parallel to the substrate, and a slope of a set angle is formed around it.

[0011] Furthermore, the heat dissipation cover is made of a high thermal conductivity material such as copper or graphene.

[0012] Furthermore, the method also includes: adding solder balls on a pad on a side of the substrate away from the chiplet, for interconnecting the chiplet module with other components.

[0013] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a high-performance chiplet packaging implementation method, wherein chiplets are interconnected through TSV to achieve extremely high density interconnection; a hybrid bonding process is used between chiplets and between chiplets and substrates to reduce the resistance and parasitic inductance of the connection channel and reduce the delay; multiple chiplets can flexibly adopt different process steps to support heterogeneous integration; The present invention provides a high-performance chiplet packaging implementation method, which can provide mechanical protection for the chip by attaching a heat dissipation cover, while enhancing heat dissipation, thereby improving chip performance. The top of the heat dissipation cover cavity is parallel to the substrate, and a certain slope is formed around it. While increasing the heat dissipation area, under the same load, the stress is more uniform, the stress concentration coefficient at the corner is smaller, and failure is not easy to occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of a chiplet after preprocessing provided by an embodiment of the present invention; Figure 2 is a schematic diagram of a substrate after pretreatment provided by an embodiment of the present invention; Figure 3 is a schematic diagram of bonding a chiplet and a substrate provided by an embodiment of the present invention; Figure 4 is a schematic diagram of chiplet-to-chiplet bonding provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of bonding various chiplets and substrates provided by an embodiment of the present invention; Figure 6 This is a schematic diagram of adding a heat dissipation cover provided by an embodiment of the present invention; Figure 7 It is a schematic diagram of adding solder balls provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0016] Embodiment 1: This embodiment introduces a high-performance chiplet packaging implementation method, including: Pre-process multiple chiplets, make TSVs in the chiplets, and deposit a layer of dielectric material on the surface of their metal layers; Pre-treating the substrate and depositing a layer of dielectric material on the side of the substrate with the pad; Bonding the pre-processed chiplet to the pre-processed substrate; then bonding another pre-processed chiplet to the bonded chiplet to form a chiplet module; Among them, the chiplets bonded together rely on TSV to form information exchange.

[0017] The high-performance chiplet packaging implementation method provided in this embodiment specifically involves the following steps in its application process: 1. Preprocessing. Figure 1 , Figure 2 As shown, the chiplet and substrate are surface treated to remove surface impurities. The surface of the chiplet is a copper pad and a silicon dioxide matrix; the surface of the substrate is a copper layer and an insulating layer (generally epoxy resin). Surface impurities can be removed by plasma cleaning. Impurities include metal oxides and organic pollutants such as photoresist films and outgassing products of epoxy resins; Make TSV (Through Silicon Via) in the chiplet and deposit a layer of dielectric material on the surface of its metal layer (Cu). Deposit a thin layer of dielectric material on the side of the substrate with the pad. The height of Cu needs to be slightly lower than the dielectric layer.

[0018] 2. Mixed bonding. Figure 3 , Figure 4 , Figure 5As shown, the chiplet is aligned with the substrate, and the chiplet is directly bonded after alignment. During the hybrid bonding process, the copper on the chiplet and substrate surface grows due to heat, and the chiplet and the chiplet are bonded together. To ensure the alignment accuracy, the distance between the chiplet and the substrate and between the chiplet and the chiplet can be kept within 50um during the alignment process before bonding.

[0019] 3. Add a heat sink cover. Figure 6 As shown in FIG. 1 , a heat sink cover is mounted on the chiplet surface to provide physical protection for the chiplet module after bonding and to help dissipate heat. The heat sink cover can be made of materials with high thermal conductivity such as copper or graphene.

[0020] 4. Ball planting and packaging are completed. Figure 7 As shown, solder balls are added to the pads on the other side of the substrate to facilitate the interconnection of the package with other components.

[0021] The beneficial effects of this embodiment are as follows: 1. Extremely high-density interconnection. Chiplet and chiplet are interconnected through TSV, which can achieve ultra-fine pitch chip interconnection. The pad diameter and pad spacing can be reduced to 10um, and the number of I / Os is increased under the same area.

[0022] 2. Reduce latency. Hybrid bonding technology is used between chiplets and between chiplets and substrates to reduce the resistance and parasitic inductance of the connection channel and reduce latency.

[0023] 3. Support heterogeneous integration. Different modules such as chiplet1 / chiplet2 / chiplet3 can flexibly adopt different process technologies. For example, the storage chiplet adopts 28nm process and the computing chiplet adopts 12nm process.

[0024] 4. Enhanced heat dissipation. When the chip performs high-density calculations, it generates a lot of heat, causing the chip temperature to rise significantly, and even affecting the chip performance. By attaching a heat dissipation cover to provide mechanical protection for the chip, it can enhance heat dissipation and thus improve chip performance. The top of the heat dissipation cover cavity is parallel to the substrate, and a certain slope is formed around it. While increasing the heat dissipation area, under the same load, the stress is more uniform, the stress concentration coefficient at the corner is smaller, and it is not easy to fail.

[0025] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A high-performance chiplet packaging implementation method, characterized in that: include: Pre-processing multiple chiplets, including making TSVs inside the chiplets and depositing a layer of dielectric material on the chiplet surface where metal is distributed; Pre-treating the substrate, including depositing a layer of dielectric material on a side of the substrate having a pad; Bonding the pre-processed chiplet to the pre-processed substrate; then bonding another pre-processed chiplet to the bonded chiplet to form a chiplet module; Among them, the chiplets bonded together rely on TSV to form information exchange.

2. The high-performance chiplet packaging implementation method according to claim 1, characterized in that: The method further comprises: treating the chiplet and the substrate surface to remove surface impurities.

3. The high-performance chiplet packaging implementation method according to claim 1, characterized in that: The height of the metal on the surface of the chip is lower than the height of the deposited dielectric material layer.

4. The high-performance chiplet packaging implementation method according to claim 1, characterized in that: During the alignment process before bonding, the distance between chiplet and substrate and between chiplets is kept within 50um.

5. The high-performance chiplet packaging implementation method according to claim 1, characterized in that: A plurality of TSVs are fabricated in the chiplet.

6. The high-performance chiplet packaging implementation method according to claim 1, characterized in that: The method further includes: mounting a heat dissipation cover on the surface of the chiplet module.

7. The high-performance chiplet packaging implementation method according to claim 6, characterized in that: The top of the heat dissipation cover cavity is parallel to the base plate, and a slope of a set angle is formed around it.

8. The high-performance chiplet packaging implementation method according to claim 6, characterized in that: The heat dissipation cover is made of copper or graphene.

9. The high-performance chiplet packaging implementation method according to claim 1, characterized in that: The method further includes: adding solder balls on a solder pad on a side of the substrate away from the chiplet, for interconnecting the chiplet module with other components.

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