Semiconductor circuit structure with direct die heat rejection structure

Abstract

The invention provides a semiconductor circuit structure with a direct die heat rejection structure. The semiconductor circuit structure includes a semiconductor substrate having an original semiconductor surface, a set of active regions in the semiconductor substrate, and a first shallow trench isolation region adjacent to the set of active regions and extending along a first direction. Wherein the first shallow trench isolation region comprises a heat removal layer, and the material of the heat removal layer is different from that of silicon dioxide.

Description

Technical Field

[0001] The invention relates to a semiconductor structure, and in particular to a semiconductor circuit structure with a direct die heat removal structure. Background Art

[0002] The single-chip integration capability of silicon chips has evolved from Giga Scale Integration (GSI): more than billions of transistors on a single chip (chip) to Tera Scale Integration (TSI): more than trillion transistors on a single chip (chip), and operating such a large number of transistors will lead to a sharp increase in power consumption. Limited by the limited heat dissipation capacity of existing technologies, the increased power consumption will adversely increase the junction temperature of the transistor, thereby increasing the temperature of the entire chip (chip). Since the thermal conductivity of silicon dioxide is very low, the thermal conductivity of silicon itself is not very high. This structural problem of materials and components will lead to a negative cyclic effect, that is, the increase in chip (chip) temperature will slow down the speed of the transistor. Then it is inevitable to enhance the design to increase the power of the circuit to accelerate the performance of the transistor, but this mechanism will cause the chip (chip) temperature to rise sharply, causing the heat dissipation problem to become more serious. This problem of insufficient heat dissipation leading to increased chip operating temperature is one of the most serious problems that the entire chip industry needs to solve urgently, and it is the main obstacle to be avoided when integrating more components into chips. However, progress in reducing the temperature of giant scale integrated circuit (GSI) chips has not improved as much as it should.

[0003] In fact, as the process technology node is further miniaturized, the size of transistors will inevitably become smaller (for example, the minimum feature size is reduced from 7nm to 5nm, and then to 3nm, etc.), and the percentage of oxide coverage in the total transistor size is also increasing, resulting in further concentration of heat dissipation through component junctions. Although the industry has created many heat dissipation methods, such as covering the entire chip with a higher heat dissipation pad outside the chip (granule), or using a liquid cooling cycle outside the packaged chip, these methods are very expensive, but the return efficiency of effectively reducing the junction temperature of the transistor is very low. Summary of the invention

[0004] The present invention focuses on a heat remover (HR) structure specifically created in the semiconductor die during the monolithic processes of manufacturing transistors. This heat remover structure is a bit like a connection to the die to make the whole a single piece to maximize the heat dissipation area. In addition, this heat remover structure can be connected to the overall edge of the die so that it can be more easily connected to some heat sink outside the semiconductor die, thereby creating a larger heat dissipation path for the die to connect to the external environment of the die and thus to the packaged chip. This new type of heat removal structure is considered to be the closest path that can be integrated with a single transistor to achieve a very effective heat dissipation function. Moreover, all of the multiple heat removal structures can be connected together and span the entire die as part of an optimized heat dissipation network built into the die.

[0005] An embodiment of the present invention provides a semiconductor circuit structure. The semiconductor circuit structure includes a semiconductor substrate having an original semiconductor surface (OSS), a group of active regions located in the semiconductor substrate, and a first shallow trench isolation region (STI) adjacent to the group of active regions and extending along a first direction. The first shallow trench isolation region includes a heat removal layer, and the material of the heat removal layer is different from silicon dioxide (SiO2).

[0006] According to one aspect of the present specification, the heat dissipation layer has a higher thermal conductivity than silicon dioxide.

[0007] According to one aspect of the present disclosure, the heat removal layer is an electrical insulator during operation of the semiconductor circuit structure.

[0008] According to one aspect of the present description, the heat removal layer extends into one of the set of active regions.

[0009] According to one aspect of the present specification, the heat dissipation layer includes a metal layer and an insulating thin layer, wherein the insulating thin layer is located between the metal layer and the group of active regions.

[0010] According to one aspect of the present disclosure, the heat removal layer includes a composite material.

[0011] According to one aspect of the present specification, the first shallow trench isolation region further includes a silicon dioxide layer located below the heat dissipation layer.

[0012] According to one aspect of the present disclosure, a heat removal layer is located in a front end of line (FEOL) region of a semiconductor circuit structure.

[0013] According to one aspect of the present specification, a first shallow trench isolation region surrounds the group of active regions.

[0014] According to one aspect of the present specification, the heat removal layer is located in the first shallow trench isolation region and below the original semiconductor surface, and the heat removal layer surrounds the group of active regions.

[0015] According to one aspect of the present specification, a spare STI region is further included, connected to the first STI region, and the heat dissipation layer extends along the first direction to the spare STI region.

[0016] According to one aspect of the present disclosure, the spare shallow trench isolation region is close to the center of the semiconductor substrate or close to the edge of the semiconductor substrate.

[0017] According to one aspect of the present specification, a heat dissipation pad is further included in the spare shallow trench isolation region, and the heat dissipation layer is connected to the heat dissipation pad.

[0018] According to one aspect of the present specification, a thermal via is located above the spare shallow trench isolation region and connected to a heat dissipation pad in the spare shallow trench isolation region.

[0019] According to one aspect of the present specification, a heat dissipation plate is located above the thermal via plug and connected to the thermal via plug.

[0020] According to one aspect of the present specification, a plurality of insulators are further included above the set of active regions, wherein the thermal via plug penetrates the plurality of insulators and is connected to the heat dissipation pad located in the spare shallow trench isolation region.

[0021] According to one aspect of the present disclosure, a plurality of insulators and thermal via plugs are located in a back end of line (BEOL) region of a semiconductor circuit structure.

[0022] According to one aspect of the present specification, a through semiconductor via (TSV) extends from the backside surface of the semiconductor substrate to the bottom surface of the heat dissipation pad located in the spare shallow trench isolation region, wherein the backside surface and the original semiconductor surface are located on opposite sides.

[0023] According to one aspect of the present specification, a heat sink is located below a backside surface of a semiconductor substrate and is connected to a semiconductor through via plug.

[0024] According to one aspect of the present specification, the first shallow trench isolation region surrounds four sidewalls of one of the set of active regions.

[0025] Another embodiment of the present invention provides a semiconductor circuit structure, including a semiconductor substrate having an original semiconductor surface, a group of transistors formed in the semiconductor substrate, and a composite shallow trench isolation region adjacent to the group of transistors and extending to an edge portion of the semiconductor substrate along a first direction, wherein the composite shallow trench isolation region is located in a front end of line (FEOL) region of the semiconductor circuit structure.

[0026] According to one aspect of the present disclosure, the composite shallow trench isolation region includes a heat row layer adjacent to the group of transistors and extending along a first direction to an edge portion of the semiconductor substrate.

[0027] According to one aspect of the present specification, a thermal via plug is disposed above or below the heat dissipation layer, wherein the thermal via plug is connected to the heat dissipation layer.

[0028] According to one aspect of the present disclosure, a heat sink is located above or below a semiconductor substrate, wherein the semiconductor substrate is connected to a thermal via plug.

[0029] According to one aspect of the present disclosure, a thermal via plug is located in a back-end processing region of a semiconductor circuit structure.

[0030] Another embodiment of the present invention provides a semiconductor circuit structure, including a semiconductor substrate having an original semiconductor surface, a first group of active regions located in the semiconductor substrate and extending along a first direction; a second group of active regions located in the semiconductor substrate and extending along the first direction, and a first shallow trench isolation region located between the first group of active regions and the second group of active regions, wherein the first shallow trench isolation region extends along the first direction; wherein the first shallow trench isolation region includes a heat removal layer extending along the first direction, and the thermal conductivity of the heat removal layer is higher than the thermal conductivity of silicon dioxide.

[0031] According to one aspect of the present specification, the semiconductor circuit structure also includes a spare shallow trench isolation region away from the first group of active regions and the second group of active regions, the spare shallow trench isolation region is connected to the first shallow trench isolation region, and includes a heat dissipation pad located in the spare shallow trench isolation region, wherein the heat dissipation layer is connected to the heat dissipation pad.

[0032] According to one aspect of the present specification, a width of the heat dissipation pad is greater than a width of the heat dissipation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein:

[0034] Figure 1a is a top view showing a structure of a conventional semiconductor circuit structure having a shallow trench isolation region and an active region; Figure 1b It is shown Figure 1aA top view of the structure in some areas; Figure 1c It is shown Figure 1a Schematic diagram of the structural section;

[0035] Figure 2 (including Figure 2a and Figure 2b ) are a top view and a cross-sectional schematic diagram respectively showing a process structure after forming an active area and a shallow trench isolation area;

[0036] Figure 3 (including Figure 3a and Figure 3b ) are a top view and a cross-sectional schematic diagram respectively showing a process structure after a nitride protection zone is formed above the center of the active region;

[0037] Figure 4 (including Figure 4a and Figure 4b ) are a top view and a cross-sectional schematic diagram respectively showing a process structure after forming a vertical spacer to cover the exposed silicon sidewall;

[0038] Figure 5 (including Figure 5a and Figure 5b ) are a top view and a cross-sectional schematic diagram respectively showing the process structure after the deeper silicon sidewall is exposed to the outside;

[0039] Figure 6 (including Figure 6a , Figure 6b and Figure 6c ) are schematic diagrams showing a top view of the process structure after forming a vacant tunnel region (vacant tunnel regions) and a schematic diagram of a structural cross section of two regions;

[0040] Figure 7 (including Figure 7a and Figure 7b ) are a top view and a cross-sectional schematic diagram respectively showing a process structure after depositing a high thermal dissipation material;

[0041] Figure 8 (including Figure 8a and Figure 8b ) are a top view and a cross-sectional schematic diagram respectively showing a process structure after forming a horizontal heat dissipation plate (Horizontal Heat-Dissipation Plate, HHDP) and a vertical heat dissipation column (Vertical Heat-Dissipation Column, VHDC);

[0042] Figure 9 (including Figure 9a and Figure 9b ) is a top view and a cross-sectional schematic diagram respectively showing a process structure after forming a horizontal heat dissipation plate and a vertical heat dissipation column according to another embodiment;

[0043] Fig.10is a schematic diagram showing the structure after the horizontal heat dissipation plate and the vertical heat dissipation column are connected and extended to the edge of the chip / die;

[0044] Fig.11 is a schematic diagram of a transistor cooling (Cool Transistor, CQT) structure according to the present invention;

[0045] Fig.12a and Figure 12b is a schematic cross-sectional view of a vertical heat dissipation column structure according to different embodiments of the present invention; Fig.12c According to another embodiment, Figure 12b A schematic diagram of the structure after the vertical heat dissipation column is extended to the edge of the chip / die;

[0046] Fig.13 is based on Figure 12b Another schematic diagram of a transistor cooling structure is shown;

[0047] Fig.14a is a top view of a semiconductor circuit structure according to some embodiments of this specification;

[0048] Fig.14b is a top view of a semiconductor circuit structure according to other embodiments of the present specification;

[0049] Fig.15a is a top view of a semiconductor circuit structure according to some embodiments of this specification; Figure 15b to Figure 15c It is shown in the production Fig.15a A top view of a semiconductor circuit structure in different stages of manufacturing process;

[0050] Figures 16a to 16f is a schematic cross-sectional view of different semiconductor circuit structures according to some embodiments of the present specification;

[0051] Fig.17a is a diagram showing the temperature distribution of a fin field effect transistor (FinFET) created by TCAD simulation software Sentaurus; and

[0052] Fig.17b is a graph showing the relationship between the temperature difference and the thickness of the shallow trench isolation region.

[0053] Reference numerals:

[0054] 101: pad silicon oxide thin layer

[0055] 102: first pad silicon nitride layer

[0056] 103: Active area

[0057] 201: Shallow trench isolation area

[0058] 301: second pad silicon nitride layer

[0059] 401: Silicon oxide thin layer

[0060] 403: third pad silicon nitride layer

[0061] 601: Hollow Tunnel Area

[0062] 701: Silicon oxide layer

[0063] 702:Z Material

[0064] 801: Silicon oxide

[0065] 1101: Gate metal region

[0066] 1102: High dielectric constant dielectric layer

[0067] 1103: Source region

[0068] 1104: drain region

[0069] 200:Semiconductor circuit structure

[0070] 205: Vertical heat dissipation column structure

[0071] 209: Vertical heat dissipation column structure

[0072] 214: Horizontal shallow trench isolation area

[0073] 214-1 to 214-4: Shallow Trench Isolation Area

[0074] 220A-1 Active Area

[0075] 220A: Active area

[0076] 220B: Shallow trench isolation area

[0077] 220C: Pad opening layer

[0078] 224: Large shallow trench isolation area

[0079] 224-1 to 224-4: Large Shallow Trench Isolation Area

[0080] 300:Semiconductor circuit structure

[0081] 314-1, 314-2, 314-3: Shallow trench isolation area

[0082] 305-1, 305-2, 305-3: Vertical heat dissipation column structure

[0083] 400:Semiconductor substrate

[0084] 400B: Back surface

[0085] 414: Shallow trench isolation area

[0086] 424: Large shallow trench isolation area

[0087] 431: Connecting plug

[0088] 440: Upper internal connection structure

[0089] 441: Contact structure

[0090] 442: Dielectric layer

[0091] 700:Semiconductor circuit structure

[0092] 733:Through Silicon Via Plug

[0093] 734: Heat dissipation film

[0094] 735: Barrier or isolation film

[0095] 737: Heat sink

[0096] 739: Top heat sink

[0097] 800:Semiconductor circuit structure

[0098] 833: Upper thermal via plug

[0099] 900:Semiconductor circuit structure

[0100] 934: Upper heat dissipation film

[0101] 12c: Tangent

[0102] 6b-6b': Tangent

[0103] 6c-6c': Tangent

[0104] OSS: Original Semiconductor Surface

[0105] t1: Depth

[0106] t2: Depth

[0107] t3: thickness

[0108] M1-M3: Metal layer

[0109] V1, V2: Connecting plugs

[0110] C1, C2: Chip DETAILED DESCRIPTION

[0111] Various embodiments will be described more fully below with reference to the accompanying drawings, wherein the drawings are only for illustration and explanation of the technical content and are not intended to limit the present invention. For the sake of clarity, the components in the drawings may not be drawn to scale. In addition, some components and / or component numbers may be omitted in some drawings. It is contemplated that the components and features of one embodiment may be incorporated into another embodiment without further description. In the following method for manufacturing a semiconductor component, one or more additional steps may exist between the steps described, and the order of these steps may be changed. The same / similar component numbers may be used in the various drawings to indicate the same / similar components.

[0112] Ordinal numbers used to describe components in the specification and the claims of the claimed invention, such as "first", "second", etc., do not imply or represent a specific position in the structure, or the order of arrangement, or the order of manufacture. Ordinal numbers are only used to clearly distinguish multiple components with the same name. As used in the specification and the claims of the attached claims, spatial relationship terms, such as "upper", "above", "above", "upper", "top", "lower", "below", "below", "lower", "bottom", etc., are only used to describe the relative spatial relationship or positional relationship between one or more components and another component in the drawings, and these spatial relationships or positional relationships, unless otherwise specified, may be direct or indirect. In addition to the directions depicted in the drawings, spatial relationship terms are intended to cover different directions of the structure. The structure can be inverted or rotated at various angles, and the descriptions of the various spatial relationships used in this specification can be interpreted accordingly.

[0113] In addition, the terms "electrically connected" and "electrically coupled" used in the specification and claims may refer to ohmic contact between components, or to the ability of current to flow through the components, or to an operational relationship between components. For example, the operational relationship may refer to one component driving another component, but current may not flow directly between the two components.

[0114] In a conventional semiconductor circuit structure, there are many transistors or circuit components located in active areas or active areas (AA) in a semiconductor substrate, and there are many shallow trench isolation regions surrounding the multiple active areas, such as Figure 1a Shown. Figure 1b It is shown Figure 1a A top view of the structure in some areas; Figure 1c It is shown Figure 1aSchematic diagram of the structural cross-section of a semiconductor device. Before manufacturing the transistor, the silicon island in the active area will be covered by an oxide layer and a nitride layer, and the multiple oxide layers and nitride layers are deposited above the original semiconductor surface of the semiconductor substrate. The depth of the shallow trench isolation region extending downward from the original semiconductor surface is usually 250 nanometers (nm) to 300 nanometers, and the material of the shallow trench isolation region is usually silicon dioxide, which has a very low thermal conductivity of 1.3 to 1.5 W / m×K. Therefore, the shallow trench isolation region may increase the die temperature and reduce the speed of the transistor. Worse, the shallow trench isolation region in the semiconductor substrate may occupy 40% or more of the total area of ​​the semiconductor substrate, and the multiple shallow trench isolation regions do not have any special function except for the isolation purpose.

[0115] The following is a description of how to manufacture a heat dissipation structure in a substrate or a tube core according to an embodiment of the present invention. Please refer to Figure 1. Please refer to Figure 2a and Figure 2b . First, a thin pad silicon oxide layer 101 is thermally grown on the top of the original semiconductor surface, and then a first pad silicon nitride layer (pad-nitride-1layer) 102 is deposited on the thin pad silicon oxide layer (thin pad-oxide layer) 101. Use photolithography and etching technology to define the active area 103, wherein the main body 1031 of the transistor or the fin structure is located below the composite layer composed of the first pad silicon nitride layer 102 and the pad silicon oxide thin layer 101. A concave trench area 104 connected to the inside of the tube core is formed on the outside of the active area 103 (its depth t1 is 250 nanometers to 300 nanometers calculated from the original semiconductor surface). Then a thick silicon oxide layer is deposited, and a shallow trench isolation area 201 is made by chemical-mechanical-polishing (CMP) technology so that its top surface is flush with the top surface of the first pad silicon nitride layer 102 (wherein the top surface top view and the structural cross-sectional schematic diagram are shown respectively as follows). Figure 2a and Figure 2b shown).

[0116] Please refer to Figure 3a and Figure 3b , depositing a second pad silicon nitride layer (pad-Nitride-2 layer) 301, and using photolithography mask technology, leaving a portion of the second pad silicon nitride layer 301 in the center of the active area 103. Figure 3a and Figure 3b are the top view and cross-sectional schematic diagrams showing the process structure. Figure 4a and Figure 4b ( Figure 4a and Figure 4b, which are top views and cross-sectional schematic diagrams respectively showing the process structure, to etch away a portion of the silicon oxide exposed to the outside in the shallow trench isolation region 201 to a depth t2 (for example, a depth t2 of 70 nanometers, or 100 nanometers to 150 nanometers); the second pad silicon nitride layer 301 and the silicon oxide in the shallow trench isolation region 201 below the second pad silicon nitride layer 301 are maintained unaffected. The silicon sidewalls below the original semiconductor surface are thereby exposed. A thin layer of silicon oxide 401 (for example, having a thickness of approximately 1.5 nanometers to 3 nanometers) is then grown on the multiple sidewalls using a thermal oxidation process. Then, a third pad silicon nitride layer (pad-nitride-3layer) 403 is deposited. The third pad silicon nitride layer 403 is etched using an anisotropic etching technique to serve as a spacer on the vertical sidewalls. Under proper intentional design, the second pad silicon nitride layer 301 still remains on the flat surface, but becomes thinner due to the anisotropic etching performed to form the spacers of the third pad silicon nitride layer 403 .

[0117] Please refer to Figure 5a and Figure 5b , Figure 5a and Figure 5b 2 are top views and cross-sectional schematic diagrams showing the process structure, respectively. Anisotropic etching technology is used to remove a portion of the silicon oxide layer exposed to the outside in the shallow trench isolation region 201. The etching thickness t3 is about 8 nanometers, thereby forming a flat silicon oxide surface. The distance from the top of the exposed silicon oxide surface to the original semiconductor surface is a distance (t2+t3) of about 78 nanometers. The exposed silicon oxide thin layer 401 is removed using anisotropic etching technology to expose the silicon on the sidewall.

[0118] Please refer to Figure 6a , Figure 6b and Figure 6c Figure 6c, where Figure 6a is a top view showing the process structure; Figure 6b It is along Figure 6a A schematic cross-sectional view of the structure shown by the tangent line 6b-6b'; Figure 6c It is along Figure 6a The schematic diagram of the cross-section of the structure shown by the cut line 6c-6c' in FIG. The isotropic etching technology is used to remove a portion of the exposed silicon surface. Preferably, the etching rate in the lattice arrangement direction (1,1,0) can be adjusted to be much faster than the etching rate in the lattice arrangement direction (1,0,0). Therefore, the exposed silicon layer can be removed to form a hollow tunnel region 601. The silicon removal process can be well controlled and can be adjusted to terminate at an appropriate time so that a vertical distance of silicon is protected by the spacer of the third pad silicon nitride layer 403.

[0119] It is worth noting that different processes can be used to accomplish similar Figure 6a , Figure 6b and Figure 6c For example, in the formation of Figure 5a and Figure 5b After the structure shown, the aforementioned anisotropic etching technique may not be used to remove a portion of the exposed silicon surface, but a thermal oxidation process may be used to grow silicon oxide to replace the exposed silicon area. Since the horizontal distance of the exposed silicon area may be narrow, the silicon oxide layer (e.g., thermal silicon oxide) grown below the top surface of the silicon island can quickly fill the horizontal gap and have a good smooth close-up shape, while the silicon bulk material covered by the third pad silicon nitride layer 403 can be well protected as a strong pillar to connect the semiconductor body region of the transistor to the wafer substrate region without being over-oxidized. Then, the thermal silicon oxide is removed using an anisotropic etching technique to produce a structure similar to Figure 6a , Figure 6b and Figure 6c The structure shown.

[0120] Please refer to Figure 7a and Figure 7b , use isotropic etching technology to remove the spacer of the third pad silicon nitride layer 403. A very thin (for example, 1 nanometer to 3 nanometers) silicon oxide layer 701 is grown by thermal oxidation process to well protect the newly formed and exposed silicon surface. Then select a suitable material with very high thermal conductivity (for example, boron nitride (BN), which is an electrical insulator but has a very high thermal conductivity, such as 600W / m×K, while the thermal conductivity of silicon material is 149W / m×K; aluminum nitride (AlN), a material with a thermal conductivity of up to 321W / m×K; or any other material with an appropriate thermal conductivity, any of which can be referred to as Z material 702). Then use a chemical vapor deposition (CVD) process, such as selecting boron nitride (BN), to fill the hollow tunnel area 601 formed by the previous process. Of course, the gap inside the shallow trench isolation area is also filled with boron nitride (BN) material ( Figure 7a and Figure 7b 2 are a top view and a cross-sectional schematic diagram showing the process structure respectively).

[0121] In another embodiment, the thermal conductivity of Z material 702 is higher than that of silicon, or higher than that of silicon nitride, or higher than 10 W / mK or 30 W / mK. Of course, other materials that may be used as Z material 702 may be graphene or metal (such as copper, tungsten or composite metal, etc.). And preferably, a titanium nitride (TiN) barrier layer or other suitable material layer is covered on the tungsten layer. When the material of Z material 702 is metal, there may be a thin layer of insulator between the active area and Z material 702, such as a thermal silicon oxide layer. In addition, the material of Z material 702 may be a composite material layer composed of two or more of the above materials. Obviously, Z material 702 is different from the original material (silicon dioxide) of the shallow trench isolation region. In another embodiment, Z material 702 is also different from silicon nitride. Z material 702 may include a material with a higher thermal conductivity than the original material (such as silicon oxide) of the shallow trench isolation region, such as aluminum nitride, boron nitride, silicon carbide (SiC), silicon (Si), deposited diamond or silicon germanium (SiGe), etc.

[0122] Afterwards, the boron nitride material or Z material 702 located above the first pad silicon nitride layer 102 can be removed using chemical mechanical polishing technology to form a flat surface, and further anisotropic etching technology can be used to remove a portion of the boron nitride material or Z material 702 so that the top of the Z material 702 is aligned with the original semiconductor surface, or lower than the original semiconductor surface. Next, a layer of silicon oxide 801 is deposited on top of the remaining Z material 702 until it is flush with the top surface of the first pad silicon nitride layer 102. After removing the second pad silicon nitride layer 301, the silicon surface will be covered by the silicon oxide above the first pad silicon nitride layer 102 and the shallow trench isolation region, and familiar processes can be performed in the remaining semiconductor active area to complete the preparation of transistors (for example, planar transistors, fin field effect transistors, or gate-all-around (GAA) transistors, etc.) (see Figure 8, where Figure 8a and Figure 8b 2 are a top view and a cross-sectional schematic diagram showing the process structure respectively).

[0123] Since the boron nitride material or Z material 702 is filled in the hollow tunnel area below the active area (or fin field effect transistor / tri-gate device), it can be called a horizontal heat sink. As shown in Figure 8, some Z materials 702 filled in the vertical gaps in the shallow trench isolation area can be called vertical heat sinks. After forming the transistor in the active area, the source / drain area of ​​the transistor can be positioned close to the horizontal heat sink and vertical heat sink having a higher thermal conductivity than the silicon dioxide (or silicon) material surrounding the transistor in the traditional design. In fact, the hottest areas of the transistor when it is fully operational are concentrated in the p / n junction area between the drain area and the source area connected to the transistor channel area. The multiple horizontal heat sinks and vertical heat sink structures can very effectively disperse the heat energy generated by the multiple p / n junction areas.

[0124] Another possibility is to use a similar method as described above to create a horizontal heat sink structure that is deeper from the original silicon surface, and to add more horizontal heat sinks to expand the heat dissipation area. For example, after the deposition of the boron nitride material or Z material 702 is completed by a chemical vapor deposition process, an anisotropic etching technique can be used to remove the boron nitride material or Z material 702 vertically located inside the shallow trench isolation region 201. Then, an anisotropic etching technique can also be used to remove or etch away the silicon oxide material at the bottom of the shallow trench isolation region 201 (for example, only 20 nanometers to 50 nanometers thick silicon oxide is retained inside the shallow trench isolation region 201 without damaging the boron nitride material that has been horizontally inserted into the hollow tunnel region 601). Then, the boron nitride material or Z material 702 is deposited into the gap in the shallow trench isolation region 21 for a second time. The two-step process of forming the boron nitride material or Z material 702, the first step is used to form a horizontal heat sink, and then the second step is used to optimize the volume of all the boron nitride or Z material 702 inside the shallow trench isolation region 21 (see Figure 9, where Figure 9a and Figure 9b ) Of course, before the second deposition of the Z material 702, an additional step may be applied to form a thin vertical isolation layer (e.g., a silicon oxide thin layer 401), so that the vertical isolation layer is located below the horizontal heat sink and between the sidewall of the silicon substrate and the Z material 702.

[0125] It is also worth noting that Figure 1aAs shown, the shallow trench isolation region is distributed throughout the entire wafer substrate. Since the horizontal heat sink material is all located below the body region (or active region) of the metal oxide semiconductor field effect transistor (MOSFET) / transistor and is connected to all vertical heat sink materials inside the shallow trench isolation region, the high heat dissipation material network constructed can serve as a heat sink (heat-dissipation sink) connected to the working P / N junction of the transistor. By designing the Z material in a single chip (monolithic die) and utilizing familiar single chip (die) process parameters (recipes), all Z materials can be connected to the edge ring of the chip or tube core. Moreover, the Z material 702 located in the shallow trench isolation region can form a contact by opening its top surface, so that the Z material 702 of the entire tube core can be thermally connected to the outer edge of the chip / tube core for more direct and efficient heat dissipation. See Fig.10 , respectively showing a top view and a cross-sectional schematic diagram of the process structure. Therefore, the horizontal heat sink in the shallow trench isolation region (and / or the horizontal heat sink in the active region) can be called a direct die heat remover (DDHR). The present invention provides a direct die cooling technology (DDCT) based on the vertical heat sink (and / or horizontal heat sink).

[0126] There are multiple active areas in the semiconductor substrate. In the present invention, the active area (or multiple active areas) can be surrounded by Z material 702. Z material 702 extends from one active area to another active area, and further extends to the edge of the chip / die. Each active area can accommodate a circuit component, such as a transistor. In another embodiment, the chip / die with vertical heat dissipation columns (and / or horizontal heat dissipation plates) can be thinned first, and then the vertical heat dissipation columns (and / or horizontal heat dissipation plates) are exposed through openings, so that another substrate with thermal vias or heat sinks can be connected to the vertical heat dissipation columns (and / or horizontal heat dissipation plates) from the bottom of the chip / die.

[0127] After the structure of the vertical heat sink (and / or horizontal heat sink) is completed by a part of the front-end process, the transistors can be formed in the active area by the remaining front-end foundry process, such as Fig.11 As shown. The diffusion region (or source / drain region) of the transistor may be in contact with or nearly in contact with the vertical heat sink (and / or horizontal heat sink). Therefore, it can be said that the vertical heat sink (and / or horizontal heat sink) is formed during the semiconductor front-end foundry process, or is formed within the front-end process area of ​​the semiconductor die.

[0128] exist Fig.11In the embodiment, the transistor includes a gate structure, which includes a gate metal region 1101 and a high dielectric constant (Hi-K) dielectric layer 1102. The transistor also includes a source region 1103, which includes a lightly doped region extending laterally from the sidewall of the substrate and a heavily doped region extending laterally from the sidewall of the lightly doped region. The multiple lightly doped regions and heavily doped regions are formed by selective growth methods (e.g., epitaxial growth methods). Above the top of the source region 1104. There is a metal contact 1105 between the gate structure of the transistor and the shallow trench isolation region (the silicon oxide 801 above). It is worth noting that the top surface of the shallow trench isolation region (the silicon oxide 801 above) is higher than the original semiconductor surface (e.g., flush with the top of the gate structure), so a contact hole is automatically formed, and there is no need to use a photolithography process to form the contact hole. Therefore, the metal contact 1105 is self-aligned with the source region 1103. In addition, in another embodiment, the metal contact 1105 may be connected not only to the top of the source region 1103 but also to the most lateral sidewall of the source region 1103. The transistor also includes a drain region 1104, and since its structure is the same or substantially the same as that of the source region 1103, it will not be described in detail here. Fig.11 The final transistor structure shown has a microstructure of vertical heat sinks (and / or horizontal heat sinks) to create a new "transistor cooling (CQT)" structure, which is the best term to describe embodiments of the present invention. This transistor cooling (CQT) structure can realize the performance scaling (more transistors) and size reduction (smaller transistor size) strategies from the current giant scale integrated circuit (GSI) era to the near future terascale integrated circuit (TSI) era. The new heat dissipation path created for the chip or die is to form a heat dissipation path directly from the transistor level to the entire die level. There are some designs that can connect the heat dissipation path of the die level to the chip level (chip-level thermal path) thermal path. Under the current cooling methods used for chips and packages / heterogeneous integration modules, it can certainly serve as an effective heat dissipation device for chips and packages / heterogeneous integration modules (for example, through silicon via plugs (TSV) or through insulator vias (TIV), etc.).

[0129] In addition, in another embodiment, the process of forming the horizontal heat sink can be omitted, and only the vertical heat sink column can be constructed. For example, referring to FIG. 12 , the shallow trench isolation region 201 can be etched downward to expose the sidewall of the silicon substrate to the outside, so that the depth of the remaining material in the shallow trench isolation region is about 150 nanometers to 200 nanometers, and then a silicon oxide (thermal silicon oxide) thin layer 401 is formed along the sidewall of the silicon substrate exposed to the outside. Then, the Z material 702 is deposited and etched back to a depth of 100 nanometers to 150 nanometers to form a vertical heat sink column, and additional silicon oxide 801 or other isolation materials are deposited on the vertical heat sink column, such as Fig.12a Shown.

[0130] Figure 12b FIG. 4 is a schematic cross-sectional view of a structure of a vertical heat dissipation column located in a shallow trench isolation region according to another embodiment of the present invention. Fig.12a and Figure 12b The difference is that most of the silicon dioxide material in the shallow trench isolation area is replaced by vertical heat sinks. The depth of the traditional shallow trench isolation area is 250 nanometers to 300 nanometers from the original semiconductor surface (OSS) of the chip. Figure 12b In the embodiment, only silicon dioxide material with a depth of 20 nanometers to 50 nanometers remains in the lower part of the shallow trench isolation region; Fig.12a The silicon dioxide material with a depth of 150 nanometers to 200 nanometers remains in the lower part of the shallow trench isolation region shown. The more silicon dioxide is replaced by the vertical heat dissipation pillars, the higher the thermal conductivity of the tube core structure. Of course, the top of the vertical heat dissipation pillars can be lower or higher than the original semiconductor surface. Similarly, Fig.12a or Figure 12b The vertical heat sink structure shown can also extend along all shallow trench isolation regions within the semiconductor die, such as Fig.12c As shown. Among them, Fig.12c The sub-figure below is along the Fig.12c The schematic cross-sectional view of the structure is shown by the tangent line 12c in the upper sub-figure.

[0131] Fig.13 is a schematic diagram showing another transistor cooling structure, Fig.13 and Fig.11 The difference is that Fig.13 The transistor cooling structure is based on Figure 12b The vertical heat sink pillars are shown in the shallow trench isolation region. Fig.13 Other descriptions of the transistor cooling structure shown are similar to Fig.11 The transistor cooling structure shown is the same, and the detailed description thereof is skipped for the sake of brevity.

[0132] As mentioned above, the vertical heat dissipation column or Z material can be made of a single high heat dissipation material or a composite structure. For example, the vertical heat dissipation column includes a layer of a first high heat dissipation material (for example, boron nitride, aluminum nitride, etc., not in Fig.12a or Figure 12b ) and another metal or metalloid column covered by the first high heat dissipation material. Since the vertical heat dissipation column is located in the shallow trench isolation region and the metalloid material is surrounded by the first high heat dissipation material, the material will not conduct electricity during the operation of the transistor in the chip / die (in this case, the silicon oxide thin layer 401 can be omitted), so the metalloid material in the vertical heat dissipation column will not affect the operation of the transistor in the chip / die. Of course, the first high heat dissipation material and the metal or metalloid column can be further extended to the edge of the chip / die and form a heat dissipation network as described above. Therefore, there is a composite shallow trench isolation region (including the original shallow trench isolation region silicon dioxide material and the vertical heat dissipation column; only including the vertical heat dissipation column, which can be a composite material with two different layers) or a heterogeneous shallow trench isolation region (Heterogeneous STI, HSTI) in the semiconductor structure of the present invention.

[0133] Furthermore, in one embodiment, Figure 1a All or most of the shallow trench isolation regions in the composite material can be replaced by shallow trench isolation regions of the composite material. The shallow trench isolation regions of the composite material can extend from one active area to another active area and further extend to the edge of the chip / die. In another embodiment, the peripheral border of the first group of active areas is surrounded by the shallow trench isolation regions of the composite material and extends to the second group of active areas and further extends to the edge of the chip / die.

[0134] Fig.14a FIG. 2 is a top view of a semiconductor circuit structure 200 according to some embodiments of the present specification. The semiconductor circuit structure 200 may be formed in a semiconductor chip or a substrate. Fig.14aMore active areas or active areas 220A, shallow trench isolation areas 220B, and pad open layers 220C that can accommodate contact pads of semiconductor circuit structure 200 are shown. Some large shallow trench isolation areas 224-1 to 224-4 in shallow trench isolation areas 220B can be located in corner areas adjacent to the peripheral / edge area of ​​the semiconductor chip, or in the center spare area of ​​the chip. Large vertical heat dissipation column structures (e.g., vertical heat dissipation column pads) 209 are located inside large shallow trench isolation areas 224-1 to 224-4 and below the original semiconductor surface of the semiconductor substrate. In addition, other thin or long vertical heat dissipation column structures (e.g., vertical heat dissipation column lines) 205 are located below the original semiconductor surface of the semiconductor substrate and are formed inside those thin or long shallow trench isolation areas 224-1 to 224-4 in shallow trench isolation areas 220B. The vertical heat dissipation column structure 205 and the shallow trench isolation regions 214-1 to 214-4 may extend along the X-axis direction (or along the long axis direction of the active region). In addition, the vertical heat dissipation column structure 205 may extend over two or more active regions 220A, for example, Fig.14a The upper right vertical heat sink structure 205 extends from a predetermined point adjacent to the active area 220A- 1 to the large shallow trench isolation region 224 - 1 .

[0135] exist Fig.14a In the embodiment, on one side of the shallow trench isolation region 214-1, there is a first group of active regions extending along the X-axis direction; on the other side of the shallow trench isolation region 214-1, there is a second group of active regions extending along the X-axis direction. Therefore, the shallow trench isolation region 214-1 is located between the first group of active regions and the second group of active regions, and extends along the X-axis direction. In addition, the vertical heat dissipation column structure 205 inside the shallow trench isolation region 214-1 is also located between the first group of active regions and the second group of active regions, and extends along the X-axis direction. In one embodiment, the minimum width and / or the maximum width (for example, along the Y-axis direction) of the vertical heat dissipation column structure 205 located between the first group of active regions and the second group of active regions is less than the width of the vertical heat dissipation column structure 209 (for example, along the Y-direction) connected to the straight heat dissipation column structure 205.

[0136] Furthermore, each of the shallow trench isolation regions 214 - 1 to 214 - 4 may be adjacent to a group of transistors in the plurality of active regions 220A, and the large shallow trench isolation region 214 - 1 is away from the group of transistors. The vertical heat dissipation pillar structure 205 is coupled to or directly connected to the vertical heat dissipation pillar structure 209 .

[0137] The width of the vertical heat dissipation column structure 209 along the Y-axis direction is greater than the width of the vertical heat dissipation column structure 205 along the Y-axis direction. The width of the vertical heat dissipation column structure 209 along the Y-axis direction may be between about 2 micrometers (μm) and 8 micrometers. The width of the vertical heat dissipation column structure 205 along the Y-axis direction may be between about 10 nanometers and 100 nanometers. The area of ​​the vertical heat dissipation column structure 209 may be between about 4 square micrometers (μm 2 ) to about 50 square microns. The materials of the vertical heat dissipation column structures 205 and 209 can be the same or different.

[0138] The spare or large STI region 224 may form extra alignment marks for backside through silicon vias (TSVs) or thermal vias extending from the bottom of the large STI region 224 to the bottom side of the substrate, such as Fig.14b As shown. The multiple back-side through silicon via plugs (TSV) or thermal via plugs are located directly below the large-sized vertical heat dissipation column pads inside the large shallow trench isolation area 224 and are connected to the large-sized vertical heat dissipation column pads. The area of ​​the spare or large shallow trench isolation area 224 is large enough to accommodate one or more through silicon via plugs (TSV) or thermal via plugs. Of course, those spare or large shallow trench isolation areas 224 can also form additional alignment marks for through silicon via plugs (TSV) or thermal via plugs extending from the top of the large shallow trench isolation area 22 to the top side of the substrate top side. The multiple thermal via plugs are located directly above the large-sized vertical heat dissipation column pads in the spare shallow trench isolation area and are connected to the large-sized vertical heat dissipation column pads. The through silicon via plug (TSV) or thermal via plug of the present invention can be manufactured by a back-end process foundry and connected to the large-sized vertical heat dissipation column pads. Therefore, it can be said that through silicon vias (TSVs) or thermal vias are formed during back end foundry manufacturing, or in a back end process area of ​​a semiconductor die.

[0139] In other embodiments, the vertical heat dissipation column structure may extend along a direction other than the X-axis, such as Fig.15a Shown. Fig.15a is a top view of a semiconductor circuit structure 300 according to some embodiments of this specification. Fig.14a Compared with the semiconductor circuit structure 200 shown, Fig.15aThe semiconductor circuit structure 300 shown further includes shallow trench isolation regions 314-1, 314-2 and 314-3 extending along the Y-axis direction and vertical heat dissipation column structures 305-1, 305-2 and 305-3. The vertical heat dissipation column structures 305-1, 305-2 and 305-3 are located below the original semiconductor surface of the semiconductor substrate and are formed inside the shallow trench isolation regions 314-1, 314-2 and 314-3, respectively. The vertical heat dissipation column structures 305-1, 305-2 and 305-3 can be vertical heat dissipation column lines. The vertical heat dissipation column structures 305-1, 305-2 and 305-3 and the shallow trench isolation regions 314-1, 314-2 and 314-3 can extend along the Y-axis direction (or along the width direction of the active area). In addition, the vertical heat dissipation column structures 305-1, 305-2 and 305-3 can extend above two or more active areas 220A. 15 extends from a predetermined point adjacent to the active area 220A-2 to the horizontal shallow trench isolation region 214. Each of the shallow trench isolation regions 314-1, 314-2 and 314-3 may be adjacent to a group of transistors located in the active area 220A.

[0140] exist Fig.15a In the embodiment, the vertical heat dissipation column structure extending along the non-X-axis direction can be connected to (or electrically coupled to) the vertical heat dissipation column structure extending along the X-axis direction and / or the vertical heat dissipation column pad located in the large shallow trench isolation area. For example, the vertical heat dissipation column structure 305-1 is connected to (or electrically coupled to) the vertical heat dissipation column structure 205; the vertical heat dissipation column structure 305-2 is connected to (or electrically coupled to) two vertical heat dissipation column structures 205 and is located between the two vertical heat dissipation column structures 205; the vertical heat dissipation column structure 305-3 is connected to (or electrically coupled to) the vertical heat dissipation column pad 209 located in the large shallow trench isolation area 224. The size and material of the vertical heat dissipation column structures 305-1, 305-2 and 305-3 can be similar to those of the vertical heat dissipation column structure 205.

[0141] Through the arrangement of vertical heat dissipation column structures / lines extending along the X-axis direction, vertical heat dissipation column structures / lines extending along the Y-axis direction (or directions other than the X-axis direction), and vertical heat dissipation column pads located in large shallow trench isolation areas, a vertical heat dissipation column grid (VHDCmesh) (or "Direct Die Cooling Technology") can be provided inside the tube core or semiconductor substrate and below the original semiconductor surface of the semiconductor substrate. The vertical heat dissipation column structures extending along the X-axis direction (i.e., horizontal vertical heat dissipation column lines) can be used to connect the vertical heat dissipation column structures (i.e., vertical heat dissipation column pads) located in the large shallow trench isolation area; and the vertical heat dissipation column structures extending along the Y-axis direction (i.e., vertical vertical heat dissipation column lines) can be used to connect vertical heat dissipation column pads or horizontal vertical heat dissipation column lines.

[0142] In some embodiments, the vertical heat dissipation column structure extending along the non-X-axis direction, such as Fig.15a The vertical heat dissipation column structures 305 - 1 , 305 - 2 and 305 - 3 shown in FIG. 1 can be manufactured through the following steps. Figure 15b to Figure 15c It is shown in the production Fig.15a The process structure top view of the semiconductor circuit structure 300 at different stages is shown. A pad silicon oxide layer (not shown) and a pad silicon nitride layer 3206 are sequentially deposited on the semiconductor substrate. Then, a temporary active area is first defined by a photolithography and etching process, and a temporary shallow trench isolation area and a large shallow trench isolation area (such as Fig.15b Then, Z material is formed in the temporary shallow trench isolation region and the large shallow trench isolation region. Then, the real active region 150A can be defined by another photolithography and etching process, and the removed temporary active region is used as the remaining shallow trench isolation region, such as Fig.15c As shown in .

[0143] The location, size, and number of the vertical heat dissipation column structures are not based on Figures 14 and Fig.15aThe content shown is limited. As described above, for heat dissipation applications, the vertical heat dissipation column structure may include (or may be made of) high thermal conductivity materials, such as tungsten (having a thermal conductivity of about 170W / mK), boron nitride (having a thermal conductivity of about 600W / mK), and aluminum nitride (having a thermal conductivity of about 321W / mK). Other materials with higher thermal conductivity than the original material (silicon dioxide) of the shallow trench isolation region may also be used, such as silicon carbide, silicon germanium, undoped silicon, or deposited diamond. In some embodiments, the vertical heat dissipation column structure may include (or may be made of) a composite material, which includes two or more high thermal conductivity materials. The present invention can utilize a vertical heat dissipation column structure to replace part of the silicon dioxide in the original shallow trench isolation region. Since the thermal conductivity of the material of the vertical heat dissipation column structure is higher than that of silicon dioxide and / or silicon, the heat dissipation capacity can be improved.

[0144] like Fig.15a As shown, the vertical heat dissipation column structure for heat dissipation can extend from some shallow trench isolation areas next to the active area where the transistor is located to the large shallow trench isolation area where the vertical heat dissipation column pad is located (for example, the area of ​​the vertical heat dissipation column pad can be between about 4 square microns and 50 square microns). In another embodiment, all the vertical heat dissipation column structures can be thermally coupled together. For example, the vertical heat dissipation column structure located in the large shallow trench isolation area (i.e., the vertical heat dissipation column pad) can be thermally coupled to the vertical heat dissipation column structure located in the shallow trench isolation area (i.e., the vertical heat dissipation column line). In addition, the large shallow trench isolation area can be used to align with one or more thermal via plugs, such as Fig.14b In addition, all or most (eg, more than 60%, or even 70% to 90%) of the shallow trench isolation region in the semiconductor chip can be filled with the vertical heat dissipation column structure provided by the present invention to achieve the purpose of heat dissipation.

[0145] Fig.16ais a cross-sectional schematic diagram of a semiconductor circuit structure 700 according to some embodiments of the present specification. The semiconductor circuit structure 700 includes an upper interconnect structure 440 located above a semiconductor substrate 400. The upper interconnect structure 440 includes a contact structure 441, metal layers M1 to M3, connecting vias V1 and V2, and a dielectric layer (or a set of insulating layers) 442. The contact structure 441, the metal layers M1 to M3, the connecting vias V1 and V2 are located in a dielectric layer 442 that may include a plurality of sub-dielectric layers. The contact structure 441 is located between the transistor TS and the metal layer M1. The metal layers M1 to M3 are sequentially located above the original semiconductor surface of the semiconductor substrate 400 along the Z-axis direction. The metal layers M1 to M3 are vertically separated from each other. The connecting vias V1 and V2 are located above the original semiconductor surface of the semiconductor substrate 400. The connecting via V1 is located between the metal layers M1 and M2. The connecting via V2 is located between the metal layers M2 and M3. The metal layers M1 to M3 and the connection plugs V1 and V2 are electrically connected to each other.

[0146] The semiconductor circuit structure 700 further includes a backside through silicon via plug (TSV) 733, which is located in the second vertical heat dissipation column structure 209 (i.e., including the second vertical heat dissipation column structure 209) in the large shallow trench isolation region 424. Fig.16a The second vertical heat dissipation column structure 209 is directly below the vertical heat dissipation column pad of the composite layer shown in the figure, and is connected to the second vertical heat dissipation column structure 209; it includes a heat dissipation film 734 located on the side wall of the through silicon via plug (TSV) 733, a barrier or isolation film 735 located on the side wall of the heat dissipation film 734, a heat dissipation plate 737 located at or near the back surface 400B of the semiconductor substrate 400 (or the back side of the chip), and a top heat dissipation plate 739 located above the upper interconnect structure 440. The through silicon via plug (TSV) 733 is used for heat dissipation and can be understood as a (back) thermal via plug. The heat dissipation plate 737 can be a heat sink, and its material can be the same as that of the heat dissipation film 734 or the through silicon via plug (TSV) 733. The through silicon via plug (TSV) 733 extends from the bottom surface of the second vertical heat dissipation column structure 209 to the back surface 400B of the semiconductor substrate 400. A through silicon via (TSV) 733 is connected between the second vertical heat dissipation column structure 209 and the heat dissipation plate 737 to form a heat dissipation path including the second vertical heat dissipation column structure 209 , the through silicon via (TSV) 733 and the heat dissipation plate 737 .

[0147] In order to dissipate heat, the vertical heat dissipation column structure in this embodiment may include a material having a thermal conductivity higher than that of silicon dioxide (or may be made of a material having a thermal conductivity higher than that of silicon dioxide). For example, the vertical heat dissipation column structure may include tungsten, copper, boron nitride, aluminum nitride, silicon carbide, silicon germanium, or deposited diamond, undoped silicon, or any combination of the above materials. In some embodiments, the vertical heat dissipation column structure includes an isolation material having a thermal conductivity higher than that of silicon. The through silicon via plug (TSV) 733 may include copper, and the heat dissipation film 734 may be boron nitride or aluminum nitride.

[0148] In addition, the through silicon via plug (TSV) 733 is directly connected to the second vertical heat dissipation column structure 209, and then the second vertical heat dissipation column structure 209 is connected to the first vertical heat dissipation column structure 205 (i.e., including the first vertical heat dissipation column structure 205) located in the shallow trench isolation region 414. Fig.16a The first vertical heat sink structure 205 can also be connected to the transistor (e.g., the source / drain region of the transistor) through the corresponding connection plug 431. In this way, the heat generated by the transistor can be dissipated to the through-silicon via plug (TSV) 733 through the connection plug 431, the first vertical heat sink structure 205 and the second vertical heat sink structure 209, thereby providing a vertical heat sink heat dissipation network with high heat dissipation efficiency. In another embodiment, the vertical heat sink structure can be isolated from the transistor, but the heat dissipation purpose can be achieved through the vertical heat sink line, the vertical heat sink pad and the through-silicon via plug (TSV) 733.

[0149] The vertical heat dissipation column structure 205 located inside and extending along the shallow trench isolation region 414 can be connected to the source terminal or drain terminal of the transistor through the connection plug 431 located in the active region of the transistor by a self-aligned or self-constructed method. The connection plug 431 is connected to the sidewall of the vertical heat dissipation column structure.

[0150] The conventional semiconductor circuit structure only includes the upper thermal via plug in the upper interconnect structure 440, and does not include a vertical heat dissipation column structure, especially does not include a vertical heat dissipation column pad. Therefore, the alignment of the upper thermal via plug is a key issue. In addition, the upper thermal via plug of the conventional semiconductor circuit structure is only located inside the dielectric layer 442 of the upper interconnect structure 440, and is isolated by the dielectric layer 442 of the upper interconnect structure 440, and the plurality of upper thermal via plugs are far away from the transistor. Therefore, the heat generated by the transistor is difficult to dissipate effectively. The semiconductor circuit structure provided in this specification can provide a larger alignment window for the thermal via plug with the help of the vertical heat dissipation column pad. In addition, by means of the vertical heat dissipation column structure, the thermal coupling path between the thermal via plug and the source / drain end of the transistor is shortened. Therefore, the heat generated from the transistor can be effectively dissipated by the configuration of this specification.

[0151] Fig.16b 8 is a cross-sectional schematic diagram of a semiconductor circuit structure 800 according to some embodiments of the present specification. The semiconductor circuit structure 800 includes an upper or top-side thermal via plug 833 located inside the dielectric layer 442 of the upper interconnect structure 440. The upper thermal via plug 833 extends upward from the upper surface of the second vertical heat dissipation column structure 209 to the top heat dissipation plate 739 and penetrates the dielectric layer 442 of the upper interconnect structure 440.

[0152] Therefore, the upper thermal via plug 833 is connected to the second vertical heat dissipation column structure 209 (i.e., the vertical heat dissipation column pad located in the shallow trench isolation area 424), and then the second vertical heat dissipation column structure 209 is connected to the first vertical heat dissipation column structure 205 (i.e., the vertical heat dissipation column line located in the shallow trench isolation area 414). The first vertical heat dissipation column structure 205 is connected to the transistor (e.g., the source / drain region of the transistor) through the corresponding connection plug 431. Therefore, the top heat sink 739, the upper thermal via plug 833, the first vertical heat dissipation column structure 205 and the second vertical heat dissipation column structure 209 can form a heat dissipation path to dissipate the heat generated by the transistor. In this way, the heat generated by the transistor can be dissipated to the upper thermal via plug 833 through the connection plug 431, the first vertical heat dissipation column structure 205 and the second vertical heat dissipation column structure 209. According to the direct thermal cooling technology provided in this specification, a vertical heat dissipation column heat dissipation network with high heat dissipation efficiency is provided. In another embodiment, even if the vertical heat dissipation column structure 205 (i.e., the vertical heat dissipation column line located in the shallow trench isolation region 414) is isolated from the transistor, the purpose of heat dissipation can still be achieved. In other embodiments, the upper thermal via plug 833 can extend from the upper surface of the upper interconnect structure 440 to the first vertical heat dissipation column structure 205. Further, the material constituting the upper thermal via plug 833 can be a Z material with a higher thermal conductivity than silicon or silicon dioxide, for example, copper. The material constituting the upper thermal via plug 833 can be the same as or different from the material constituting the top heat sink 739.

[0153] Fig.16c is a cross-sectional schematic diagram of a semiconductor circuit structure 900 according to some embodiments of the present specification. Fig.16c The semiconductor circuit structure 900 is shown with Fig.16b The difference of the semiconductor circuit structure 800 shown is that the semiconductor circuit structure 900 includes an upper heat dissipation film 934 located on the sidewall of the upper thermal via plug 833. The upper heat dissipation film 934 may include a material having a higher thermal conductivity than the Z material of silicon or silicon dioxide, such as boron nitride or aluminum nitride (or may be made of such a material). Providing the upper heat dissipation film 934 on the upper thermal via plug 833 may improve the heat dissipation efficiency.

[0154] In some embodiments, Fig.16a The through silicon via (TSV) 733 is shown with Fig.16b The upper thermal via plug 833 (or Fig.16c The upper heat dissipation film 934 and the upper thermal via plug 833 shown can be combined together, such as Fig.16dAs shown. Some upper thermal via plugs 833 extend from the upper surface of the upper interconnect structure 440 to the second vertical heat dissipation column structure 209 and are connected to the top heat dissipation plate 739. Through silicon via plugs (TSV) 733 (additional thermal via plugs) extend from the back side surface 400B of the semiconductor substrate 400 to the second vertical heat dissipation column structure 209 (or other vertical heat dissipation column structures) and are connected to the heat dissipation plate 737 located above or near the back side surface 400B of the semiconductor substrate 400. This sandwich structure (the middle vertical heat dissipation column structure in the chip, the top heat dissipation plate connected to the middle vertical heat dissipation column structure, and the heat dissipation plate located on the back side surface of the semiconductor substrate and connected to the middle vertical heat dissipation column structure) can greatly improve the heat dissipation capacity of the IC chip.

[0155] Advanced 2.5th generation (2.5D) or 3rd generation (3D) packaging structures, or even high bandwidth memory (HBM) structures, have two or more IC / memory chips stacked together. Figures 16a to 16d Any structure shown can be applied to the multiple IC chips stacked vertically. Fig.16e As shown, Fig.16e The vertical heat dissipation column structure shown in FIG. 1 can be applied to chips C1 and C2 stacked vertically together. Fig.16b The vertical heat dissipation column structure shown in FIG) can be flipped first and then stacked on chip C2 (with Fig.16d The vertical heat dissipation column structure shown in FIG. Fig.16f Of course, another interposer (such as a silicon interposer or other interposer) may be provided between the two IC chips, and Figures 16a to 16d Any of the structures shown may be employed in the interposer.

[0156] Fig.17a The semiconductor circuit structure includes a fin field effect transistor and a shallow trench isolation region adjacent to (or surrounding) the fin field effect transistor, wherein a portion of the shallow trench isolation region (marked by oblique lines) is replaced by a vertical heat dissipation column structure made of tungsten. Fig.17a The temperature distribution diagram of the fin field effect transistor created by the TCAD simulation software Sentaurus is also shown. When a portion of the shallow trench isolation region is replaced by tungsten, the temperature difference (ΔT) between the transistor peak temperature (hot spot area) and the ambient temperature (40°C) is calculated, as shown in Figure 2. Fig.17b More shown. Fig.17bThe term "completely" used in the figure means that all shallow trench isolation regions are not replaced by tungsten. The term "1nm" to "15nm" means the remaining thickness of the shallow trench isolation region that has not been replaced by tungsten. It can be clearly seen that the smaller the remaining thickness of the shallow trench isolation region, the smaller the temperature difference between the peak temperature of the transistor and the ambient temperature (the better the heat dissipation performance). Therefore, the present invention can effectively reduce the peak temperature of the transistor.

[0157] This specification provides a direct die cooling technology (or heat removal structure, such as vertical heat dissipation column lines and vertical heat dissipation column pads located below the original semiconductor surface and within the shallow trench isolation region) based on a composite material shallow trench isolation region. As needed, some vertical heat dissipation column structures can be connected to transistors, and the heat dissipation structure can form a vertical heat dissipation column grid or heat dissipation network within the chip or semiconductor substrate. Since the large shallow trench isolation region has sufficient space to accommodate the vertical heat dissipation column pad, it can provide a larger misalignment tolerance and shorten the path of connecting the back-side through silicon via plug (TSV) to the vertical heat dissipation column grid, thereby improving the IR drop of signal transmission and enhancing heat dissipation performance.

[0158] It is worth noting that the above-mentioned structures and methods are provided only to illustrate the technical features of the present invention. The technical content of this specification is not limited to the above-mentioned structures and methods. Other embodiments with different known components can be applied. The illustrated structure can be adjusted and changed according to the needs of actual applications. Of course, it should be noted that the configuration of the attached icons is only for illustration and not for limiting the present invention. Therefore, it is known to those with general knowledge in the art that the relevant components and layers in the semiconductor structure, the shape or positional relationship of the components and the process details can be adjusted or changed according to actual needs and / or actual applications.

[0159] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention.

[0160] Therefore, the protection scope of the present invention shall be based on the definition of the claims.

Claims

1. A semiconductor circuit structure, comprising: A semiconductor substrate having an original semiconductor surface (OSS); a set of active regions located in a semiconductor substrate; as well as a first shallow trench isolation region (STI) adjacent to the group of active regions and extending along a first direction to a spare shallow trench isolation region (spare STI region); the spare shallow trench isolation region is far away from the group of active regions; The first shallow trench isolation region includes a heat removing layer, and the material of the heat removing layer is different from silicon dioxide (SiO2).

2. The semiconductor circuit structure according to claim 1, wherein: The heat dissipation layer has a thermal conductivity higher than that of silicon dioxide.

3. The semiconductor circuit structure according to claim 2, wherein: The heat removal layer is an electrical insulator during an operation of the semiconductor circuit structure.

4. The semiconductor circuit structure according to claim 2, wherein: The heat removal layer extends into one of the set of active regions.

5. The semiconductor circuit structure according to claim 2, wherein: The heat dissipation layer includes a metal layer and an insulating thin layer, and the insulating thin layer is located between the metal layer and the group of active regions.

6. The semiconductor circuit structure according to claim 2, wherein: The heat removal layer includes a composite material.

7. The semiconductor circuit structure according to claim 2, wherein: The first shallow trench isolation region further includes a silicon dioxide layer located below the heat dissipation layer.

8. The semiconductor circuit structure according to claim 1, wherein: The heat removal layer is located in a front end of line (FEOL) region of the semiconductor circuit structure.

9. The semiconductor circuit structure according to claim 1, wherein: The first shallow trench isolation region surrounds the group of active regions.

10. The semiconductor circuit structure according to claim 9, wherein: The heat removal layer is located in the first shallow trench isolation region and below the original semiconductor surface, and the heat removal layer surrounds a peripheral border of the group of active regions.

11. The semiconductor circuit structure according to claim 1, wherein: The backup shallow trench isolation region is connected to the first shallow trench isolation region, and the heat dissipation layer extends along the first direction to the backup shallow trench isolation region.

12. The semiconductor circuit structure according to claim 11, wherein: The spare shallow trench isolation region is close to a center of the semiconductor substrate or close to an edge portion of the semiconductor substrate.

13. The semiconductor circuit structure according to claim 11, wherein: The invention further comprises a heat removal pad located in the spare shallow trench isolation region, and the heat removal layer is connected to the heat removal pad.

14. The semiconductor circuit structure according to claim 13, wherein: The invention further comprises a thermal via plug located above the spare shallow trench isolation region and connected to the heat dissipation pad located in the spare shallow trench isolation region.

15. The semiconductor circuit structure according to claim 14, wherein: A heat dissipation plate is further included which is located above the thermal via plug and connected to the thermal via plug.

16. The semiconductor circuit structure according to claim 14, wherein: It further includes a plurality of insulators located above the group of active regions, wherein the thermal via plug penetrates through the plurality of insulators and is connected to the heat dissipation pad located in the spare shallow trench isolation region.

17. The semiconductor circuit structure according to claim 16, wherein: The plurality of insulators and the thermal via plug are located in a back end of line (BEOL) region of the semiconductor circuit structure.

18. The semiconductor circuit structure according to claim 13, wherein: It further includes a semiconductor through semiconductor via (TSV) extending from a back side surface of the semiconductor substrate to a bottom surface of the heat dissipation pad located in the spare shallow trench isolation area, wherein the back side surface and the original semiconductor surface are located on opposite sides respectively.

19. The semiconductor circuit structure according to claim 18, wherein: The invention further comprises a heat dissipation plate, which is located below the back surface of the semiconductor substrate and connected to the semiconductor through-hole plug.

20. The semiconductor circuit structure according to claim 18, wherein: The first shallow trench isolation region surrounds four sidewalls of one of the set of active regions.

21. A semiconductor circuit structure comprising: A semiconductor substrate having an original semiconductor surface; a set of transistors formed in the semiconductor substrate; as well as A composite shallow trench isolation region is adjacent to the group of transistors and extends along a first direction to an edge portion of the semiconductor substrate; The composite shallow trench isolation region is located in a front end of line (FEOL) region of the semiconductor circuit structure.

22. The semiconductor circuit structure according to claim 21, wherein: The composite shallow trench isolation region includes a heat removal layer adjacent to the group of transistors and extending along the first direction to the edge portion of the semiconductor substrate.

23. The semiconductor circuit structure according to claim 22, wherein: A thermal via plug is disposed above or below the heat dissipation layer, wherein the thermal via plug is connected to the heat dissipation layer.

24. The semiconductor circuit structure according to claim 23, wherein: The invention further includes a heat sink above or below the semiconductor substrate, wherein the semiconductor substrate is connected to the thermal via plug.

25. The semiconductor circuit structure according to claim 23, characterized in that: The thermal via plug is located in a back-end process area of ​​the semiconductor circuit structure.

26. A semiconductor circuit structure comprising: A semiconductor substrate having an original semiconductor surface; A first set of active regions is located in the semiconductor substrate and extends along a first direction; a second set of active regions located in the semiconductor substrate and extending along the first direction; and a first shallow trench isolation region, located between the first group of active regions and the second group of active regions, and extending along a first direction to a spare shallow trench isolation region away from the first group of active regions and the second group of active regions; in, The first shallow trench isolation region includes a heat dissipation layer extending along the first direction, and a thermal conductivity of the heat dissipation layer is higher than a thermal conductivity of silicon dioxide.

27. The semiconductor circuit structure according to claim 26, wherein: The backup shallow trench isolation region is connected to the first shallow trench isolation region and includes a row of heat pads located in the backup shallow trench isolation region, wherein the heat dissipation layer is connected to the heat dissipation pads.

28. The semiconductor circuit structure according to claim 27, wherein: A width of the heat dissipation pad is greater than a width of the heat dissipation layer.

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