Chip package structure and method of manufacturing the same

Abstract

The application discloses a chip packaging structure and a preparation method thereof, and belongs to the technical field of chip packaging. The chip packaging structure comprises a substrate, a first heat dissipation layer, a chip and a second heat dissipation layer. The first heat dissipation layer is arranged on the substrate, and a first groove is arranged on the first heat dissipation layer. The chip is arranged in the first groove. The second heat dissipation layer is arranged on one side of the first heat dissipation layer close to the substrate. A sintering layer is arranged on one side of the second heat dissipation layer away from the substrate, and the material of the sintering layer comprises copper. The technical scheme can solve the problem of poor heat dissipation of the chip packaging structure in the related art.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to chip packaging structures and their fabrication methods. Background Technology

[0002] As people continue to pursue more complete functions of electronic products, the integration level of integrated circuits is getting higher and higher, the number of chip I / Os is increasing, and the integration level of system modules is also getting higher and higher. This forces chip (IC) level packaging and circuit board (PCB) level packaging technology to become closer and closer, thus giving rise to the embedded component packaging method. However, for GaN chips, which have better operating temperatures, better heat dissipation design is needed to bring out their excellent performance.

[0003] Currently, in related technologies, chip packaging structures primarily rely on thermally conductive adhesive, blind vias, insulating metal plates, or embedded copper layers for heat dissipation. However, compared to GaN chips, the heat dissipation effect of these chip packaging structures is insufficient to meet the operating temperature of GaN chips, thus affecting normal chip operation and preventing the chips from achieving their higher power density. Furthermore, in current related technologies, the heat dissipation path in the chip packaging structure is a vertical path, that is, a heat dissipation path from the top to the bottom of the chip packaging structure.

[0004] However, in GaN chip packaging structures, a resin layer is placed around the GaN chip to protect it. However, due to the low thermal conductivity of the resin layer, the chip packaging structure in related technologies cannot achieve efficient three-dimensional heat dissipation of the chip. Summary of the Invention

[0005] This application provides a chip packaging structure aimed at solving the problem of poor heat dissipation in chip packaging structures in related technologies.

[0006] In a first aspect, this application provides a chip packaging structure, including:

[0007] Base;

[0008] A first heat dissipation layer is disposed on the substrate, and a first groove is provided on the first heat dissipation layer;

[0009] A second heat dissipation layer is disposed on the side of the first heat dissipation layer near the substrate;

[0010] A sintered layer is disposed on the side of the second heat dissipation layer away from the substrate;

[0011] The sintered layer is made of copper.

[0012] In some embodiments, a second groove is provided on the side of the sintered layer away from the second heat dissipation layer, and the first heat dissipation layer is located in the second groove;

[0013] And / or, a third groove is provided on the side of the second heat dissipation layer away from the substrate, and the sintered layer is located in the third groove.

[0014] In some embodiments, the chip packaging structure further includes: a first thermally conductive layer, a conductive portion, and a second thermally conductive layer; the conductive portion is disposed between the substrate and the first thermally conductive layer;

[0015] The first thermally conductive layer is disposed between the conductive part and the second thermally conductive layer;

[0016] The second thermal conductive layer includes a first thermal conductive portion and a second thermal conductive portion. The first thermal conductive portion is disposed on the side of the chip away from the second thermal conductive layer. The second thermal conductive portion is disposed between the first thermal conductive portion and the substrate.

[0017] In some embodiments, the chip packaging structure further includes:

[0018] Multiple pads are provided on the surface of the chip away from the first thermal conductive layer; and / or, the pads are made of copper.

[0019] A conductive layer is disposed on the side of the second thermally conductive layer away from the chip; at least one conductive pillar is disposed on the side of the conductive layer close to the second thermally conductive layer.

[0020] The conductive post is electrically connected to the pad, and the orthographic projection of the conductive post on the substrate coincides with the orthographic projection of the pad on the substrate.

[0021] In some embodiments, the chip packaging structure further includes:

[0022] A first solder resist layer is disposed on the side of the substrate away from the chip;

[0023] The first solder mask layer is provided with a first through hole, and the orthographic projection of the first through hole on the substrate covers the orthographic projection of the second thermal conductive layer on the substrate.

[0024] And / or,

[0025] A second solder resist layer is disposed on the side of the conductive layer away from the chip;

[0026] The second solder mask layer has a second through hole, and the orthogonal projection of the second through hole on the substrate covers the orthogonal projection of the chip on the substrate.

[0027] In some embodiments, the chip packaging structure further includes:

[0028] A first antioxidant layer is disposed on the side of the substrate away from the chip and located in the first via.

[0029] And / or,

[0030] The second antioxidant layer is disposed on the side of the conductive layer away from the chip and is located in the second via.

[0031] In some embodiments, the length of the chip ranges from [3um, 10um]; the width of the chip ranges from [2um, 10um]; and the height of the chip ranges from [200um, 500um].

[0032] In some embodiments, the length of the third groove ranges from [53um, 60um]; the width of the third groove ranges from [52um, 60um]; and the height of the third groove ranges from [200um, 500um].

[0033] In some embodiments, the material of the first thermally conductive layer includes copper; and / or, the material of the second thermally conductive layer includes copper.

[0034] In the embodiments of this application, copper can be selected as the material for the sintering layer. This arrangement allows the heat generated by the chip during operation to be conducted to the substrate through the first heat dissipation layer, the sintering layer, and the second heat dissipation layer, all of which have high thermal conductivity, thereby achieving efficient heat dissipation.

[0035] Furthermore, in this embodiment, a first groove is provided on the first heat dissipation layer, and the chip is located in the first groove. This arrangement of placing the chip in the first groove allows the first heat dissipation layer to dissipate heat generated by the chip from the sidewalls and bottom wall of the groove in multiple directions, thereby achieving three-dimensional efficient heat dissipation of the chip packaging structure.

[0036] Secondly, this application also provides a method for fabricating a chip packaging structure, comprising:

[0037] A first heat dissipation layer is formed on the bottom and sides of the chip using a magnetron sputtering process;

[0038] A second heat dissipation layer is made using copper blocks;

[0039] Using a pressureless sintering process, the sintering material filling the space between the first heat dissipation layer and the second heat dissipation layer is sintered to form a sintered layer; wherein, the material of the sintered layer includes copper. Attached Figure Description

[0040] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0041] Figure 1A A schematic diagram of a chip packaging structure provided for related technology 1.

[0042] Figure 1B This is a schematic diagram of a chip packaging structure provided for related technology 2.

[0043] Figure 1C This is a schematic diagram of a chip packaging structure provided for related technology 3.

[0044] Figure 1D This is a schematic diagram of a chip packaging structure provided for related technology 4.

[0045] Figure 1E This is a partial structural diagram of a chip packaging structure provided for related technology 5.

[0046] Figure 1F A schematic diagram of the chip packaging structure provided for related technologies.

[0047] Figure 1G A schematic diagram illustrating the heat dissipation principle of a chip packaging structure provided for related technologies.

[0048] Figure 1 This is a schematic diagram of a chip packaging structure provided in this application.

[0049] Figure 2 This is a partial flowchart illustrating a method for fabricating a chip packaging structure provided in this application.

[0050] Figure 3 This is a schematic flowchart illustrating a method for fabricating a chip packaging structure provided in this application.

[0051] Figures 4A to 4O This is a schematic diagram illustrating the process of fabricating a chip packaging structure provided in this application. Detailed Implementation

[0052] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0053] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0054] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0055] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0056] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0057] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0058] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0059] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0060] Currently, with people's continuous pursuit of more complete functions in electronic products, the integration level of integrated circuits is getting higher and higher, the number of chip I / Os is increasing, and the integration level of system modules is also getting higher and higher, which makes the connection between chip (IC) level packaging and circuit board (PCB) level packaging technology closer and closer.

[0061] Therefore, embedded component packaging emerged. However, since GaN chips operate at high temperatures, better heat dissipation design is needed to realize their excellent performance.

[0062] Currently, the mainstream heat dissipation path only focuses on vertical heat dissipation at the top and bottom of the chip. For embedded 3D packaging, a lot of heat also accumulates in the resin layer around the side of the chip.

[0063] For example, Figure 1A A schematic diagram of a chip packaging structure provided for related technology 1. Figure 1B A schematic diagram of a chip packaging structure provided for related technology 2. Figure 1C This is a schematic diagram of a chip packaging structure provided for related technology 3. Figure 1D A schematic diagram of a chip packaging structure provided for related technology 4. Figure 1E A schematic diagram of a chip packaging structure provided for related technology 5, such as Figure 1A As shown, in related technology 1,

[0064] The chip packaging structure includes a substrate, thermally conductive adhesive 2A, and a chip 1A. The chip 1A is bonded to the substrate via the thermally conductive adhesive 2A. Heat generated by the chip 1A during operation is transferred to the substrate for heat dissipation via the thermally conductive adhesive 2A. Furthermore, the thermal conductivity of the thermally conductive adhesive ranges from [0.6 W / (m·K), 1.5 W / (m·K)]. For example, in one example, the thermal conductivity of the thermally conductive adhesive is 0.6 W / (m·K), 0.9 W / (m·K), 1 W / (m·K), 1.2 W / (m·K), and 1.5 W / (m·K).

[0065] In related technology 2, such as Figure 1B As shown, the chip package structure includes a substrate, multiple blind vias Va, and a chip 1B. The chip 1B is connected to the substrate via the blind vias Va. Furthermore, a dielectric material with a thermal conductivity of 0.6 W / (m·K) is disposed within the blind vias Va. The heat generated by the chip 1B during operation is transferred to the substrate for heat dissipation through the dielectric material in the blind vias Va.

[0066] In related technology 3, such as Figure 1C As shown, Figure 1CAs shown, the chip package structure includes an Insulated Metal Substrate (IMS), a Gate Driver Board (GDB), and a chip 3A. The heat generated by the chip 3A during operation is dissipated through the IMS.

[0067] In related technology 4, such as Figure 1D As shown, the chip packaging structure includes a baseplate, a substrate DBC, and a GaN chip device. The GaN chip device is disposed on the substrate DBC, and the heat generated by the GaN chip device during operation is conducted to the baseplate through the substrate DBC, and is dissipated through the substrate DBC and the baseplate.

[0068] In related technology 5, such as Figure 1E As shown, the chip packaging structure includes a chip (not shown) and a copper block 5B, wherein the chip is soldered or bonded to the upper part of the copper block 5B, and the heat generated by the chip during operation is dissipated through the copper block 5B.

[0069] In summary, current related technologies primarily rely on thermally conductive adhesive, blind vias, insulating metal plates, or copper blocks for heat dissipation in chip packaging structures. However, compared to GaN chips, the heat dissipation performance of the aforementioned chip packaging structures is insufficient to meet the operating temperature requirements of GaN chips, thus affecting their normal operation and preventing them from achieving their higher power density.

[0070] Furthermore, in current related technologies, the heat dissipation path in the chip packaging structure is a vertical heat dissipation path, that is, a heat dissipation path from the top of the chip packaging structure to the bottom of the chip packaging structure.

[0071] However, in GaN chip packaging structures, a resin layer is placed around the GaN chip to protect it. However, due to the low thermal conductivity of the resin layer, the chip packaging structure in related technologies cannot achieve efficient three-dimensional heat dissipation of the chip.

[0072] The following analysis, based on the underlying principles, examines the heat dissipation path and performance of the chip packaging structure in related technologies 1-5:

[0073] Figure 1F A schematic diagram of a chip packaging structure provided for related technologies. Figure 1G A schematic diagram of the heat dissipation principle of the chip packaging structure provided for related technologies, such as Figure 1F and Figure 1G As shown, the chip package structure includes a chip 6A and a PCB board 6B, wherein the chip 6A is disposed on the PCB board 6B.

[0074] refer to Figure 1F and Figure 1G It can be seen that T C T is the temperature of the chip package surface. B Temperature of the PCB surface when chip 6A is installed; T A The ambient temperature; T J The temperature of the transistor junction inside the chip is denoted as ; P is the chip power.

[0075] The formula for the thermal resistance from the chip to the packaging layer is:

[0076] ;

[0077] The formula for the thermal resistance from the chip to the PCB board is:

[0078]

[0079] In summary, in current related technologies, the heat dissipation path in chip packaging structures is a vertical heat dissipation path, that is, a heat dissipation path from the top to the bottom of the chip packaging structure. The thermal resistance formula is as described above.

[0080] Figure 1 This application provides a schematic diagram of a chip packaging structure, as shown below. Figure 1 As shown, the chip packaging structure includes: a substrate 1, a chip 2, a first heat dissipation layer 3, a second heat dissipation layer 4, and a sintering layer 5. The first heat dissipation layer 3 is disposed on the substrate 1, and a first groove V1 is formed on the first heat dissipation layer 3. The chip 2 is disposed in the first groove V1. Further, the chip 2 can be a GaN chip. The second heat dissipation layer 4 is disposed on the side of the first heat dissipation layer 3 closest to the substrate 1.

[0081] The sintered layer 5 is disposed on the side of the second heat dissipation layer 4 away from the substrate 1, and the material of the sintered layer 5 includes copper. In this embodiment, the thermal conductivity of the sintered layer 5 is as high as 200 W / (m·K), which can efficiently dissipate heat from the chip 2.

[0082] In this embodiment, the sintered layer 5 can be made of copper. This arrangement allows the heat generated by the chip 2 during operation to be conducted to the substrate 1 through the first heat dissipation layer 3, the sintered layer 5, and the second heat dissipation layer 4, all of which have high thermal conductivity, thereby achieving efficient heat dissipation.

[0083] Furthermore, in this embodiment, a first groove V1 is provided on the first heat dissipation layer 3, and the chip 2 is located in the first groove V1. This arrangement of placing the chip 2 in the first groove V1 allows the heat generated by the chip 2 by the first heat dissipation layer 3 to dissipate heat in multiple directions from the sidewalls and bottom wall of the first groove V1, thereby achieving three-dimensional efficient heat dissipation of the chip packaging structure. Compared with the chip packaging structures provided in related technologies, the chip packaging structure provided in this application has a better heat dissipation effect.

[0084] Of course, in another embodiment, the materials of the first heat dissipation layer 3, the second heat dissipation layer 4, and the sintering layer 5 can all be copper. For example, the first heat dissipation layer 3 is a first copper layer, the second heat dissipation layer 4 is a second copper layer, and the sintering material used for the sintering layer 5 is copper paste. This arrangement allows the heat generated by the chip 2 during operation to be conducted to the substrate 1 through the first copper layer, the sintering layer 5, and the second copper layer, which have high thermal conductivity, thereby achieving efficient heat dissipation.

[0085] Preferably, when the chip in the chip package structure is a GaN chip, since the source, gate, and drain of the GaN chip are all disposed on the surface of the GaN chip, the chip package structure provided in this application embodiment is more suitable for efficient three-dimensional heat dissipation of GaN chips.

[0086] In some embodiments, a second groove V2 is provided on the side of the sintered layer 5 away from the second heat dissipation layer 4, and the first heat dissipation layer 3 is located in the second groove V2; and / or, a third groove V3 is provided on the side of the second heat dissipation layer 4 away from the substrate 1, and the sintered layer 5 is located in the third groove V3.

[0087] This application achieves three-dimensional heat dissipation of the chip by providing a first groove V1, a second groove V2, and a third groove V3 on the first heat dissipation layer 3, the sintering layer 5, and the second heat dissipation layer 4, respectively, and placing the chip in the first groove V1, the sintering layer in the second groove V2, and the second heat dissipation layer 4 in the third groove V3.

[0088] In some embodiments, the chip packaging structure further includes: a first thermally conductive layer 7, a conductive portion 20, and a second thermally conductive layer 8, wherein the conductive portion 20 is disposed between the substrate 1 and the first thermally conductive layer 7; and the first thermally conductive layer 7 is disposed between the conductive portion 20 and the second thermally conductive layer 8.

[0089] The second thermal conductive layer 8 includes a first thermal conductive part 80 and a second thermal conductive part 81 connected as one piece. The first thermal conductive part 80 is disposed on the side of the chip 2 away from the second heat dissipation layer 4, and the second thermal conductive part 81 is disposed between the first thermal conductive part 80 and the substrate 1.

[0090] Furthermore, the materials of the first thermally conductive layer 7 and the second thermally conductive layer 8 can be the same or different. For example, in the embodiments of this application, the material of the first thermally conductive layer 7 includes BT resin; the material of the second thermally conductive layer 8 includes BT resin.

[0091] Furthermore, the second thermal conductive layer 8 includes a first thermal conductive part 80 and a second thermal conductive part 81. The first thermal conductive part 80 is disposed on the side of the chip 2 away from the second heat dissipation layer 4, and the second thermal conductive part 81 is disposed between the first thermal conductive layer 7 and the second heat dissipation layer 4.

[0092] In some embodiments, the chip package structure further includes: a plurality of pads 13 and a conductive layer 9. The plurality of pads 13 are respectively disposed on the surface of the chip 2 away from the first heat dissipation layer 3; and / or, the material of the pads 13 is copper.

[0093] The conductive layer 9 is disposed on the side of the second thermal conductive layer 80 away from the chip 2, and at least one conductive post 14 is disposed on the side of the conductive layer 9 close to the second thermal conductive layer 80; the conductive post 14 is electrically connected to the pad, and the orthographic projection of the conductive post 14 on the substrate coincides with the orthographic projection of the pad on the substrate.

[0094] In this embodiment, the chip 2 transmits electrical signals to the outside world through the electrical connection between the pad 13 and the conductive layer 9.

[0095] In some embodiments, the chip packaging structure further includes: a first solder resist layer 10, and / or a second solder resist layer 11;

[0096] The first solder resist layer 10 is disposed on the side of the substrate 1 away from the chip 2, and the first solder resist layer 10 is provided with a first through hole V4. The orthogonal projection of the first through hole V4 on the substrate 1 covers the orthogonal projection of the second thermal conductive layer 4 on the substrate 1.

[0097] The second solder resist layer 10 is disposed on the side of the conductive layer 9 away from the chip 2.

[0098] A second through-hole V5 is provided on the second solder mask layer 11, and the orthogonal projection of the second through-hole V5 on the substrate 1 covers the orthogonal projection of the chip 2 on the substrate 1.

[0099] In some embodiments, the chip package structure further includes: a first antioxidant layer 16, and / or a second antioxidant layer 17. The first antioxidant layer 16 is disposed on the side of the substrate 1 away from the chip 2 and is located in the first via V4.

[0100] Furthermore, the orthographic projection of the first antioxidant layer 16 on the substrate 1 coincides with the orthographic projection of the first through hole V4 on the substrate 1.

[0101] And / or, the second antioxidant layer 17 is disposed on the side of the conductive layer 9 near the chip 2 and is located in the second via V5.

[0102] Furthermore, the orthographic projection of the second antioxidant layer 17 on the substrate 1 coincides with the orthographic projection of the second through hole V5 on the substrate 1.

[0103] In some embodiments, the length of chip 2 ranges from [3μm to 10μm]; the width of chip 2 ranges from [2μm to 10μm]; and the height of chip 2 ranges from [200μm to 500μm].

[0104] For example, the length of chip 2 can be 3μm, 5μm, 7μm, 9μm, or 10μm; the width of chip 2 can be 2μm, 4μm, 6μm, 8μm, or 10μm; and the height of chip 2 can be 200μm, 250μm, 300μm, 350μm, 400μm, or 500μm.

[0105] In some embodiments, the length of the third groove V3 ranges from [53 μm to 60 μm]; the width of the third groove V3 ranges from [52 μm to 60 μm]; and the height of the third groove V3 ranges from [200 μm to 500 μm].

[0106] For example, the length L1 of the third groove V3 can be 53μm, 55μm, 58μm, or 60μm; the width L3 of the third groove V3 can be 52μm, 53μm, 55μm, 58μm, or 60μm; and the height L2 of the third groove V3 can be 200μm, 300μm, 400μm, 450μm, or 500μm.

[0107] Furthermore, the thickness L4 of the bottom of the third groove is 0.1 mm.

[0108] In some embodiments, the material of the first thermally conductive layer 7 includes copper; and / or, the material of the second thermally conductive layer 8 includes copper; and / or, the material of the first heat dissipation layer 3 includes copper; and / or, the material of the second heat dissipation layer 4 includes copper. For example, in one example, the material of the first thermally conductive layer 7 is copper and the material of the second thermally conductive layer 8 is copper.

[0109] Figure 2 This is a partial flowchart illustrating a method for fabricating a chip packaging structure provided in this application, as shown below. Figure 2 As shown, the preparation method includes:

[0110] S10. Using magnetron sputtering, a first heat dissipation layer with a first groove is formed on the bottom and side of the chip;

[0111] S20. Use copper blocks to create a second heat dissipation layer;

[0112] S30. Using a pressureless sintering process, the sintering material filling the space between the first heat dissipation layer and the second heat dissipation layer is sintered to form a sintered layer; wherein the material of the sintered layer includes copper.

[0113] Based on the above embodiments, this application also provides a specific embodiment of a method for fabricating a chip packaging structure, wherein, Figure 3 This is a schematic flowchart illustrating a method for fabricating a chip packaging structure provided in this application. Figures 4A to 4O This is a schematic diagram illustrating the process of fabricating a chip packaging structure provided in this application, as shown below. Figure 3 as well as Figures 4A to 4O As shown, the method includes:

[0114] S1. Using magnetron sputtering, titanium and copper layers are sequentially sputtered onto the bottom and sides of the chip to form the first heat dissipation layer. The chip can be a GaN chip.

[0115] Furthermore, the chip is provided with pads, and the upper surface of the pads is not higher than the upper surface of the passivation layer on the surface of chip 2. This arrangement can prevent short circuits when the chip 2 is side-sputtered.

[0116] For example, in one instance, a 0.1 μm Ti layer and a 4 μm copper layer (first heat dissipation layer) are sequentially sputtered onto the back side of the substrate of chip 2 (the substrate is typically a Si substrate) by magnetron sputtering for interconnection in the back-end sintering process, thereby improving interlayer reliability.

[0117] Then, magnetron sputtering is performed on the sides (left and right sides) of chip 2: chip 2 with the first heat dissipation layer is placed on the magnetron sputtering platform and made perpendicular to the sputtering surface. A 0.1μm Ti layer and a 4μm copper layer (second heat dissipation layer 4) are formed on the sides of chip 2 with the first heat dissipation layer.

[0118] S2. Using a pressureless sintering process, the first heat dissipation layer and the second heat dissipation layer 4 are sintered; using a dispensing process, sintering material is filled between the chip and the substrate to form a sintered layer and obtain a sample.

[0119] In the pressureless sintering process, a copper film with a thickness of approximately 75 μm can be directly bonded to the second heat dissipation layer 4. The sintering conditions are: baking at 250°C for 3 hours in an oxygen-free (nitrogen atmosphere). This method can result in a sintered layer with good flatness.

[0120] Alternatively, the nano-copper paste can be applied to the second heat dissipation layer 4 by screen printing or dispensing. In this case, the thickness of the nano-copper paste should be approximately 100 μm.

[0121] The GaN chip 2, after the above treatment, is attached to the second heat dissipation film, with the pads of the GaN chip 2 located on the side furthest from the substrate. This arrangement allows the offset tolerance of the GaN chip 2 to be ≤10μm.

[0122] It should be noted that in the pressureless sintering process, the gap between the first heat dissipation layer and the second heat dissipation layer 4 is filled with nano copper paste through a dispensing process, and the copper paste is not higher than the surface of the second heat dissipation layer 4 away from the substrate, thereby preventing short circuits.

[0123] S3. The first thermally conductive layer is pressed together with the copper layer on the PCB substrate to form a lamination layer, and a non-sealed groove is formed on the lamination layer using a laser.

[0124] Furthermore, the total thickness of the lamination layer is related to the height of chip 2 and the bottom thickness of the second groove V2.

[0125] For example, in this embodiment, the total thickness of the lamination layer ranges from L2 to L4 to 30 μm. Here, L2 is the height of chip 2, and its value ranges from [200 μm to 500 μm], and L4 (L4 = 0.1 mm) is the bottom thickness of the third groove V3.

[0126] Furthermore, in this application, a UV laser is used to ablate a predetermined area of ​​the laminate to form a non-sealed groove.

[0127] S4. An adhesive layer 30 is provided on the side of the copper layer away from the first thermal conductive layer, and the surface of the sample away from the chip 2 is bonded to the surface of the adhesive layer 30 close to the copper layer.

[0128] Furthermore, the adhesive layer 30 can be PI high-temperature tape to support the embedded second heat dissipation layer 4, and the adhesive function of the PI high-temperature tape is used to prevent the embedded second heat dissipation layer 4 from shifting during the bonding process.

[0129] In the embodiments of this application, the misalignment accuracy of sample bonding is ≤10μm.

[0130] S5. A second thermal conductive layer is formed on the side of the chip away from the substrate; wherein the second thermal conductive layer includes a first thermal conductive part and a second thermal conductive part, the first thermal conductive part is disposed on the side of the chip away from the second thermal conductive layer; the second thermal conductive part is disposed between the first thermal conductive layer and the first thermal conductive layer.

[0131] The step of forming a second thermally conductive layer on the side of chip 2 away from the substrate further includes: laminating the second thermally conductive layer with a lamination layer, wherein the thickness of the second thermally conductive layer is 100 μm.

[0132] Of course, users can make reasonable choices regarding the thickness of the second thermal conductive layer by combining the width and height of the unsealed groove, thereby preventing reliability risks such as missing adhesive around the second thermal conductive layer after pressing.

[0133] S6. Using laser technology, at least one through hole is formed on the side of the second thermally conductive layer away from the chip.

[0134] The second thermally conductive layer above the pads of chip 2 is ablated using a CO2 laser to form at least one through hole for subsequent electroplating of conductive pillars 14.

[0135] During the process of CO2 laser ablation of the second thermally conductive layer above the pads of chip 2, the pads on chip 2 must not be broken through, otherwise chip 2 will fail.

[0136] S7. A conductive layer 9 is provided on the side of the second thermal conductive layer away from the chip, and at least one conductive pillar is provided on the side of the conductive layer 9 close to the second thermal conductive layer.

[0137] Through processes such as horizontal descaling, horizontal hole formation, and VCP via filling, a conductive layer 9 above the second thermal conductive layer and conductive pillars 14 for connecting the chip pads are formed.

[0138] S8. The conductive pillar is electrically connected to the chip's pad through a through-hole, and the orthographic projection of the conductive pillar on the substrate coincides with the orthographic projection of the pad on the substrate.

[0139] S9. A first solder resist layer is formed on the side of the substrate away from the chip, and / or a second solder resist layer is formed on the side of the conductive layer 9 away from the second thermally conductive layer.

[0140] Based on the above steps, a first solder resist layer is formed on the side of the substrate away from the chip 2, and / or a second solder resist layer is formed on the side of the conductive layer 9 away from the second thermally conductive layer, thereby forming a chip package structure.

[0141] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip package structure, characterized by, Comprise: a substrate; a first heat dissipation layer, the first heat dissipation layer is arranged on the substrate, and a first recess is arranged on the first heat dissipation layer; a chip, the chip is arranged in the first recess; a second heat dissipation layer, the second heat dissipation layer is arranged on the side of the first heat dissipation layer close to the substrate; a sintering layer, the sintering layer is arranged on the side of the second heat dissipation layer away from the substrate; wherein the material of the sintering layer comprises copper; the side of the sintering layer away from the second heat dissipation layer is provided with a second recess, and the first heat dissipation layer is located in the second recess; and / or, the side of the second heat dissipation layer away from the substrate is provided with a third recess, and the sintering layer is located in the third recess; The chip package structure further comprises: a first heat conduction layer, an electrically conductive part, and a second heat conduction layer; The electrically conductive part is arranged between the substrate and the first heat conduction layer; The first heat conduction layer is arranged between the electrically conductive part and the second heat conduction layer; The second heat conduction layer comprises a first heat conduction part and a second heat conduction part connected as a whole, the first heat conduction part is arranged on the side of the chip away from the second heat dissipation layer, and the second heat conduction part is arranged between the first heat conduction part and the substrate.

2. The chip package structure of claim 1, wherein, Also include: a plurality of pads, a plurality of the pads are respectively arranged on the surface of the side of the chip away from the first heat dissipation layer; and / or, the material of the pad is copper; The electrically conductive layer is arranged on the side of the second heat conduction layer away from the chip; The side of the electrically conductive layer close to the second heat conduction layer is provided with at least one electrically conductive column; The electrically conductive column is electrically connected with the pad, and the orthographic projection of the electrically conductive column on the substrate coincides with the orthographic projection of the pad on the substrate.

3. The chip package structure of claim 2, wherein, Also include: A first solder resist layer, the first solder resist layer is arranged on the side of the substrate away from the chip; Wherein, the first solder resist layer is provided with a first through hole, and the orthographic projection of the first through hole on the substrate covers the orthographic projection of the second heat conduction layer on the substrate; and / or, A second solder resist layer, the second solder resist layer is arranged on the side of the electrically conductive layer away from the chip; The second solder resist layer is provided with a second through hole, and the orthographic projection of the second through hole on the substrate covers the orthographic projection of the chip on the substrate.

4. The chip package structure of claim 3, wherein, Also include: A first oxidation-resistant layer, the first oxidation-resistant layer is arranged on the side of the substrate away from the chip, and located in the first through hole; and / or, A second oxidation-resistant layer, the second oxidation-resistant layer is arranged on the side of the electrically conductive layer away from the chip, and located in the second through hole.

5. The chip package structure of claim 1, wherein, The length of the chip ranges from [3μm, 10μm]; The width of the chip ranges from [2μm, 10μm]; The height of the chip ranges from [200μm, 500μm].

6. The chip package structure of claim 1, wherein, The length of the third recess ranges from [53μm, 60μm]; The width of the third recess ranges from [52μm, 60μm]; The height of the third recess ranges from [200μm, 500μm].

7. The chip package structure of claim 1, wherein, The material of the first heat conduction layer comprises: copper; and / or, the material of the second heat conduction layer comprises: copper; And / or, the material of the first heat dissipation layer comprises copper; and / or, the material of the second heat dissipation layer comprises copper.

8. A method of producing a chip package structure, which is adapted to produce the chip package structure according to any one of claims 1 to 7, characterized by, Comprise: A first heat dissipation layer is formed on the bottom and side edges of the chip by using a magnetron sputtering process; A second heat dissipation layer is made of a copper block; The sintered material filled between the first heat dissipation layer and the second heat dissipation layer is sintered by using a pressureless sintering process to form a sintered layer; wherein the material of the sintered layer comprises copper.

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