Heat dissipation cover, chip packaging structure and chip packaging method

Abstract

The invention relates to the technical field of semiconductor packaging, and discloses a heat dissipation cover, a chip packaging structure and a chip packaging method.The heat dissipation cover comprises a cover body and a supporting structure connected with the cover body, and the supporting structure is provided with a containing space for containing a semiconductor chip; the end, away from the cover body, of the supporting structure is used for being connected with a packaging substrate, a groove is formed in the end, away from the cover body, of the supporting structure, and / or the surface roughness of the end, away from the cover body, of the supporting structure is larger than that of the end, close to the cover body, of the supporting structure. The surface roughness of the heat dissipation cover is increased, and / or the contact area of the heat dissipation cover and the insulation paste is increased by arranging the groove, so that the firmness of the heat dissipation cover fixed on the packaging substrate is improved, and the falling risk of the heat dissipation cover is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a heat dissipation cover, a chip packaging structure and a chip packaging method. Background Art

[0002] Flip Chip Ball Grid Array (FCBGA) packaging is an advanced packaging technology that pastes the chip on the substrate in the form of flip-chip and uses spherical solder as the electrical connection point. FCBGA has the advantages of excellent electrical performance, high input / output (I / O) pin density and small package size. It is mainly used in the field of high-density, high-speed and multi-functional large-scale integrated circuit chip packaging.

[0003] In FCBGA devices, the heat sink is not only used to guide the heat of the chip to dissipate and relieve the heat dissipation pressure of the heat sink, but also used to protect the chip and provide support for the chip. As the functional requirements of FCBGA continue to increase, the chip size and required circuit components become larger and more numerous, the weight and internal stress borne by the heat sink increase, and the bonding force between the heat sink and the insulating glue may be difficult to resist the increased stress, resulting in an increased risk of the heat sink falling off the substrate, affecting the performance and reliability of the chip. Summary of the invention

[0004] In view of this, the present invention provides a heat dissipation cover, a chip packaging structure and a chip packaging method to reduce the risk of the heat dissipation cover falling off a substrate.

[0005] In a first aspect, the present invention provides a heat dissipation cover, which is applied to a chip packaging structure. The heat dissipation cover includes a cover body and a support structure connected to the cover body, wherein the support structure has an accommodation space for accommodating a semiconductor chip; an end of the support structure away from the cover body is used to be connected to a packaging substrate, and a groove is provided at the end of the support structure away from the cover body, and / or the surface roughness of the end of the support structure away from the cover body is greater than the surface roughness of the end of the support structure close to the cover body.

[0006] In this embodiment, by providing a groove at the bottom of the support structure and / or increasing the surface roughness of the bottom of the support structure, the contact area between the support structure and the insulating glue on the packaging substrate can be increased, thereby improving the bonding force between the heat dissipation cover and the insulating glue, and more firmly fixing the heat dissipation cover on the packaging substrate, reducing the risk of the heat dissipation cover falling. Moreover, the packaging substrate connected to the heat dissipation cover can be pulled by the strong bonding force, thereby improving the deformation of the chip packaging structure.

[0007] In an optional implementation, the length of the groove ranges from 10 μm to 100 μm, and the depth of the groove ranges from 10 μm to 100 μm.

[0008] In this embodiment, the length and depth of the groove are limited to between 10 μm and 100 μm, which can further reduce the risk of the cover falling off. Moreover, limiting the length and depth of the groove to between 10 μm and 100 μm can also provide a better filling space for the insulating glue, enhance the anchoring effect of the insulating glue, effectively disperse the stress, and avoid stress concentration on the bonding interface between the insulating glue and the heat dissipation cover or the packaging substrate, thereby reducing the possibility of glue bonding failure and reducing the risk of the cover falling off.

[0009] In an optional embodiment, the groove is semicircular, or the groove is serrated, or the groove is pitted.

[0010] In an optional embodiment, there are multiple grooves, and the multiple grooves are arranged at intervals along the length direction of the support structure.

[0011] In a second aspect, the present invention provides a chip packaging structure, which includes a packaging substrate, a semiconductor chip and a heat dissipation cover according to the first aspect or any corresponding embodiment thereof; the active surface of the semiconductor chip is arranged on the packaging substrate, the heat dissipation cover is arranged on the packaging substrate, and the heat dissipation cover is arranged on the semiconductor chip.

[0012] In an optional implementation, the support structure of the heat dissipation cover is fixed on the packaging substrate by means of insulating glue.

[0013] In an optional implementation, the insulating adhesive is epoxy resin-based insulating adhesive, silicone rubber-based insulating adhesive or polyimide insulating adhesive.

[0014] In an optional implementation, the cover body of the heat dissipation cover and a surface of the semiconductor chip on a side away from the packaging substrate are fixedly connected by heat dissipation adhesive.

[0015] In a third aspect, the present invention provides a chip packaging method, which includes: providing a packaging substrate, a semiconductor chip and a heat dissipation cover according to the first aspect or any corresponding embodiment thereof; welding and fixing the active surface of the semiconductor chip to a side surface of the packaging substrate; coating an insulating adhesive on an edge of the packaging substrate; coating a heat dissipation adhesive on a side surface of the semiconductor chip away from the packaging substrate; attaching a support structure of the heat dissipation cover to an area of ​​the packaging substrate coated with the insulating adhesive, and performing a curing treatment to fix the heat dissipation cover on the packaging substrate.

[0016] In an optional embodiment, the temperature of the curing treatment ranges from 100°C to 200°C. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a cross-sectional view of a heat dissipation cover according to an embodiment of the present invention;

[0019] Figure 2 is a front view of a heat dissipation cover according to an embodiment of the present invention;

[0020] Figure 3 is a cross-sectional view of another heat dissipation cover according to an embodiment of the present invention;

[0021] Figure 4 is a cross-sectional view of a chip packaging structure according to an embodiment of the present invention;

[0022] Figure 5 is a front view of a chip packaging structure according to an embodiment of the present invention;

[0023] Figure 6 is a schematic diagram of coating insulating glue on a packaging substrate with a semiconductor chip welded thereon according to an embodiment of the present invention;

[0024] Figure 7 According to an embodiment of the present invention Figure 6 Schematic diagram of applying heat dissipation glue on the foundation;

[0025] Figure 8 According to an embodiment of the present invention Figure 7 A schematic diagram of a heat dissipation cover provided on the foundation;

[0026] Fig. 9 According to an embodiment of the present invention Figure 8 Schematic diagram of the curing process on the basis.

[0027] Figure numerals: 100, heat dissipation cover; 110, cover body; 120, support structure; 121, accommodating space; 122, groove; 200, packaging substrate; 300, semiconductor chip; 400, insulating glue; 500, heat dissipation glue; 600, glue dispenser. DETAILED DESCRIPTION

[0028] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0029] In the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified for the purpose of clear expression, and some details may be omitted. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships between them are only exemplary, and may be deviated due to manufacturing tolerances or technical limitations in practice, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be a middle layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.

[0030] FCBGA packaging is an integrated circuit packaging technology. In FCBGA packaging, the semiconductor chip is flipped and installed, with the active surface (the side with circuit connection) of the semiconductor chip facing down and directly connected to the packaging substrate through solder bumps.

[0031] In FCBGA packaging, the heat sink plays a key role in the heat dissipation of semiconductor chips. The heat sink is usually bonded to the package substrate with insulating glue. When the size of the semiconductor chip and the number of circuit components in the FCBGA package structure increase, the heat sink needs to cover a larger area to effectively dissipate heat. However, the bonding force between the heat sink and the insulating glue is limited, and it is difficult to meet the tensile force required after the heat sink is enlarged, resulting in an increased risk of the heat sink falling off the substrate.

[0032] If the heat dissipation cover falls off, it will affect the performance and reliability of the semiconductor chip. Specifically, if the heat dissipation cover falls off, first of all, the heat dissipation function will be damaged, making it difficult to effectively dissipate the heat generated by the semiconductor chip during operation, which will in turn cause the temperature of the semiconductor chip to rise, thereby affecting the performance of the semiconductor chip, and may even damage the semiconductor chip due to overheating. Secondly, the falling of the heat dissipation cover may cause physical damage to the internal circuit components, or cause problems such as electrical short circuits, reducing the reliability of the packaging structure.

[0033] In view of this, the present invention provides a heat dissipation cover, which increases the contact area between the heat dissipation cover and the insulating glue by increasing the surface roughness of the heat dissipation cover and / or setting grooves, thereby improving the firmness of the heat dissipation cover fixed to the packaging substrate and reducing the risk of the heat dissipation cover falling.

[0034] The heat dissipation cover provided by the present invention is applied to a chip packaging structure, and the chip packaging structure may be an FCBGA packaging structure or other chip packaging structures with heat dissipation requirements.

[0035] Firstly, the structure of the heat dissipation cover provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0036] like Figure 1 and Figure 2 As shown, the heat dissipation cover 100 provided by the present invention includes a cover body 110 and a support structure 120 connected to the cover body 110 .

[0037] The support structure 120 has a receiving space 121 for receiving a semiconductor chip (not shown in the figure), and the support structure 120 can be a rectangular frame structure. That is, the heat dissipation cover 100 is arranged on the semiconductor chip to play a heat dissipation role to meet the heat dissipation requirements of the chip packaging structure.

[0038] Specifically, the end of the support structure 120 away from the cover body 110 is used to connect to the packaging substrate (not shown in the figure), the end of the support structure 120 away from the cover body 110 is provided with a groove 122, and / or the surface roughness of the end of the support structure 120 away from the cover body 110 is greater than the surface roughness of the end of the support structure 120 close to the cover body 110.

[0039] That is to say, the bottom end of the support structure 120 may be only provided with a groove 122, or the surface roughness of the bottom end of the support structure 120 may be greater than the surface roughness of other end surfaces of the support structure 120, or the surface roughness of the bottom end of the support structure 120 may be greater than the surface roughness of other end surfaces of the support structure 120 and a plurality of grooves 122 may also be provided.

[0040] In this embodiment, by providing a groove 122 at the bottom of the support structure 120 and / or increasing the surface roughness of the bottom of the support structure 120, the contact area between the support structure 120 and the insulating glue on the package substrate can be increased, thereby improving the bonding force between the heat dissipation cover 100 and the insulating glue, and more firmly fixing the heat dissipation cover 100 on the package substrate, reducing the risk of the heat dissipation cover 100 falling. Moreover, the package substrate connected to the heat dissipation cover 100 can be pulled by the strong bonding force, thereby improving the deformation of the chip package structure.

[0041] In the above embodiments, the semiconductor chip may be a central processing unit (CPU), a graphics processing unit (GPU), a baseband processing unit (BBU) chip, a communication chip or a storage chip, etc., and the present invention is not limited thereto.

[0042] Specifically, the CPU is the core component of the computer system, responsible for executing instructions in the computer program, performing data processing and calculations. The GPU can be used to accelerate graphics rendering tasks, as well as to accelerate parallel computing tasks such as matrix operations in deep learning. For example, when training a neural network model, the GPU can process a large number of matrix multiplication operations at the same time to increase the computing speed. The BBU chip is used to process baseband signals, such as encoding and modulating the information to be sent (such as voice, data, etc.). The communication chip is used to realize the communication function between devices. The communication chip can be a radio frequency chip, a modem chip, etc. The storage chip is used to store data and programs. The storage chip can be a random access memory (Random Access Memory, RAM) chip, a read-only memory (Read Only Memory, ROM) chip, etc.

[0043] Illustratively, the cover 110 and the support structure 120 may be integrally formed.

[0044] like Figure 2 As shown, the number of the grooves 122 provided at the bottom end of the support structure 120 may be one or more. When the number of the grooves 122 is more than one, as shown in FIG. Figure 2 As shown, a plurality of grooves 122 are arranged along the length direction ( Figure 2 The plurality of grooves 122 are arranged at intervals in the horizontal direction under the viewing angle, and the opening directions of the plurality of grooves 122 are consistent. The plurality of grooves 122 can be randomly distributed or distributed according to a rule defined by a designer.

[0045] The present invention does not limit the specific shape of the groove 122. For example, the shape of the groove 122 can be as follows: Figure 2 The semicircle shown can also be Figure 3 The zigzag shape shown can also be a square, a trapezoid, a pit or other shapes. Specifically, the pit can refer to a small and dot-shaped pit set at the bottom of the support structure 120.

[0046] In the present invention, the size of the groove 122 can be determined by the designer based on the size of the package substrate and process requirements.

[0047] Optionally, the length of the groove 122 may range from 10 μm to 100 μm, and the depth of the groove 122 may range from 10 μm to 100 μm. That is, the length of the groove 122 may be any value between 10 μm and 100 μm, for example, the length of the groove 122 may be 10 μm, 20 μm, 60 μm, 80 μm or 100 μm, etc.; the depth of the groove 122 may also be any value between 10 μm and 100 μm, for example, the depth of the groove 122 may be 10 μm, 30 μm, 50 μm, 60 μm, 80 μm or 100 μm, etc.

[0048] Specifically, Figure 2 As shown, the length of the groove 122 may refer to the maximum length of the groove 122 in the horizontal direction, and the depth of the groove 122 may refer to the maximum length of the groove 122 in the vertical direction.

[0049] In this embodiment, the length and depth of the groove 122 are limited to between 10 μm and 100 μm, which can further reduce the risk of the cover falling off. Moreover, limiting the length and depth of the groove 122 to between 10 μm and 100 μm can also provide a better filling space for the insulating glue, enhance the anchoring effect of the insulating glue, effectively disperse the stress, and avoid stress concentration on the bonding interface between the insulating glue and the heat dissipation cover or the packaging substrate, thereby reducing the possibility of glue bonding failure and reducing the risk of the cover falling off.

[0050] The present invention also provides a chip packaging structure, such as Figure 4 and Figure 5 As shown, the chip packaging structure includes a packaging substrate 200, a semiconductor chip 300 and a heat dissipation cover 100 provided in any of the above embodiments.

[0051] Among them, Figure 4 and Figure 5 As shown, the active surface of the semiconductor chip 300 is disposed on the packaging substrate 200 , the heat dissipation cover 100 is disposed on the packaging substrate 200 , and the heat dissipation cover 100 is covered on the semiconductor chip 300 .

[0052] Specifically, solder joints are arranged on the active surface of the semiconductor chip 300 , and the semiconductor chip 300 is fixed on the packaging substrate 200 through the solder joints, and is electrically connected to the packaging substrate 200 through the solder joints, so as to transmit the signals on the semiconductor chip 300 to the corresponding circuits on the packaging substrate 200 .

[0053] Exemplarily, the solder joint is a small spherical structure made of metal (tin-lead alloy or lead-free alloy, etc.), and the packaging substrate 200 can be a multi-layer printed circuit board (PCB). The packaging substrate 200 is not only used to provide physical support for the semiconductor chip and ensure the stable position of the semiconductor chip in the package, but also used to redistribute and transmit the signal transmitted from the semiconductor chip through the solder joint, and lead the signal to the pins (balls) outside the package.

[0054] Alternatively, if Figure 4 and Figure 5 As shown, the support structure 120 of the heat dissipation cover 100 can be fixed on the packaging substrate 200 by means of an insulating adhesive 400 .

[0055] Exemplarily, the insulating adhesive may be epoxy resin-based insulating adhesive, silicone rubber-based insulating adhesive, polyimide insulating adhesive, or the like.

[0056] Epoxy resin-based insulating adhesive includes epoxy resin, curing agent and filler. Epoxy resin has good adhesion, chemical stability and mechanical properties. Curing agent is used to make epoxy resin undergo cross-linking reaction, transform from liquid to solid, and form a three-dimensional network structure, so as to achieve good bonding and fixing effect. Filler can be used to adjust the thermal conductivity, expansion coefficient and other properties of insulating adhesive. Silicone rubber-based insulating adhesive includes silicone rubber, cross-linking agent and filler. Silicone rubber has good flexibility and high and low temperature resistance. Cross-linking agent is used to make silicone rubber molecular chains undergo cross-linking reaction to form an elastic network structure. Filler can change the hardness, strength and thermal conductivity of insulating adhesive. Polyimide insulating adhesive is made of polyimide resin as the main material.

[0057] For example, Figure 4 and Figure 5 As shown, the cover body 110 of the heat dissipation cover 100 and the surface of the semiconductor chip 300 on one side away from the packaging substrate 200 are fixedly connected by a heat dissipation adhesive 500 .

[0058] Specifically, the heat dissipation adhesive is filled in the gap between the heat dissipation cover 100 and the semiconductor chip 300 to effectively transfer the heat generated by the semiconductor chip 300 to the heat dissipation cover 100, while providing certain bonding and sealing functions to ensure that the heat dissipation cover 100 can stably perform the heat dissipation function and ensure that the internal structure is not affected by external environmental factors.

[0059] Exemplarily, the heat dissipation adhesive may be thermal grease, thermal gel or thermal adhesive, etc.

[0060] In some embodiments, a plurality of solder balls (such as tin balls) are arranged in an array on a side surface of the package substrate 200 away from the semiconductor chip 300. Specifically, a plurality of tin balls form a ball grid array and are distributed on the bottom of the package substrate 200, which is used to connect the packaged semiconductor chip 300 to an external circuit board, and the semiconductor chip can communicate and work in coordination with other components by soldering the solder balls at the bottom of the package to the pads of the external circuit board.

[0061] The present invention also provides a chip packaging method, which includes but is not limited to steps S101 to S105:

[0062] S101, providing a packaging substrate, a semiconductor chip and a heat dissipation cover.

[0063] The packaging substrate may be a printed circuit board, the semiconductor chip may be a CPU, a GPU or a memory chip, etc., and the heat dissipation cover may be the heat dissipation cover 100 provided in any of the above embodiments.

[0064] S102, soldering and fixing the active surface of the semiconductor chip onto a side surface of the packaging substrate.

[0065] Specifically, solder joints are made on the pads on the active surface of the semiconductor chip, flux is applied to the position of the package substrate where the semiconductor chip needs to be soldered, the active surface of the semiconductor chip with the solder joints is facing downward, and the semiconductor chip is accurately placed on the package substrate through high-precision alignment equipment, so that the solder joints on the semiconductor chip correspond to the pads on the package substrate one by one. Then, the entire assembly is passed through a reflow soldering device to melt the solder joints at high temperature and form a metallurgical bond with the pads on the package substrate, thereby achieving electrical connection and mechanical fixation between the semiconductor chip and the package substrate.

[0066] S103, coating insulating glue on the edge of the packaging substrate.

[0067] Specifically, Figure 6 As shown, after the semiconductor chip is fixed on the package substrate, the insulating glue can be applied to the edge of the package substrate by 3D printing process (glue dispenser 600). In other embodiments, the insulating glue can also be applied to the edge of the package substrate by screen printing.

[0068] S104, coating heat dissipation adhesive on a surface of the semiconductor chip away from the packaging substrate.

[0069] Specifically, Figure 7 As shown, after insulating glue is coated on the edge of the packaging substrate, heat dissipation glue is coated on the surface of the semiconductor chip away from the packaging substrate by a glue dispenser or screen printing.

[0070] S105, attaching the support structure of the heat dissipation cover to the area of ​​the packaging substrate coated with the insulating glue, and performing a curing process to fix the heat dissipation cover on the packaging substrate.

[0071] Specifically, when obtaining Figure 7 After the structure shown, Figure 8 and Fig. 9 As shown, the support structure 120 of the heat dissipation cover 100 is mounted on the area of ​​the package substrate 200 coated with the insulating glue, and then the assembly is placed in an oven for quick curing (Snap Cure) to fix the heat dissipation cover 100 on the package substrate 200 to obtain the following Figure 4 and Figure 5 The chip packaging structure shown.

[0072] Exemplarily, the curing temperature may range from 100° C. to 200° C. For example, the curing temperature may be 100° C., 120° C., 160° C., 180° C. or 200° C. The curing time may range from a few minutes to a few hours, and the specific parameters are determined based on the type of insulating adhesive and the coating thickness.

[0073] In some embodiments, the insulating adhesive may be a light-curing insulating adhesive, in which case the insulating adhesive is cured by irradiation under ultraviolet light or visible light.

[0074] An embodiment of the present invention further provides a computer device having the above chip packaging structure.

[0075] The computer device may include: one or more processors, memory, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The processor and memory may be packaged in the above-mentioned chip packaging structure.

[0076] The various components are connected to each other using different buses for communication, and can be mounted on a common motherboard or in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface).

[0077] In some optional embodiments, if desired, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system).

[0078] The processor may be a central processing unit, a network processor or a combination thereof. The processor may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0079] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0080] The memory may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid state drive; the memory may also include a combination of the above types of memory.

[0081] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0082] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0083] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0084] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0085] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the present invention.

Claims

1. A heat dissipation cover, characterized in that: Applied to a chip packaging structure, the heat dissipation cover comprises a cover body and a support structure connected to the cover body, and the support structure has an accommodation space for accommodating a semiconductor chip; The end of the support structure away from the cover body is used to connect with the packaging substrate, the end of the support structure away from the cover body is provided with a groove, and / or the surface roughness of the end of the support structure away from the cover body is greater than the surface roughness of the end of the support structure close to the cover body.

2. The heat dissipation cover according to claim 1, characterized in that: The length of the groove ranges from 10 μm to 100 μm, and the depth of the groove ranges from 10 μm to 100 μm.

3. The heat dissipation cover according to claim 1, characterized in that: The groove is semicircular, or the groove is serrated, or the groove is pitted.

4. The heat dissipation cover according to any one of claims 1 to 3, characterized in that: There are multiple grooves, and the multiple grooves are arranged at intervals along the length direction of the support structure.

5. A chip packaging structure, characterized in that: The chip packaging structure comprises a packaging substrate, a semiconductor chip and a heat dissipation cover as claimed in any one of claims 1 to 4; The active surface of the semiconductor chip is arranged on the packaging substrate, the heat dissipation cover is arranged on the packaging substrate, and the heat dissipation cover is arranged on the semiconductor chip.

6. The chip packaging structure according to claim 5, characterized in that: The support structure of the heat dissipation cover is fixed on the packaging substrate by means of insulating glue.

7. The chip packaging structure according to claim 6, characterized in that: The insulating adhesive is epoxy resin-based insulating adhesive, silicone rubber-based insulating adhesive or polyimide insulating adhesive.

8. The chip packaging structure according to claim 5, characterized in that: The cover body of the heat dissipation cover and a surface of the semiconductor chip on one side away from the packaging substrate are fixedly connected by heat dissipation adhesive.

9. A chip packaging method, characterized in that: The chip packaging method comprises: Providing a packaging substrate, a semiconductor chip and a heat dissipation cover as claimed in any one of claims 1 to 4; Soldering and fixing the active surface of the semiconductor chip to a side surface of the packaging substrate; Applying insulating glue on the edge of the packaging substrate; Coating heat dissipation glue on a surface of the semiconductor chip away from the packaging substrate; The support structure of the heat dissipation cover is mounted on the area of ​​the packaging substrate coated with the insulating glue, and a curing treatment is performed to fix the heat dissipation cover on the packaging substrate.

10. The chip packaging method according to claim 9, characterized in that: The curing temperature ranges from 100°C to 200°C.

Images