Silicon through hole test structure, test method and preparation method thereof
By designing multiple test areas with different depths in the through-silicon test structure and setting probes between the test pads and the test areas, the problem of the inability to accurately locate the leakage current depth and position in the through-silicon structure in the prior art is solved, and efficient leakage current positioning and monitoring are achieved.
Patent Information
- Application Number
- CN202311310361.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-10
- Publication Date
- 2025-04-11
AI Technical Summary
The prior art is unable to accurately locate the specific depth and location of leakage current in the through-silicon structure, resulting in a degradation of chip performance.
Design a through-silicon test structure, including a semiconductor substrate, a through-silicon structure, a test pad and multiple test areas. The test area is distributed radially on the outside of the through-silicon structure with different depths. Real-time sampling and positioning of leakage current is achieved by setting probes between the test pad and the test area.
The precise positioning of the depth and position of leakage current in the through-silicon structure is achieved, which avoids the back of the wafer, simplifies the test process, and can monitor the leakage of the entire wafer surface.
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Figure CN119812163A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor testing technology, and in particular to a through silicon via testing structure, a testing method and a preparation method thereof. Background Art
[0002] With the rapid development of semiconductor devices and integrated circuit technology, the size and process line width of chip components are constantly shrinking, and their integration is also constantly improving in accordance with Moore's Law. Therefore, three-dimensional integrated circuits and related three-dimensional interconnection and packaging technologies have emerged in recent years. Among them, three-dimensional integration technology with through silicon via (TSV) as the core is the research and development hotspot of the current semiconductor industry. With the development of through silicon via technology, more and more products use high-density and high aspect ratio TSV through holes. The conventional through silicon via structure is a Cu-Si composite structure filled with electroplated copper, which has a multi-layer interface (Cu / Ta / SiO2 / Si). The thermal expansion coefficients of Cu and Si differ by 6 times. Due to the significant difference in the thermal expansion coefficients of the materials constituting the interfaces of each layer, thermal mismatch will cause large tensile stress and shear stress between the materials of each layer of the through silicon via interface, which is easy to induce interface stratification and cause leakage of the through silicon via structure, thereby reducing the performance of the chip.
[0003] In the prior art, the location of the leakage current in the TSV structure is usually located by the hotspot failure location analysis method, that is, a test voltage is applied between the TSV structure and the substrate. After the test voltage is applied, a hotspot is generated at the location where the leakage current occurs. The hotspot can be found by the tester and stored through a hotspot map. However, the above method can only test the hotspot on the front of the chip, and cannot locate the specific location of the hotspot, nor can it locate the depth of the hotspot in the TSV structure, and it is even more impossible to perform PFA analysis.
[0004] Therefore, how to find a practical and effective method to accurately obtain the specific depth position of the leakage current in the silicon via structure has become a technical problem that needs to be solved urgently in this field. Summary of the invention
[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a through silicon via test structure, a test method and a preparation method thereof, so as to solve the problem that the through silicon via structure in the prior art cannot accurately locate the depth and position of the leakage current and the resulting reduction in chip performance.
[0006] In order to achieve the above-mentioned object and other related objects, the present invention provides a through silicon via test structure, wherein the through silicon via test structure comprises:
[0007] A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface arranged opposite to each other, an interlayer dielectric layer is arranged on the first surface, and the semiconductor substrate has through holes arranged in a circumferential direction;
[0008] A through silicon via structure, wherein the through silicon via structure is formed in the through hole;
[0009] A test pad, wherein the test pad covers at least two of the through silicon via structures;
[0010] A test area has different depths and exposes the first surface, and the test area is radially distributed outside the through silicon via structure.
[0011] Optionally, there are multiple test areas, and the distance between each test area and the through silicon via structure gradually increases along the radial direction.
[0012] Optionally, the width of each of the test areas is 80-100 μm and the depth of each of the test areas is 20%-100% of the depth of the through silicon via structure.
[0013] Optionally, the plurality of test areas are distributed in a stepped manner and the depth of each test area increases in equal proportion along the radial direction.
[0014] Optionally, the depth difference between two adjacent test areas is 10-30 μm.
[0015] Optionally, the interior of the through silicon via structure is filled with an insulating layer, a barrier layer and a metal column in sequence, the metal column and the test pad have the same material and the metal column and the test pad are electrically connected.
[0016] Optionally, the metal column and the test pad are both formed of metal copper.
[0017] The present invention also provides a method for preparing a through silicon via test structure, the preparation method comprising the following steps:
[0018] A semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface arranged opposite to each other, an interlayer dielectric layer is formed on the first surface, the interlayer dielectric layer serves as an etching barrier layer, and an etching process is used to form through holes arranged in a circumferential direction in the semiconductor substrate;
[0019] Filling the through hole with an insulating layer, a barrier layer and a metal column in sequence, and performing a CMP process on the metal column to form a through silicon via structure;
[0020] Depositing a dielectric layer on the semiconductor substrate, and etching the dielectric layer again to form a groove on the metal column, and filling the groove with metal to form a test pad, wherein the test pad covers at least two of the through silicon via structures;
[0021] Fixing the etching knife, setting a first etching depth, and rotating the semiconductor substrate to form a first test area outside the through silicon via structure;
[0022] After etching is completed, a plurality of different etching depths are set and the etching knife is moved radially along the through silicon via structure, and the semiconductor substrate is rotated to form a plurality of test areas distributed in a stepped manner outside the through silicon via structure.
[0023] The present invention also provides a method for testing a through silicon via test structure, the method comprising the following steps:
[0024] Providing any of the through silicon via test structures described above;
[0025] A probe is arranged between the test pad and the test area, and the test pad, the test area and the probe are connected by a metal interconnection line;
[0026] Each time, one of the test areas is grounded and a forward voltage is applied to the test pad. Since the test pad corresponds to a plurality of test areas with different depths, leakage current values of areas with different depths of the through silicon via structure can be sampled in real time.
[0027] The leakage current value obtained in real time is compared with the preset reference leakage current value. When the leakage current value is significantly larger than the nA level, it can be determined that leakage occurs at the depth of the through silicon via structure corresponding to the test area.
[0028] Optionally, the forward voltage applied to the test pad is not greater than 10V.
[0029] Optionally, the preset reference leakage current is a leakage current when no hot spot is generated in the through silicon via structure.
[0030] As described above, the silicon via test structure, test method and preparation method thereof of the present invention have the following beneficial effects: the present invention forms test areas with different depths and stepped distribution on both sides of the test pad, and sets a probe between the test pad and the test area, so that there is no need to grind the back side of the wafer during testing, and convenient testing of the leakage area can be achieved. Moreover, since the test area has different depths, the leakage current values of the areas with different depths of the silicon via structure can be sampled in real time and compared with the preset reference leakage current values for analysis, so as to accurately locate the depth and position of the leakage current of the silicon via structure, and can also monitor the leakage of the entire wafer. In addition, the preparation method of the silicon via test structure of the present invention is simple, and the metal column matrix in the silicon via under the test pad can be freely set, so that it can be applied to silicon via structures of different sizes, so as to monitor and locate the leakage positions of different depths. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 It is a schematic cross-sectional structure diagram of a through silicon via test structure of the present invention.
[0032] Figure 2 It is a schematic diagram showing the steps of the method for preparing a through silicon via test structure of the present invention.
[0033] Figures 3 to 8 Shown are structural schematic diagrams corresponding to each step of the method for preparing a through silicon via test structure.
[0034] Fig. 9 It is a schematic diagram showing the steps of the through silicon via test structure testing method of the present invention.
[0035] Fig.10 It is a schematic structural diagram of the through silicon via test structure of the present invention when conducting a leakage test.
[0036] Component number description
[0037] 101, semiconductor substrate; 1011, through hole; 102, interlayer dielectric layer; 103, through silicon via structure; 1031, insulating layer; 1032, barrier layer; 1033, metal pillar; 104, dielectric layer; 105, test pad; 106, first test area; 107, second test area; S1~S5 and S20~S23, steps. DETAILED DESCRIPTION
[0038] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0039] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.
[0040] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0041] See also Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0042] Embodiment 1
[0043] In conventional technology, a test voltage is generally applied between the TSV structure 103 and the semiconductor substrate 101, which then generates a hot spot at the location where the leakage current occurs. The hot spot is discovered by a tester and a hot spot map is stored. However, it can only test the hot spot on the front of the chip, and cannot locate the specific location of the hot spot, nor the depth of the hot spot in the TSV structure 103, which results in the problem that the conventional TSV test structure cannot accurately locate the leakage current location.
[0044] It should be noted that, for the sake of convenience of description, the present invention uses through hole 1011 to describe this type of device structure of "vertical conduction between chips and between wafers to achieve interconnection between chips", but those skilled in the art should know that the material of the structure of the present invention is not limited to silicon wafers, and the shape and doping conditions of the through hole 1011 are not limited; any other device with the structure and function of through hole 1011, such as germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), gallium nitride (GaN), graphene materials, etc., can also use this structure to test its leakage current.
[0045] In this embodiment, a through silicon via test structure is provided, such as Figure 1 As shown, it is a schematic diagram of the cross-sectional structure of a through silicon via test structure, wherein the through silicon via test structure includes a semiconductor substrate 101, an interlayer dielectric layer 102 located on the surface of the semiconductor substrate 101, a through silicon via structure 103 located in the semiconductor substrate 101 and the interlayer dielectric layer 102, a test pad 105 located on the through silicon via structure 103, and a plurality of test areas arranged around the test pad 105.
[0046] Specifically, Figure 1 As shown, in this embodiment, the semiconductor substrate 101 can be one of a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate and a nitride substrate. The material of the interlayer dielectric layer 102 is silicon oxide or a low-K dielectric material.
[0047] Specifically, Figure 1As shown, the through hole 1011 is located in the interlayer dielectric layer 102 and the semiconductor substrate 101, wherein the through hole 1011 may penetrate the semiconductor substrate 101 and the interlayer dielectric layer 102, or may not penetrate the semiconductor substrate 101 and the interlayer dielectric layer 102, and the through hole 1011 has a high depth-to-width ratio, for example, a depth-to-width ratio of 10:1, and then the through hole 1011 is filled with an insulating layer 1031, a barrier layer 1032 and a metal column 1033 in sequence to form a through silicon via structure 103, wherein the insulating layer 1031 is located on the side wall and the bottom wall of the through hole 1011, and the insulating layer 1031 is used to electrically isolate the metal column 1033 in the through hole 1011 from the semiconductor substrate 101, so as to avoid subsequent use of the through hole 1011 structure for In order to prevent leakage or short circuit during electrical connection, a barrier layer 1032 may be formed between the insulating layer 1031 and the metal pillar 1033. The barrier layer 1032 may prevent the conductive material forming the metal pillar 1033 from diffusing into the insulating layer 1031 to affect the insulating performance of the insulating layer 1031, and may also serve as a bonding layer between the conductive material forming the metal pillar 1033 and the insulating layer 1031, thereby preventing the metal pillar 1033 from peeling off from the insulating layer 1031. After the barrier layer 1032 is formed, the conductive material is continuously filled into the through hole 1011 to form the conductive metal pillar 1033. After the conductive material is filled to form the conductive metal pillar 1033, a CMP planarization process may be performed to obtain a flat surface. Preferably, in this embodiment, the metal pillar 1033 is a metal copper pillar formed of a conductive material copper.
[0048] like Figure 1 As shown, in this embodiment, a test pad 105 is formed on the metal pillar 1033 after CMP planarization, wherein the test pad 105 covers at least two through silicon via structures 103, and the width of the test pad 105 is greater than the width of at least two metal pillars 1033, thereby facilitating the convenience of subsequent testing. In addition, the test pad 105 is also formed of a conductive material copper and the test pad 105 is electrically connected to the metal pillar 1033.
[0049] like Figure 1 As shown, in this embodiment, test regions are distributed on both sides of the test pad 105 . The test regions are distributed radially outside the test pad 105 and have different depths and expose the semiconductor substrate 101 .
[0050] As an example, there are multiple test areas, and the distance between each test area and the through silicon via structure 103 gradually increases along the radial direction.
[0051] Specifically, Figure 1As shown, multiple test areas are distributed on both sides of the test pad 105, and the distance between each test area and the through silicon via structure 103 gradually increases radially outward, and the width of each test area is 80 to 100 μm, for example, 80 μm, 90 μm or 100 μm. In order to accurately locate the leakage current position in different areas and at different depths, the depth of each test area is distributed in 20% to 100% of the depth of the through silicon via structure 103. For example, the depth of the test area closest to the through silicon via structure 103 is 20% of the metal column 1033, and the depth of the test area farthest from the through silicon via structure 103 is equal to the depth of the metal column 1033, that is, the depth of the test area farthest from the through silicon via structure 103 is 100% of the metal column 1033. Preferably, the multiple test areas are distributed in a stepped manner and the depth of each test area increases in equal proportion along the radial direction. In this embodiment, the number of test areas is five, and the five test areas are distributed in a stepped manner on both sides of the test pad 105 in sequence. The depths of the five test areas are 20%, 40%, 60%, 80% and 100% of the depth of the metal column 1033 in sequence, so that when the metal column 1033 is subsequently tested for leakage current, the leakage current positions of different areas and different depths can be accurately located. Of course, in other embodiments, the number and depth of the test areas can be set as needed, and are not limited here.
[0052] As an example, the depth difference between two adjacent test areas is 10-30 μm.
[0053] Specifically, Figure 1 As shown, the depth difference between two adjacent test areas is 10-30 μm, for example, 10 μm, 20 μm or 30 μm. Of course, in other embodiments, the depth difference between two adjacent test areas can be set as needed and is not limited here.
[0054] In this embodiment, test areas with different depths and stepped distribution are formed on both sides of the test pad 105, so that there is no need to grind the back side of the wafer when testing the leakage current. A probe can be directly set between the test pad 105 and the test area to achieve convenient testing of the leakage area. Since the test area has different depths, the leakage current values of the metal pillars 1033 in the through silicon via structure 103 at different depths and in different areas can be sampled in real time and compared with the preset reference leakage current values for analysis, thereby achieving accurate positioning of the depth and position of the leakage current in the through silicon via structure 103, and also enabling monitoring of the leakage situation of the entire wafer surface.
[0055] Embodiment 2
[0056] like Figure 2As shown, an embodiment of the present invention provides a method for preparing a through silicon via test structure, and the preparation method comprises the following steps S1 to S5:
[0057] S1: providing a semiconductor substrate 101, wherein the semiconductor substrate 101 has a first surface and a second surface arranged opposite to each other, forming an interlayer dielectric layer 102 on the first surface, wherein the interlayer dielectric layer 102 serves as an etching stop layer 1032, and forming through holes 1011 arranged in a circumferential direction in the semiconductor substrate 101 by an etching process;
[0058] S2: filling the through hole 1011 with an insulating layer 1031 , a barrier layer 1032 and a metal pillar 1033 in sequence, and performing a CMP process on the metal pillar 1033 to form a through silicon via structure 103 ;
[0059] S3: depositing a dielectric layer 104 on the semiconductor substrate 101, and etching the dielectric layer 102 again to form a groove on the metal pillar 1033, and filling the groove with metal to form a test pad 105, wherein the test pad 105 covers at least two of the through silicon via structures 103;
[0060] S4: fixing the etching knife, setting a first etching depth, and rotating the semiconductor substrate 101 to form a first test area 106 outside the through silicon via structure 103;
[0061] S5: After the etching is completed, a plurality of different etching depths are set and the etching knife is moved along the radial direction of the TSV structure 103 , and the semiconductor substrate 101 is rotated to form a plurality of test areas distributed in a stepped manner on the outer side of the TSV structure 103 .
[0062] The following combination Figures 3 to 8 , the technical scheme and technical effects of the embodiments of the present invention are described in detail.
[0063] First, see Figure 2 and Figure 3 and Figure 4 , perform step S1, provide a semiconductor substrate 101, the semiconductor substrate 101 has a first surface and a second surface arranged opposite to each other, form an interlayer dielectric layer 102 on the first surface, the interlayer dielectric layer 102 serves as an etching stop layer 1032, and adopt an etching process to form through holes 1011 arranged along the circumferential direction in the semiconductor substrate 101.
[0064] Specifically, Figure 3As shown, the semiconductor substrate 101 may be one of a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate and a nitride substrate. The material of the interlayer dielectric layer 102 is silicon oxide or a low-K dielectric material, and the structure of the interlayer dielectric layer 102 may also be a single layer or a multilayer. In this embodiment, the interlayer dielectric layer 102 may be used as an etching stop layer and may be used as an isolation structure between adjacent through holes 1011. In fact, during the preparation process, the interlayer dielectric layer 102 may include a silicon nitride layer, a silicon oxide layer and a silicon oxynitride layer stacked on the semiconductor substrate 101 from bottom to top, wherein the silicon oxynitride layer may play a good anti-reflection role when performing photolithography to form the through hole 1011 corresponding to the deposited conductive material, but the material and structure of the interlayer dielectric layer 102 are not limited thereto.
[0065] Specifically, Figure 4 As shown, the interlayer dielectric layer is used as a photolithography mask to etch the interlayer dielectric layer and the semiconductor substrate by photolithography until the first surface of the semiconductor substrate 101 is exposed to form a through hole 1011 with a high aspect ratio. For example, the aspect ratio of the through hole 1011 is 10:1.
[0066] Next, see Figure 2 and Figure 5 , perform step S2, fill the insulating layer 1031, the barrier layer 1032 and the metal column 1033 in the through hole 1011 in sequence, perform a CMP process on the metal column 1033, and form a through silicon via structure 103.
[0067] Specifically, Figure 5As shown, an insulating layer 1031 , a barrier layer 1032 and a metal pillar 1033 are sequentially deposited in the through hole 1011 , and a CMP process is performed on the metal pillar 1033 , thereby forming a through silicon via structure 103 . Among them, the insulating layer 1031 is located on the side walls and bottom walls of the through hole 1011. The insulating layer 1031 is used to electrically isolate the metal column 1033 in the through hole 1011 from the semiconductor substrate 101 to avoid leakage or short circuit when the silicon through hole structure 103 is used for electrical connection later. A barrier layer 1032 can also be formed between the insulating layer 1031 and the metal column 1033. The barrier layer 1032 can prevent the conductive material forming the metal column 1033 from diffusing into the insulating layer 1031 to affect the insulating performance of the insulating layer 1031, and can also serve as a bonding layer between the conductive material forming the metal column 1033 and the insulating layer 1031, thereby preventing the metal column 1033 from peeling off from the insulating layer 1031. After the barrier layer 1032 is formed, the conductive material is continuously filled in the through hole 1011 to form a conductive metal column 1033. After the conductive material is filled to form the conductive metal column 1033, a CMP planarization process can be performed to obtain a flat surface. After forming the through silicon via structure 103 , the step of removing part of the interlayer dielectric layer 102 is also included.
[0068] Next, see Figure 2 and Figure 6 , execute step S3, deposit a dielectric layer 102 on the semiconductor substrate 101, and etch the dielectric layer 102 again to form a groove on the metal column 1033, and fill the groove with metal to form a test pad 105, wherein the test pad 105 covers at least two of the through silicon via structures 103.
[0069] like Figure 6 As shown, a dielectric layer 104 is continuously deposited on the semiconductor substrate 101 and the through silicon via structure 103. The material of the dielectric layer 104 is silicon oxide or a low-K dielectric material. The structure of the dielectric layer 104 can also be a single layer or a multilayer. The thickness of the dielectric layer 104 is generally 2 μm, and is greater than the thickness of the interlayer dielectric layer 102. The dielectric layer 104 is etched again using a Damascus process. The etching width must at least cover two through silicon via structures 103, thereby forming a groove on the through silicon via structure 103. A conductive metal is filled in the groove and a planarization process is performed to form a test pad 105. The test pad 105 covers at least two through silicon via structures 103, so that the width of the test pad 105 is greater than the width of at least two metal pillars 1033, which is convenient for improving the convenience of subsequent testing. After the test pad 105 is formed, the dielectric layer 104 on the area other than the test pad 105 is removed by etching to expose the first surface of the semiconductor substrate 101.
[0070] See also Figure 2 and Figure 7 , proceed to step S4 , fix the etching knife, set a first etching depth, and rotate the semiconductor substrate 101 to form a first test area 106 outside the through silicon via structure 103 .
[0071] Specifically, Figure 7 As shown, the etching knife is fixed, and the first etching depth is set, and the semiconductor substrate 101 is fixed and rotated. At this time, since the etching knife is fixed, the first test area 106 can be formed on both sides of the outside of the test pad 105.
[0072] See also Figure 2 and Figure 7 , execute step S5, after the etching is completed, set a plurality of different etching depths and move the etching knife along the radial direction of the through silicon via structure 103, rotate the semiconductor substrate 101 to form a plurality of test areas distributed in a stepped manner on the outside of the through silicon via structure 103.
[0073] Specifically, Figure 8 As shown, after the first test area 106 is etched, the engraving knife is moved again along the radial direction of the through silicon via structure 103 to adjust the engraving knife position, set the second etching depth, and continue to rotate the semiconductor substrate 101 to form a second test area 107 on both sides of the outside of the test pad 105. Then, the above steps are repeated to set multiple different etching depths until multiple test areas distributed in a stepped manner are formed on both sides of the outside of the test pad 105.
[0074] Preferably, the multiple test areas are distributed in a stepped manner and the depth of each test area increases in equal proportion along the radial direction. In this embodiment, the number of test areas is five, and the five test areas are distributed in a stepped manner on both sides of the test pad 105 in sequence. The depths of the five test areas are 20%, 40%, 60%, 80% and 100% of the depth of the metal column 1033 in sequence, so that when the metal column 1033 is subsequently tested for leakage current, the leakage current positions of different areas and different depths can be accurately located. Of course, in other embodiments, the number and depth of the test areas can be set as needed, and are not limited here.
[0075] The preparation method of the through silicon via test structure in the embodiment of the present invention is simple, and the test areas of different depths can be formed by adjusting the position of the engraving knife and setting the etching depth. Since each test area can correspond to a metal pillar 1033 of different depths, when the metal pillar 1033 is subsequently subjected to a leakage current test, the leakage current position of different areas and different depths can be accurately located. The preparation method of the through silicon via test structure in this embodiment can be applied to through silicon via structures 103 of different sizes, thereby realizing the monitoring and positioning of the leakage current position of different depths and different areas.
[0076] Embodiment 3
[0077] like Fig. 9 As shown, it is a flow chart of a method for testing a through silicon via test structure according to an embodiment of the present invention, and the testing method includes the following steps S20 to S23:
[0078] S20: providing any one of the through silicon via test structures as described above;
[0079] S21: a probe is arranged between the test pad 105 and the test area, and the test pad 105, the test area and the probe are connected by metal interconnection wires;
[0080] S22: grounding one of the test areas each time and applying a forward voltage to the test pad 105. Since the test pad 105 corresponds to a plurality of test areas with different depths, leakage current values of areas with different depths of the through silicon via structure 103 can be sampled in real time.
[0081] S23: Compare the leakage current value obtained in real time with the preset reference leakage current value. When the leakage current value is significantly larger than the nA level, it can be determined that leakage occurs at the depth of the through silicon via structure 103 corresponding to the test area.
[0082] The through silicon via test structure described in any of the above embodiments is placed on a test bench. Specifically, the through silicon via test structure in this embodiment is tested using a conventional WAT two-terminal method, a probe is set between the test pad 105 and the test area, and a metal interconnection line is set between the test pad 105, the test area and the probe, so that the test pad 105, the test area and the probe are electrically connected, such as Fig.10 As shown, it shows the structure of the silicon via test structure of the present invention when the leakage test is performed. When each test is performed, one of the test areas is grounded and a forward voltage is applied to one end of the test pad 105, so that the leakage current values of different areas of the silicon via structure 103 at the depth corresponding to the test area where the forward voltage is applied can be sampled in real time. Since there are multiple test areas with different depths, the leakage current values of areas at different depths of the silicon via structure 103 can be sampled in real time, and then the leakage current value obtained in real time is compared with the value of a preset reference leakage current. The preset reference leakage current is the leakage current when no hot spot is generated in the silicon via structure 103. When the leakage current value appears to be a current of the order of nA that is significantly larger, it can be determined that leakage has occurred at the depth of the silicon via structure 103 corresponding to the test area.
[0083] As an example, the forward voltage value applied to the test pad 105 is not greater than 10V.
[0084] Specifically, in order to prevent the TSV structure 103 from being broken down, in this embodiment, the forward voltage applied to the test pad 105 is not greater than 10V, for example, it can be 9V, 6V or 3V, etc., which is not limited here.
[0085] The test method of the through silicon via test structure of the embodiment of the present invention is simple to set up, and the leakage current position at different depths and different areas in the chip can be accurately obtained by this method, thereby effectively improving the subsequent physical failure analysis method and process.
[0086] In summary, the silicon through hole test structure, test method and preparation method of the present invention, by forming test areas with different depths and stepped distribution on both sides of the test pad, a probe is set between the test pad and the test area, so that there is no need to grind the back of the wafer during testing, and convenient testing of the leakage area can be achieved. Since the test area has different depths, the leakage current values of the areas with different depths of the silicon through hole structure can be sampled in real time and compared with the preset reference leakage current values, so as to accurately locate the depth and position of the leakage current of the silicon through hole structure, and can also monitor the leakage of the entire surface of the wafer. In addition, the preparation method of the silicon through hole test structure in the present invention is simple, and the metal column matrix in the silicon through hole under the test pad can be freely set, so that it can be applied to silicon through hole structures of different sizes, so as to monitor and locate the leakage positions of different depths. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.
[0087] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A through silicon via test structure, characterized in that: The through silicon via test structure comprises: A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface arranged opposite to each other, an interlayer dielectric layer is arranged on the first surface, and the semiconductor substrate has through holes arranged in a circumferential direction; A through silicon via structure, wherein the through silicon via structure is formed in the through hole; A test pad, wherein the test pad covers at least two of the through silicon via structures; A test area has different depths and exposes the first surface, and the test area is radially distributed outside the through silicon via structure.
2. The through silicon via test structure according to claim 1, characterized in that: There are multiple test areas, and the distance between each test area and the through silicon via structure gradually increases along the radial direction.
3. The through silicon via test structure according to claim 1, characterized in that: The width of each of the test areas is 80-100 μm and the depth of each of the test areas is 20%-100% of the depth of the through silicon via structure.
4. The through silicon via test structure according to claim 3, characterized in that: The plurality of test areas are distributed in a stepped manner and the depth of each test area increases in equal proportion along the radial direction.
5. The through silicon via test structure according to claim 1, characterized in that: The depth difference between two adjacent test areas is 10-30 μm.
6. The through silicon via test structure according to claim 1, characterized in that: The interior of the through silicon via structure is filled with an insulating layer, a barrier layer and a metal column in sequence. The metal column and the test pad have the same material and are electrically connected to each other.
7. The through silicon via test structure according to claim 6, characterized in that: The metal column and the test pad are both formed of metal copper.
8. A method for preparing a through silicon via test structure, characterized in that: The preparation method comprises the following steps: A semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface arranged opposite to each other, an interlayer dielectric layer is formed on the first surface, the interlayer dielectric layer serves as an etching barrier layer, and an etching process is used to form through holes arranged in a circumferential direction in the semiconductor substrate; Filling the through hole with an insulating layer, a barrier layer and a metal column in sequence, and performing a CMP process on the metal column to form a through silicon via structure; Depositing a dielectric layer on the semiconductor substrate, and etching the dielectric layer again to form a groove on the metal column, and filling the groove with metal to form a test pad, wherein the test pad covers at least two of the through silicon via structures; Fixing the etching knife, setting a first etching depth, and rotating the semiconductor substrate to form a first test area outside the through silicon via structure; After etching is completed, a plurality of different etching depths are set and the etching knife is moved radially along the through silicon via structure, and the semiconductor substrate is rotated to form a plurality of test areas distributed in a stepped manner outside the through silicon via structure.
9. A method for testing a through silicon via test structure, characterized in that: The test method comprises the following steps: Providing a through silicon via test structure as claimed in any one of claims 1 to 7; A probe is arranged between the test pad and the test area, and the test pad, the test area and the probe are connected by a metal interconnection line; Each time, one of the test areas is grounded and a forward voltage is applied to the test pad. Since the test pad corresponds to a plurality of test areas with different depths, leakage current values of areas with different depths of the through silicon via structure can be sampled in real time. The leakage current value obtained in real time is compared with the preset reference leakage current value. When the leakage current value is significantly larger than the nA level, it can be determined that leakage occurs at the depth of the through silicon via structure corresponding to the test area.
10. The testing method according to claim 9, characterized in that: The forward voltage value applied to the test pad is no greater than 10V.
11. The testing method according to claim 9, characterized in that: The preset reference leakage current is the leakage current when no hot spot is generated in the through silicon via structure.