Multi-chip interconnection structure and preparation method thereof

Abstract

The invention discloses a multi-chip interconnection structure and a preparation method thereof, and relates to the technical field of semiconductor structures, and the multi-chip interconnection structure specifically comprises an intermediate plate which is provided with an intermediate electromagnetic guide part; a short wire transmission plate and a first plate are sequentially stacked on one side of the middle plate, a short wire transmission channel is arranged on the short wire transmission plate, and a short wire electromagnetic guide part is arranged on the first plate; a long-line transmission plate and a second plate are sequentially stacked on the other side of the middle plate, the long-line transmission plate is provided with a long-line transmission channel, and the second plate is provided with a long-line electromagnetic guide part; the short wire transmission channel at least partially passes through the short wire guide channel between the middle electromagnetic guide part and the short wire electromagnetic guide part; the long-wire electromagnetic guide portion passes at least partially through the long-wire guide channel between the intermediate electromagnetic guide portion and the long-wire electromagnetic guide portion. According to the separated layout, mutual isolation between the short-line transmission channel and the long-line transmission channel is realized through a naturally formed electromagnetic isolation belt, and the influence on the layout of the transmission channels is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor structures, and in particular to a multi-chip interconnection structure and a preparation method thereof. Background Art

[0002] In the semiconductor field such as high-speed electronic devices, multi-chip interconnection is the key to achieving efficient signal transmission. As communication speed and bandwidth requirements continue to increase, how to design a semiconductor structure that can effectively support multi-channel signal transmission while maintaining signal integrity has become a key research and development direction for technicians in this field.

[0003] In existing technical solutions, in order to achieve high communication speed and high bandwidth signal transmission, surface or inner layer routing is usually used to transmit signals from one chip to another, and the integrity of signal transmission needs to be guaranteed as much as possible during design. However, when multi-channel signals are in parallel, mutual interference between signals becomes a major problem in the design, especially when the routing of multiple signal channels is too close, signal crosstalk will significantly affect the performance of the system, causing signal distortion and even communication errors. In order to alleviate these problems, technicians in this field usually use electromagnetic shielding or differential signal routing to reduce electromagnetic interference, but when dealing with multiple signal channels, a more complex shielding design is often required, resulting in a more bloated overall design.

[0004] More specifically, to address the electromagnetic interference problem of multiple signal channels, the following shielding design schemes are usually adopted: First, an isolation slot or shielding wall design is adopted, that is, a metallized through-hole array is set between adjacent signal channels to form a Faraday cage effect, but dense shielding through-holes will take up a lot of wiring space; second, a coaxial shielding structure is adopted to achieve 360° shielding of the conductor by surrounding the signal line, but this scheme requires complex process implementation and the design is relatively cumbersome.

[0005] Therefore, it is necessary to design a new substrate structure to solve the technical problem that the multi-chip interconnection structure in the prior art is difficult to prevent the mutual interference of multiple signal channels while maintaining a compact structure. Summary of the invention

[0006] The object of the present invention is to provide a multi-chip interconnect structure and a preparation method thereof, so as to solve the technical problem that the multi-chip interconnect structure in the prior art is difficult to reduce the mutual interference of multiple signal channels while maintaining a compact structure.

[0007] To achieve this object, the present invention adopts the following technical solutions: A multi-chip interconnection structure comprises an intermediate board, wherein the intermediate board is provided with an intermediate electromagnetic guide portion; A short-line transmission plate and a first plate are stacked in sequence on one side of the middle plate, the short-line transmission plate is provided with a short-line transmission channel, and the first plate is provided with a short-line electromagnetic guide; a long-line transmission plate and a second plate are stacked in sequence on the other side of the middle plate, the long-line transmission plate is provided with a long-line transmission channel, and the second plate is provided with a long-line electromagnetic guide; The short-line transmission channel is electrically connected between the two chips, and at least partially passes through the short-line guide channel between the intermediate electromagnetic guide part and the short-line electromagnetic guide part; the long-line electromagnetic guide part is electrically connected between the two chips, and at least partially passes through the long-line guide channel between the intermediate electromagnetic guide part and the long-line electromagnetic guide part.

[0008] Optionally, the short-line transmission channel includes a first short-line transmission portion, an intermediate short-line transmission portion, and a second short-line transmission portion that are electrically connected in sequence; the first short-line transmission portion and the second short-line transmission portion both extend from the surface of the first board to the short-line transmission board, and the intermediate short-line transmission portion is arranged on the short-line transmission board and passes through the short-line guide channel.

[0009] Optionally, the long-line transmission channel includes a first long-line transmission portion, an intermediate long-line transmission portion, and a second long-line transmission portion that are electrically connected in sequence; the first long-line transmission portion and the second long-line transmission portion both extend from the surface of the first plate to the long-line transmission plate, and the long-line transmission portion is arranged on the long-line transmission plate and passes through the long-line guide channel.

[0010] Optionally, the first long-line transmission portion includes a first conductive portion, a second conductive portion, and a third conductive portion that are electrically connected in sequence; the first conductive portion extends from the surface of the first plate to the second plate, the second conductive portion is disposed on the second plate, and the third conductive portion extends from the surface of the second plate to the long-line transmission plate; The second conductive portion is provided with a mounting groove, and an AC capacitor is electrically connected in the mounting groove.

[0011] Optionally, the middle electromagnetic guide portion, the short-line electromagnetic guide portion and the long-line electromagnetic guide portion are all copper foil layers.

[0012] Optionally, edges of the middle electromagnetic guide portion, the short-line electromagnetic guide portion and the long-line electromagnetic guide portion are sprayed with a gradient silver nanolayer, and a ferrite sheet is embedded in the middle electromagnetic guide portion.

[0013] Optionally, the short-line transmission channel is located between the first long-line transmission part and the second long-line transmission part; the first short-line transmission part is electrically connected to an inner pin of a chip, and the second short-line transmission part is electrically connected to an inner pin of another chip; the first long-line transmission part is electrically connected to an outer pin of a chip, and the second long-line transmission part is electrically connected to an outer pin of another chip.

[0014] A method for preparing a multi-chip interconnection structure, used for preparing the multi-chip interconnection structure as described above, comprising: Step S100, preparing a chip mounting plate, wherein the chip mounting plate comprises a first plate and a short-line transmission plate stacked on each other, wherein a short-line transmission channel is provided on the short-line transmission plate, and a short-line electromagnetic guide portion is provided on the first plate; Step S200, preparing a chip carrier, the chip carrier comprising a second plate, a long-line transmission plate and an intermediate plate stacked in sequence, the intermediate plate being provided with an intermediate electromagnetic guide, the long-line transmission plate being provided with a long-line transmission channel, and the second plate being provided with a long-line electromagnetic guide; Step S300, stacking the chip mounting board on the intermediate board, connecting the chip mounting board and the chip carrier board, and extending the long-line transmission channel to the first board; Step S400: electrically connecting two chips to a first board, wherein inner pins of the chips are electrically connected to the short-line transmission channel, and outer pins of the chips are electrically connected to the long-line transmission channel.

[0015] Optionally, the step S200 includes: Step S210, providing an intermediate plate with an intermediate electromagnetic guide portion, providing a long-line transmission plate with an intermediate long-line transmission portion, and providing a second plate with a long-line electromagnetic guide portion and a second conductive portion; Step S220, pressing and connecting the middle plate, the long-line transmission plate and the second plate to obtain a chip carrier plate; Step S230, drilling a hole inwardly on the surface of the second board to form a third hole extending from the surface of the second board to the long-line transmission board, and filling the third hole with a third conductive part, wherein the third conductive part is electrically connected to the intermediate long-line transmission part; The process of extending the long-line transmission channel to the first board includes: Step S311, drilling a hole inward on the surface of the second board to form a second hole penetrating the multi-chip interconnection structure, and filling the second hole with the first conductive part to electrically connect the first conductive part, the second conductive part and the third conductive part in sequence.

[0016] Optionally, after step S311, the method further includes: Step S312: etching the second conductive portion to form a mounting groove, and mounting an AC capacitor in the mounting groove.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The multi-chip interconnect structure and preparation method thereof provided by the present invention, wherein the middle electromagnetic guide part and the short-line electromagnetic guide parts and the long-line electromagnetic guide parts arranged in layers on both sides form a bidirectional electromagnetic guide structure, which reduces the dependence on the shielding layer and realizes signal isolation through the electromagnetic field directional coupling mechanism: when the electromagnetic wave of the short-line transmission channel propagates through the channel between the middle electromagnetic guide part and the short-line electromagnetic guide part, its electromagnetic field energy is constrained in the vertical stacking area formed by the first plate to the middle plate, while the electromagnetic wave of the long-line transmission channel is confined to the stacking space on the other side from the middle plate to the second plate. The separated layout realizes mutual isolation between the short-line transmission channel and the long-line transmission channel through the naturally formed electromagnetic isolation belt, reduces the layout influence on the transmission channel, and has a simpler design, which reduces the mutual interference of multiple signal channels while maintaining the overall structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention.

[0020] Figure 1 is a schematic structural diagram of a chip mounting board in an embodiment of the present invention; Figure 2 is a schematic structural diagram of a chip carrier board in an embodiment of the present invention; Figure 3 A first structural schematic diagram of a multi-chip interconnection structure provided by an embodiment of the present invention; Figure 4 A second structural schematic diagram of a multi-chip interconnection structure provided by an embodiment of the present invention; Figure 5 A third structural schematic diagram of a multi-chip interconnection structure provided by an embodiment of the present invention; Figure 6 A fourth structural diagram of a multi-chip interconnection structure provided by an embodiment of the present invention; Figure 7 A fifth structural diagram of a multi-chip interconnection structure provided by an embodiment of the present invention; Illustrations: 100, first plate; 101, first hole; 200, short-line transmission plate; 300, middle plate; 310, insulating layer; 400, long-line transmission plate; 500, second plate; 501, second hole; 502, third hole; 610, middle electromagnetic guide; 620, short-line electromagnetic guide; 630, long-line electromagnetic guide; 640, ferrite sheet; 700, short-line transmission channel; 710, first short-line transmission unit; 720, second short-line transmission unit; 730, intermediate short-line transmission unit; 800, long-line transmission channel; 810, first long-line transmission part; 811, first conductive part; 812, second conductive part; 813, third conductive part; 814, mounting groove; 820, second long-line transmission part; 821, fourth conductive part; 830, intermediate long-line transmission part; 840, AC capacitor; 900, chip. DETAILED DESCRIPTION

[0021] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] In the description of the present invention, it should be understood that the terms "upper", "lower", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. It should be noted that when a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0023] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0024] Embodiment 1: The multi-chip interconnection structure provided in this embodiment is suitable for the chip structure in high-speed electronic devices. In this embodiment, the specific structure of the multi-chip interconnection structure is improved to reduce the crosstalk between the internal signal transmission channels, and the overall structure has the advantage of compactness, thereby significantly improving the performance of the multi-chip interconnection structure; in addition, the multi-chip interconnection structure is particularly suitable for scenarios where multiple signal channels are transmitted together between multiple chips 900.

[0025] like Figures 1 to 7 As shown, the multi-chip interconnection structure in this embodiment includes an intermediate board 300, on which an intermediate electromagnetic guide portion 610 is provided; a short-line transmission board 200 and a first board 100 are stacked in sequence on one side of the intermediate board 300, on which a short-line transmission channel 700 is provided, and on which a short-line electromagnetic guide portion 620 is provided; a long-line transmission board 400 and a second board 500 are stacked in sequence on the other side of the intermediate board 300, on which a long-line transmission channel 800 is provided on the long-line transmission board 400, and on which a long-line electromagnetic guide portion 630 is provided; the short-line transmission channel 700 is electrically connected between two chips, and at least part of it passes through the short-line guide channel between the intermediate electromagnetic guide portion 610 and the short-line electromagnetic guide portion 620; the long-line electromagnetic guide portion 630 is electrically connected between two chips, and at least part of it passes through the long-line guide channel between the intermediate electromagnetic guide portion 610 and the long-line electromagnetic guide portion 630.

[0026] It should be noted that the short-line guiding channel refers to the space between the intermediate electromagnetic guiding part 610 on the intermediate plate 300 and the short-line electromagnetic guiding part 620 on the first plate 100, which is specifically arranged on the short-line transmission plate 200. A chip 900 can transmit a signal to another chip through the short-line transmission channel 700, and the signal will pass through the above-mentioned short-line guiding channel during the transmission process; similarly, the long-line guiding channel refers to the space between the intermediate electromagnetic guiding part 610 on the intermediate plate 300 and the long-line electromagnetic guiding part 630 on the second plate 500, which is specifically arranged on the long-line transmission plate 400. A chip 900 can transmit a signal to another chip through the long-line transmission channel 800, and the signal will pass through the above-mentioned long-line guiding channel during the transmission process; at this time, the short-line guiding channel is equivalent to the waveguide structure of the short-line transmission channel 700, and the long-line guiding channel is equivalent to the waveguide structure of the long-line transmission channel 800.

[0027] Specifically, in the multi-chip interconnection structure of the present embodiment, the middle electromagnetic guide part 610 and the short-line electromagnetic guide parts 620 and the long-line electromagnetic guide parts 630 arranged in layers on both sides form a bidirectional electromagnetic guide structure, which reduces the dependence on the shielding layer and realizes signal isolation through the electromagnetic field directional coupling mechanism: when the electromagnetic wave of the short-line transmission channel 700 propagates through the channel between the middle electromagnetic guide part 610 and the short-line electromagnetic guide part 620, its electromagnetic field energy is constrained in the vertical stacking area formed by the first board 100 to the middle board 300, while the electromagnetic wave of the long-line transmission channel 800 is confined to the stacking space on the other side from the middle board 300 to the second board 500. This separated layout realizes mutual isolation between the short-line transmission channel 700 and the long-line transmission channel 800 through the naturally formed electromagnetic isolation zone, reduces the layout impact on the transmission channel, and has a simpler design. It reduces the mutual interference of multiple signal channels while maintaining the overall structure.

[0028] like Figure 1 As shown, the short-line transmission channel 700 includes a first short-line transmission portion 710, an intermediate short-line transmission portion 730, and a second short-line transmission portion 720 that are electrically connected in sequence; the first short-line transmission portion 710 and the second short-line transmission portion 720 both extend from the surface of the first plate 100 to the short-line transmission plate 200, and the intermediate short-line transmission portion 730 is disposed on the short-line transmission plate 200 and passes through the short-line guide channel.

[0029] Among them, the first short-line transmission part 710 and the second short-line transmission part 720: these two parts are mainly responsible for extending the signal from the surface of the first board 100 to the short-line transmission board 200, and connecting to the inner pins of the chip 900 to form a complete signal transmission path. The middle short-line transmission part 730 is arranged on the short-line transmission board 200, and plays the role of connecting the first short-line transmission part 710 and the second short-line transmission part 720, specifically optimizing the signal path through electromagnetic guidance and reducing electromagnetic interference.

[0030] like Figure 2 As shown, the long-line transmission channel 800 includes a first long-line transmission portion 810, an intermediate long-line transmission portion 830, and a second long-line transmission portion 820 that are electrically connected in sequence; the first long-line transmission portion 810 and the second long-line transmission portion 820 both extend from the surface of the first plate 100 to the long-line transmission plate 400, and the intermediate long-line transmission portion 830 is disposed on the long-line transmission plate 400 and passes through the long-line guide channel.

[0031] Among them, the first long-line transmission part 810 and the second long-line transmission part 820: these two parts extend from the surface of the first board 100 to the long-line transmission board 400, and are electrically connected to the outer pins of the chip to form a signal transmission path. The middle long-line transmission part 830 is located on the long-line transmission board 400, responsible for connecting the first long-line transmission part 810 and the second long-line transmission part 820, ensuring that the signal can be effectively transmitted through the long-line transmission channel 800, and ensuring that the signal transmission path is stable and interference-free through the electromagnetic guide part.

[0032] Specifically, the short-line transmission channel 700 is located between the first long-line transmission part 810 and the second long-line transmission part 820; the first short-line transmission part 710 is electrically connected to the inner pin of one chip, and the second short-line transmission part 720 is electrically connected to the inner pin of another chip; the first long-line transmission part 810 is electrically connected to the outer pin of one chip, and the second long-line transmission part 820 is electrically connected to the outer pin of another chip.

[0033] Based on the above implementation, Figures 4 to 7 As shown, the first long-line transmission part 810 includes a first conductive part 811, a second conductive part 812 and a third conductive part 813 which are electrically connected in sequence; the first conductive part 811 extends from the surface of the first plate 100 to the second plate 500, the second conductive part 812 is arranged on the second plate 500, and the third conductive part 813 extends from the surface of the second plate 500 to the long-line transmission plate 400; the second conductive part 812 is provided with a mounting groove 814, and an AC capacitor 840 is electrically connected in the mounting groove 814.

[0034] It should be noted that the three conductive parts, the first conductive part 811, the second conductive part 812 and the third conductive part 813, are important components of signal transmission, and are responsible for transmitting the signal from the first board 100 to the long-line transmission board 400, and ensuring the integrity of the signal, and can be made of copper or aluminum. The mounting groove 814 is an opening on the second conductive part 812, which is used to accommodate and connect the AC capacitor 840. The AC capacitor 840 plays a role in balancing the voltage and reducing signal interference in the multi-chip interconnection structure, especially for high-frequency signal transmission. Its role is more significant. In addition, it should be noted that the AC capacitor 840 is arranged on the second board 500 and is located at the same level as the long-line electromagnetic guide part 630, reducing the number of structural layers and complexity, so that the entire system can further improve the performance without adding additional layers, and maintain the overall compactness of the structure, that is, the arrangement reduces the mutual interference and space occupied between components, and improves the density and layout optimization of the design; in addition, the AC capacitor 840 is placed near the middle long-line transmission part 830, especially installed together with the components related to the long-line transmission channel 800, which helps to reduce the high-frequency noise in the circuit.

[0035] As an optional implementation, based on the above implementation, Figure 4 As shown, the second long-line transmission part 820 and the first long-line transmission part 810 are symmetrically arranged. At this time, except for the third hole 502 in the multi-chip interconnection structure, the first hole 101 and the second hole 501 are all through holes, which can reduce the requirements on the processing accuracy of the multi-chip interconnection structure.

[0036] As another optional implementation, based on the above implementation, Figure 6 As shown, the second long-line transmission portion 820 includes a fourth conductive portion 821, which extends from the surface of the first plate 100 to the long-line transmission plate 400, and the intermediate long-line transmission portion 830 on the long-line transmission plate 400 correspondingly extends to the outside of the long-line transmission channel 800. During processing, the second hole 501 is correspondingly extended from the first plate 100 to the second plate 500 and passes through the intermediate long-line transmission portion 830, and then the area where the second hole 501 intersects with the second plate 500 is plugged by a glue nail, so as to subsequently form a fourth conductive portion 821 extending from the first plate 100 to the long-line transmission plate 400, and then the glue nail is removed, thereby forming a fourth conductive portion 821 without additional extension, which can reduce impedance discontinuity.

[0037] Based on the above embodiment, the middle electromagnetic guide part 610, the short electromagnetic guide part 620 and the long electromagnetic guide part 630 are all copper foil layers. The edges of the middle electromagnetic guide part 610, the short electromagnetic guide part 620 and the long electromagnetic guide part 630 are sprayed with a gradient silver nano layer, and a ferrite sheet 640 is embedded in the middle electromagnetic guide part 610.

[0038] In this embodiment, if Figure 7As shown, the middle electromagnetic guide part 610, the short-line electromagnetic guide part 620 and the long-line electromagnetic guide part 630 all use copper foil as the material to optimize the electromagnetic wave propagation path in signal transmission, and ensure effective isolation between multiple signal channels and reduce interference by guiding and constraining electromagnetic waves. Copper, as the material of the electromagnetic guide part, has good conductivity and low impedance characteristics, can effectively manage the electromagnetic field and ensure the stability of the signal. In order to further optimize the electromagnetic guidance effect, the edge parts of the middle electromagnetic guide part 610, the short-line electromagnetic guide part 620 and the long-line electromagnetic guide part 630 are sprayed with a gradient silver nanolayer. This design further improves the electromagnetic performance of the guide part through the gradient coating of the silver nanolayer. Silver has higher conductivity and corrosion resistance. The gradient silver nanolayer not only enhances the electromagnetic shielding effect, but also improves the efficiency of signal transmission. The design of the gradient coating can provide better electromagnetic restraint at the edge part, reduce the leakage of electromagnetic waves in signal transmission, and further improve the integrity and transmission quality of the signal. In addition, a ferrite sheet 640 is embedded in the middle electromagnetic guide 610 to enhance the electromagnetic interference suppression function of this part. Ferrite material has good magnetic permeability and high-frequency electromagnetic wave absorption characteristics, and can effectively absorb and suppress high-frequency noise transmitted through the middle electromagnetic guide 610. This design helps to further reduce electromagnetic interference in the multi-chip interconnection structure and improve the stability and anti-interference ability of the system.

[0039] Embodiment 2: The method for preparing a multi-chip interconnection structure provided in this embodiment is used to prepare the multi-chip interconnection structure in Embodiment 1, comprising: Step S100: Figure 1 As shown, a chip mounting plate is prepared, the chip mounting plate includes a first plate 100 and a short-line transmission plate 200 which are stacked, a short-line transmission channel 700 is provided on the short-line transmission plate 200, and a short-line electromagnetic guide portion 620 is provided on the first plate 100; Among them, the short-line electromagnetic guide part 620 can be set on the first board 100 through electroplating, spraying, photolithography and other processes, and the short-line transmission channel 700 can also be realized on the short-line transmission board 200 through electroplating, spraying, photolithography and other processes. There is no limitation in this embodiment, and it can form a corresponding routing pattern; similarly, the subsequent intermediate electromagnetic guide part 610, the intermediate long-line transmission part 830, the long-line electromagnetic guide part 630, the second conductive part 812 and other structures can all be preset routing patterns; then, the installation between the first board 100 and the short-line transmission board 200 includes but is not limited to bonding, welding, etc., which is not limited in this embodiment; Step S200: Figure 2As shown, a chip carrier is prepared, the chip carrier includes a second plate 500, a long-line transmission plate 400 and an intermediate plate 300 stacked in sequence, the intermediate plate 300 is provided with an intermediate electromagnetic guide 610, the long-line transmission plate 400 is provided with a long-line transmission channel 800, and the second plate 500 is provided with a long-line electromagnetic guide 630; Step S300: Figure 3 As shown, the chip mounting plate is stacked on the middle plate 300, and the chip mounting plate is connected to the chip carrier plate, and the long-line transmission channel 800 is extended to the first plate 100; in addition, when the middle plate 300 is connected to the short-line transmission plate 200, an insulating layer 310 can be provided as a medium; Step S400 , electrically connecting two chips 900 to a first board, wherein the inner pins of the chips are electrically connected to the short-line transmission channel 700 , and the outer pins of the chips are electrically connected to the long-line transmission channel 800 .

[0040] Further, step S200 includes: Step S210, providing an intermediate plate 300 provided with an intermediate electromagnetic guide portion 610, providing a long-line transmission plate 400 provided with an intermediate long-line transmission portion 830, and providing a second plate 500 provided with a long-line electromagnetic guide portion 630 and a second conductive portion 812; Step S220, press-connecting the middle plate 300, the long-line transmission plate 400 and the second plate 500 to obtain a chip carrier plate; Step S230, drilling a hole inwardly on the surface of the second plate 500 to form a third hole 502 extending from the surface of the second plate 500 to the long-line transmission plate 400, and filling the third hole 502 with a third conductive part 813, the third conductive part 813 is electrically connected to the middle long-line transmission part 830; The process of extending the long-line transmission channel 800 to the first plate 100 includes: Step S311, drilling a hole inward on the surface of the second board 500 to form a second hole 501 that penetrates the multi-chip interconnection structure, and filling the first conductive part 811 into the second hole 501, so that the first conductive part 811, the second conductive part 812 and the third conductive part 813 are electrically connected in sequence.

[0041] After step S311, the method further includes: Step S312 , etching the second conductive portion 812 to form a mounting groove 814 , and mounting the AC capacitor 840 in the mounting groove 814 .

[0042] It can be understood that the above steps S210 to 311 can be used to form the first long-line transmission part 810, and through steps S311 to S312, the AC capacitor 840 can be set on the first long-line transmission part 810; for the second long-line transmission part 820, it can be formed through steps S210 to 311 to reduce the complexity of the process.

[0043] In addition, the second long-line transmission part 820 can also be formed by the following steps, specifically including: Step S313, drilling a hole inward on the surface of the second board 500 to form a second hole 501 penetrating the multi-chip interconnection structure, and plugging the intersection of the second hole 501 and the second board 500 with a glue nail; Step S314, filling the second hole 501 with the fourth conductive portion 821, so that the fourth conductive portion 821 extends to the middle long-line transmission portion 830; then removing the glue nail, thereby forming a fourth conductive portion 821 without additional extension.

[0044] Step S200 further includes, after step S210: step S221, etching a groove on the middle electromagnetic guide part 610; Step S222, spraying a gradient silver nanolayer on the edge of the bottom surface of the groove; Step S223, placing the ferrite sheet 640 in the groove, and spraying a gradient silver nanolayer on the edge of the surface of the ferrite sheet 640; Step S224, plating a copper layer in the groove to wrap the ferrite sheet 640; Thus, both sides of the ferrite sheet 640 are provided with a gradient silver nanolayer, and the intermediate electromagnetic guide part 610 is wrapped. It can be understood that by etching grooves on the intermediate electromagnetic guide part 610, the electromagnetic wave can be stably propagated on a specific path, thereby optimizing the signal transmission efficiency. The coating of the silver nanolayer can significantly improve the conductivity, improve the electromagnetic shielding and conductivity of the electromagnetic guide part, effectively suppress high-frequency noise, reduce electromagnetic interference, and improve the overall stability of the system and the signal transmission quality; the addition of the ferrite sheet 640, using its high-frequency magnetic material characteristics, can effectively absorb and consume high-frequency noise during the transmission process, and further suppress electromagnetic interference. In addition, the gradient silver nanolayer sprayed on both sides of the ferrite sheet 640 can provide additional electromagnetic shielding effect, enhance the overall electromagnetic isolation capability, further optimize the stability of signal transmission, and have the advantage of compact structure.

[0045] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-chip interconnection structure, characterized in that: It comprises an intermediate plate (300), wherein an intermediate electromagnetic guide portion (610) is provided on the intermediate plate (300); A short-line transmission plate (200) and a first plate (100) are sequentially stacked on one side of the intermediate plate (300), the short-line transmission plate (200) being provided with a short-line transmission channel (700), and the first plate (100) being provided with a short-line electromagnetic guide portion (620); a long-line transmission plate (400) and a second plate (500) are sequentially stacked on the other side of the intermediate plate (300), the long-line transmission plate (400) being provided with a long-line transmission channel (800), and the second plate (500) being provided with a long-line electromagnetic guide portion (630); The short-line transmission channel (700) is electrically connected between the two chips, and at least partially passes through the short-line guide channel between the intermediate electromagnetic guide part (610) and the short-line electromagnetic guide part (620); the long-line electromagnetic guide part (630) is electrically connected between the two chips, and at least partially passes through the long-line guide channel between the intermediate electromagnetic guide part (610) and the long-line electromagnetic guide part (630).

2. A multi-chip interconnection structure according to claim 1, characterized in that: The short-line transmission channel (700) comprises a first short-line transmission portion (710), an intermediate short-line transmission portion (730), and a second short-line transmission portion (720) which are electrically connected in sequence; the first short-line transmission portion (710) and the second short-line transmission portion (720) both extend from the surface of the first plate (100) to the short-line transmission plate (200), and the intermediate short-line transmission portion (730) is arranged on the short-line transmission plate (200) and passes through the short-line guide channel.

3. A multi-chip interconnection structure according to claim 2, characterized in that: The long-line transmission channel (800) comprises a first long-line transmission portion (810), an intermediate long-line transmission portion (830), and a second long-line transmission portion (820) which are electrically connected in sequence; the first long-line transmission portion (810) and the second long-line transmission portion (820) both extend from the surface of the first plate (100) to the long-line transmission plate (400), and the intermediate long-line transmission portion (830) is arranged on the long-line transmission plate (400) and passes through the long-line guide channel.

4. A multi-chip interconnection structure according to claim 3, characterized in that: The first long-line transmission portion (810) comprises a first conductive portion (811), a second conductive portion (812), and a third conductive portion (813) which are electrically connected in sequence; the first conductive portion (811) extends from the surface of the first plate (100) to the second plate (500), the second conductive portion (812) is arranged on the second plate (500), and the third conductive portion (813) extends from the surface of the second plate (500) to the long-line transmission plate (400); The second conductive portion (812) is provided with a mounting groove (814), and an AC capacitor (840) is electrically connected in the mounting groove (814).

5. The multi-chip interconnect structure according to claim 3, characterized in that: The intermediate electromagnetic guide portion (610), the short-line electromagnetic guide portion (620), and the long-line electromagnetic guide portion (630) are all copper foil layers.

6. The multi-chip interconnect structure according to claim 5, characterized in that: The edges of the middle electromagnetic guide part (610), the short-line electromagnetic guide part (620) and the long-line electromagnetic guide part (630) are all sprayed with a gradient silver nanolayer, and a ferrite sheet (640) is embedded in the middle electromagnetic guide part (610).

7. The multi-chip interconnection structure according to claim 3, characterized in that: The short-line transmission channel (700) is located between the first long-line transmission part (810) and the second long-line transmission part (820); the first short-line transmission part (710) is electrically connected to an inner pin of a chip, and the second short-line transmission part is electrically connected to an inner pin of another chip; the first long-line transmission part (810) is electrically connected to an outer pin of a chip, and the second long-line transmission part (820) is electrically connected to an outer pin of another chip.

8. A method for preparing a multi-chip interconnect structure, characterized in that: For preparing a multi-chip interconnection structure as claimed in any one of claims 1 to 7, comprising: Step S100, preparing a chip mounting plate, the chip mounting plate comprising a first plate (100) and a short-line transmission plate (200) stacked on each other, the short-line transmission plate (200) being provided with a short-line transmission channel (700), and the first plate (100) being provided with a short-line electromagnetic guide portion (620); Step S200, preparing a chip carrier, the chip carrier comprising a second plate (500), a long-line transmission plate (400) and an intermediate plate (300) stacked in sequence, the intermediate plate (300) being provided with an intermediate electromagnetic guide portion (610), the long-line transmission plate (400) being provided with a long-line transmission channel (800), and the second plate (500) being provided with a long-line electromagnetic guide portion (630); Step S300, stacking the chip mounting board on the intermediate board (300), connecting the chip mounting board and the chip carrier board, and extending the long-line transmission channel (800) to the first board (100); Step S400: electrically connecting the two chips to the first board, wherein the inner pins of the chips are electrically connected to the short-line transmission channel (700), and the outer pins of the chips are electrically connected to the long-line transmission channel (800).

9. The method for preparing a multi-chip interconnection structure according to claim 8, characterized in that: The step S200 includes: Step S210, providing an intermediate plate (300) provided with an intermediate electromagnetic guide portion (610), providing a long-line transmission plate (400) provided with an intermediate long-line transmission portion (830), and providing a second plate (500) provided with a long-line electromagnetic guide portion (630) and a second conductive portion (812); Step S220, pressing and connecting the middle plate (300), the long-line transmission plate (400) and the second plate (500) to obtain a chip carrier plate; Step S230, drilling a hole inwardly on the surface of the second plate (500) to form a third hole (502) extending from the surface of the second plate (500) to the long-line transmission plate (400), and filling the third hole (502) with a third conductive part (813), wherein the third conductive part (813) is electrically connected to the intermediate long-line transmission part (830); The process of extending the long-line transmission channel (800) to the first plate (100) comprises: Step S311, drilling a hole inward on the surface of the second board (500) to form a second hole (501) penetrating the multi-chip interconnection structure, and filling the first conductive part (811) into the second hole (501), so that the first conductive part (811), the second conductive part (812) and the third conductive part (813) are electrically connected in sequence.

10. The method for preparing a multi-chip interconnection structure according to claim 9, characterized in that: After step S311, the method further includes: Step S312: etching the second conductive portion (812) to form a mounting groove (814), and mounting an AC capacitor (840) in the mounting groove (814).

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