A multi-chip interconnection structure and a preparation method thereof

Abstract

The present invention discloses a multi-chip interconnection structure and a preparation method thereof, relating to the technical field of semiconductor structures. Specifically, it includes an intermediate plate, on which an intermediate electromagnetic guiding part is arranged; a short-line transmission plate and a first plate are sequentially stacked on one side of the intermediate plate. A short-line transmission channel is arranged on the short-line transmission plate, and a short-line electromagnetic guiding part is arranged on the first plate; a long-line transmission plate and a second plate are sequentially stacked on the other side of the intermediate plate. A long-line transmission channel is arranged on the long-line transmission plate, and a long-line electromagnetic guiding part is arranged on the second plate; at least part of the short-line transmission channel passes through a short-line guiding channel between the intermediate electromagnetic guiding part and the short-line electromagnetic guiding part; at least part of the long-line electromagnetic guiding part passes through a long-line guiding channel between the intermediate electromagnetic guiding part and the long-line electromagnetic guiding part. This separated layout realizes the mutual isolation between the short-line transmission channel and the long-line transmission channel through a naturally formed electromagnetic isolation band, reducing the layout influence on the transmission channels.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor structures, and particularly to a multi-chip interconnection structure and a preparation method thereof. Background Art

[0002] In the semiconductor field such as high-speed electronic devices, multi-chip interconnection is the key to achieving efficient signal transmission. With the continuous improvement of communication speed and bandwidth requirements, how to design a semiconductor structure that can effectively support multi-channel signal transmission while maintaining signal integrity has become a key research and development direction for those skilled in the art.

[0003] In existing technical solutions, in order to achieve high communication speed and high-bandwidth signal transmission, surface or inner-layer traces are usually used to transmit signals from one chip to another, and the integrity of signal transmission needs to be ensured as much as possible during design. However, when multi-channel signals are parallel, the mutual interference between signals becomes the main problem in design. Especially when the traces of multiple signal channels are too close, signal crosstalk will significantly affect the performance of the system, resulting in signal distortion and even communication errors. To alleviate these problems, those skilled in the art usually adopt means such as electromagnetic shielding or differential signal traces to reduce electromagnetic interference. However, when dealing with multiple signal channels, a relatively complex shielding design is often required, resulting in a relatively bulky overall design.

[0004] More specifically, for the electromagnetic interference problem of multi-signal channels, the following several shielding design schemes are usually adopted: First, an isolation groove or shielding wall design is adopted, that is, a metallized via array is set between adjacent signal channels to form a Faraday cage effect, but the dense shielding vias will occupy a large amount of wiring space; Second, a coaxial shielding structure is adopted, and the conductor is shielded 360° by surrounding the signal line, but this scheme requires complex processes to implement and the design is relatively bulky.

[0005] Therefore, it is necessary to design a new substrate structure to solve the technical problem that the multi-chip interconnection structure in the prior art is difficult to prevent the mutual interference of multi-signal channels while maintaining a compact structure. Summary of the Invention

[0006] The purpose of the present invention is to provide a multi-chip interconnection structure and a preparation method thereof, so as to solve the technical problem that the multi-chip interconnection structure in the prior art is difficult to reduce the mutual interference of multi-signal channels while maintaining a compact structure.

[0007] To achieve this purpose, the present invention adopts the following technical solutions:

[0008] A multi-chip interconnection structure includes an intermediate board, and an intermediate electromagnetic guiding part is arranged on the intermediate board;

[0009] On one side of the intermediate board, a short-line transmission board and a first board are stacked in sequence. A short-line transmission channel is provided on the short-line transmission board, and a short-line electromagnetic guiding part is provided on the first board. On the other side of the intermediate board, a long-line transmission board and a second board are stacked in sequence. The long-line transmission board is provided with a long-line transmission channel, and a long-line electromagnetic guiding part is provided on the second board.

[0010] The short-line transmission channel is electrically connected between two chips, and at least partially passes through a short-line guiding channel between the intermediate electromagnetic guiding part and the short-line electromagnetic guiding part. The long-line transmission channel is electrically connected between two chips, and at least partially passes through a long-line guiding channel between the intermediate electromagnetic guiding part and the long-line electromagnetic guiding part.

[0011] Optionally, the short-line transmission channel includes a first short-line transmission part, an intermediate short-line transmission part, and a second short-line transmission part that are electrically connected in sequence. Both the first short-line transmission part and the second short-line transmission part extend from the surface of the first board to the short-line transmission board, and the intermediate short-line transmission part is disposed on the short-line transmission board and passes through the short-line guiding channel.

[0012] Optionally, the long-line transmission channel includes a first long-line transmission part, an intermediate long-line transmission part, and a second long-line transmission part that are electrically connected in sequence. Both the first long-line transmission part and the second long-line transmission part extend from the surface of the first board to the long-line transmission board, and the long-line transmission part is disposed on the long-line transmission board and passes through the long-line guiding channel.

[0013] Optionally, the first long-line transmission part includes a first conductive part, a second conductive part, and a third conductive part that are electrically connected in sequence. The first conductive part extends from the surface of the first board to the second board, the second conductive part is disposed on the second board, and the third conductive part extends from the surface of the second board to the long-line transmission board.

[0014] An installation groove is formed in the second conductive part, and an AC capacitor is electrically connected in the installation groove.

[0015] Optionally, the intermediate electromagnetic guiding part, the short-line electromagnetic guiding part, and the long-line electromagnetic guiding part are all copper foil layers.

[0016] Optionally, a gradient silver nano layer is sprayed on the edges of the intermediate electromagnetic guiding part, the short-line electromagnetic guiding part, and the long-line electromagnetic guiding part, and a ferrite thin sheet is embedded in the intermediate electromagnetic guiding part.

[0017] Optionally, the short transmission channel is located between the first long transmission part and the second long transmission part; the first short transmission part is electrically connected to the inner pins of one chip, and the second short transmission part is electrically connected to the inner pins of the other chip; the first long transmission part is connected to the outer pins of one chip, and the second long transmission part is connected to the outer pins of the other chip.

[0018] A preparation method of a multi-chip interconnection structure for preparing the multi-chip interconnection structure as described above, including:

[0019] Step S100, prepare a chip mounting board, the chip mounting board includes a first board and a short transmission board stacked on each other, a short transmission channel is provided on the short transmission board, and a short electromagnetic guiding part is provided on the first board;

[0020] Step S200, prepare a chip carrier board, the chip carrier board includes a second board, a long transmission board and an intermediate board stacked in sequence, an intermediate electromagnetic guiding part is provided on the intermediate board, a long transmission channel is provided on the long transmission board, and a long electromagnetic guiding part is provided on the second board;

[0021] Step S300, stack the chip mounting board on the intermediate board, connect the chip mounting board and the chip carrier board, and extend the long transmission channel to the first board;

[0022] Step S400, electrically connect two chips on the first board, the inner pins of the chips are electrically connected to the short transmission channel, and the outer pins of the chips are electrically connected to the long transmission channel.

[0023] Optionally, the step S200 includes:

[0024] Step S210, provide an intermediate board provided with an intermediate electromagnetic guiding part, provide a long transmission board provided with an intermediate long transmission part, and provide a second board provided with a long electromagnetic guiding part and a second conductive part;

[0025] Step S220, press and connect the intermediate board, the long transmission board and the second board to obtain a chip carrier board;

[0026] Step S230, drill a hole inward on the surface of the second board to form a third hole extending from the surface of the second board to the long transmission board, and fill a third conductive part in the third hole, and the third conductive part is electrically connected to the intermediate long transmission part;

[0027] The process of extending the long transmission channel to the first board includes:

[0028] Step S311: Drill holes inward on the surface of the second board to form second holes penetrating the multi-chip interconnection structure, and fill the first conductive part into the second holes, so that the first conductive part, the second conductive part, and the third conductive part are electrically connected in sequence.

[0029] Optionally, after the step S311, the following steps are further included:

[0030] Step S312: Etch mounting grooves on the second conductive part, and mount AC capacitors in the mounting grooves.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] For the multi-chip interconnection structure and its preparation method provided by the present invention, the intermediate electromagnetic guiding part and the short-line electromagnetic guiding parts and long-line electromagnetic guiding parts arranged in layers on both sides form a two-way electromagnetic guiding structure, reducing the dependence on the shielding layer, and realizing signal isolation through the electromagnetic field directional coupling mechanism: when the electromagnetic wave of the short-line transmission channel propagates through the channel between the intermediate electromagnetic guiding part and the short-line electromagnetic guiding part, its electromagnetic field energy is constrained within the vertical laminated area formed by the first board to the intermediate board, while the electromagnetic wave of the long-line transmission channel is restricted in the other laminated space from the intermediate board to the second board. This separated layout realizes the mutual isolation between the short-line transmission channel and the long-line transmission channel through the naturally formed electromagnetic isolation belt, reducing the influence on the layout of the transmission channels, with a more concise design, and reducing the mutual interference of multiple signal channels while maintaining the overall structure. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0034] The structures, ratios, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those who are familiar with this technology to understand and read, and are not used to limit the limited conditions for the implementation of the present invention. Therefore, they do not have technical essential meanings. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention.

[0035] Figure 1 It is a schematic structural diagram of the chip mounting board in the embodiment of the present invention;

[0036] Figure 2 It is a schematic structural diagram of the chip carrier board in the embodiment of the present invention;

[0037] Figure 3 It is the first structural schematic diagram of the multi-chip interconnection structure provided by the embodiment of the present invention;

[0038] Figure 4 It is the second structural schematic diagram of the multi-chip interconnection structure provided by the embodiment of the present invention;

[0039] Figure 5 It is the third structural schematic diagram of the multi-chip interconnection structure provided by the embodiment of the present invention;

[0040] Figure 6 It is the fourth structural schematic diagram of the multi-chip interconnection structure provided by the embodiment of the present invention;

[0041] Figure 7 It is the fifth structural schematic diagram of the multi-chip interconnection structure provided by the embodiment of the present invention;

[0042] Illustration: 100, the first board; 101, the first hole; 200, the short-line transmission board; 300, the intermediate board; 310, the insulating layer; 400, the long-line transmission board; 500, the second board; 501, the second hole; 502, the third hole; 610, the intermediate electromagnetic guiding part; 620, the short-line electromagnetic guiding part; 630, the long-line electromagnetic guiding part; 640, the ferrite sheet;

[0043] 700, the short-line transmission channel; 710, the first short-line transmission part; 720, the second short-line transmission part; 730, the intermediate short-line transmission part;

[0044] 800, the long-line transmission channel; 810, the first long-line transmission part; 811, the first conductive part; 812, the second conductive part; 813, the third conductive part; 814, the installation groove; 820, the second long-line transmission part; 821, the fourth conductive part; 830, the intermediate long-line transmission part; 840, the AC capacitor; 900, the chip. Detailed implementation manners

[0045] To make the objectives, features, and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the embodiments described below are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. It should be noted that when a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be an intermediate component present.

[0047] The technical solution of the present invention will be further described below with reference to the drawings and specific embodiments.

[0048] Embodiment 1:

[0049] The multi-chip interconnection structure provided in this embodiment is applicable to the chip structure in high-speed electronic devices. In this embodiment, by improving the specific structure of the multi-chip interconnection structure, the crosstalk between the signal transmission channels inside it is reduced, and the overall structure has the advantage of compactness, thereby significantly improving the performance of the multi-chip interconnection structure; in addition, this multi-chip interconnection structure is particularly applicable to the scenario where multiple signals are jointly transmitted between multiple chips 900.

[0050] As Figures 1 to 7 shown, the multi-chip interconnection structure in this embodiment includes an intermediate board 300, and an intermediate electromagnetic guiding part 610 is provided on the intermediate board 300; a short-line transmission board 200 and a first board 100 are sequentially stacked on one side of the intermediate board 300. A short-line transmission channel 700 is provided on the short-line transmission board 200, and a short-line electromagnetic guiding part 620 is provided on the first board 100; a long-line transmission board 400 and a second board 500 are sequentially stacked on the other side of the intermediate board 300. The long-line transmission board 400 is provided with a long-line transmission channel 800, and a long-line electromagnetic guiding part 630 is provided on the second board 500; the short-line transmission channel 700 is electrically connected between two chips, and at least part of it passes through the short-line guiding channel between the intermediate electromagnetic guiding part 610 and the short-line electromagnetic guiding part 620; the long-line transmission channel 800 is electrically connected between two chips, and at least part of it passes through the long-line guiding channel between the intermediate electromagnetic guiding part 610 and the long-line electromagnetic guiding part 630.

[0051] It should be noted that the short - line guiding channel refers to the space between the intermediate electromagnetic guiding part 610 on the intermediate board 300 and the short - line electromagnetic guiding part 620 on the first board 100, which is specifically arranged on the short - line transmission board 200. A chip 900 can transmit signals to another chip through the short - line transmission channel 700, and the signal will pass through the above - mentioned short - line guiding channel during the transmission process. Similarly, the long - line guiding channel refers to the space between the intermediate electromagnetic guiding part 610 on the intermediate board 300 and the long - line electromagnetic guiding part 630 on the second board 500, which is specifically arranged on the long - line transmission board 400. A chip 900 can transmit signals to another chip through the long - line transmission channel 800, and the signal will pass through the above - mentioned long - line guiding channel during the transmission process. At this time, the short - line guiding channel is equivalent to the waveguide structure of the short - line transmission channel 700, and the long - line guiding channel is equivalent to the waveguide structure of the long - line transmission channel 800.

[0052] Specifically, in the multi - chip interconnection structure of this embodiment, the intermediate electromagnetic guiding part 610 and the short - line electromagnetic guiding part 620 and the long - line electromagnetic guiding part 630 arranged in layers on both sides form a bidirectional electromagnetic guiding structure, reducing the dependence on the shielding layer and realizing signal isolation through the electromagnetic field directional coupling mechanism: when the electromagnetic wave of the short - line transmission channel 700 propagates through the channel between the intermediate electromagnetic guiding part 610 and the short - line electromagnetic guiding part 620, its electromagnetic field energy is confined within the vertical laminated area formed from the first board 100 to the intermediate board 300, while the electromagnetic wave of the long - line transmission channel 800 is restricted to the other laminated space from the intermediate board 300 to the second board 500. This separated layout realizes the mutual isolation between the short - line transmission channel 700 and the long - line transmission channel 800 through the naturally formed electromagnetic isolation band, reducing the influence on the layout of the transmission channels, with a more concise design and reducing the mutual interference of multiple signal channels while maintaining the overall structure.

[0053] As Figure 1 shown, the short - line transmission channel 700 includes a first short - line transmission part 710, an intermediate short - line transmission part 730, and a second short - line transmission part 720 that are electrically connected in sequence. Both the first short - line transmission part 710 and the second short - line transmission part 720 extend from the surface of the first board 100 to the short - line transmission board 200, and the intermediate short - line transmission part 730 is arranged on the short - line transmission board 200 and passes through the short - line guiding channel.

[0054] Among them, the first short - line transmission part 710 and the second short - line transmission part 720: These two components are mainly responsible for extending the signal from the surface of the first board 100 to the short - line transmission board 200 and connecting to the inner pins of the chip 900 to form a complete signal transmission path. The intermediate short - line transmission part 730 is arranged on the short - line transmission board 200, playing a role in connecting the first short - line transmission part 710 and the second short - line transmission part 720, and specifically optimizing the signal path through electromagnetic guiding to reduce electromagnetic interference.

[0055] As Figure 2 shown, the long - line transmission channel 800 includes a first long - line transmission part 810, an intermediate long - line transmission part 830, and a second long - line transmission part 820 that are electrically connected in sequence. Both the first long - line transmission part 810 and the second long - line transmission part 820 extend from the surface of the first board 100 to the long - line transmission board 400, and the intermediate long - line transmission part 830 is disposed on the long - line transmission board 400 and passes through the long - line guiding channel.

[0056] Among them, for the first long - line transmission part 810 and the second long - line transmission part 820: These two components respectively extend from the surface of the first board 100 to the long - line transmission board 400 and are electrically connected to the outer pins of the chip to form a signal transmission path. The intermediate long - line transmission part 830 is located on the long - line transmission board 400 and is responsible for connecting the first long - line transmission part 810 and the second long - line transmission part 820 to ensure that signals can be effectively transmitted through the long - line transmission channel 800, and the electromagnetic guiding part ensures the stability and interference - free of the signal transmission path.

[0057] Specifically, the short - line transmission channel 700 is located between the first long - line transmission part 810 and the second long - line transmission part 820. The first short - line transmission part 710 is electrically connected to the inner pin of one chip, and the second short - line transmission part 720 is electrically connected to the inner pin of another chip. The first long - line transmission part 810 is electrically connected to the outer pin of one chip, and the second long - line transmission part 820 is electrically connected to the outer pin of another chip.

[0058] On the basis of the above - mentioned embodiment, as Figures 4 to 7 shown, the first long - line transmission part 810 includes a first conductive part 811, a second conductive part 812, and a third conductive part 813 that are electrically connected in sequence. The first conductive part 811 extends from the surface of the first board 100 to the second board 500, the second conductive part 812 is disposed on the second board 500, and the third conductive part 813 extends from the surface of the second board 500 to the long - line transmission board 400. The second conductive part 812 is provided with an installation groove 814, and an AC capacitor 840 is electrically connected in the installation groove 814.

[0059] It should be noted that the three conductive parts, namely the first conductive part 811, the second conductive part 812, and the third conductive part 813, are important components for signal transmission. They are respectively responsible for transmitting signals from the first board 100 to the long-line transmission board 400 and ensuring signal integrity. Copper or aluminum can be used. The installation groove 814 is an opening on the second conductive part 812 for accommodating and connecting the AC capacitor 840. The AC capacitor 840 plays a role in balancing voltage and reducing signal interference in this multi-chip interconnection structure, especially when transmitting high-frequency signals, its role is more significant. In addition, it should be noted that the AC capacitor 840 is arranged on the second board 500 and is at the same level as the long-line electromagnetic guiding part 630, reducing the number of structural layers and complexity, enabling the entire system to further improve performance without adding extra layers and maintaining the overall structural compactness. That is to say, this arrangement reduces the mutual interference and occupied space between components, improves the design density and layout optimization; in addition, the AC capacitor 840 is placed near the middle long-line transmission part 830, especially installed together with the components related to the long-line transmission channel 800, which helps to reduce high-frequency noise in the circuit.

[0060] As an optional implementation manner, based on the above implementation manner, as Figure 4 shown, the second long-line transmission part 820 is symmetrically arranged with the first long-line transmission part 810. At this time, in the multi-chip interconnection structure, except for the third hole 502, the first hole 101 and the second hole 501 are both through holes, which can reduce the requirements for the processing accuracy of the multi-chip interconnection structure.

[0061] As another optional implementation manner, based on the above implementation manner, as Figure 6 shown, the second long-line transmission part 820 includes a fourth conductive part 821, which extends from the surface of the first board 100 to the long-line transmission board 400. The middle long-line transmission part 830 on the long-line transmission board 400 correspondingly extends outside the long-line transmission channel 800. During processing, the second hole 501 is correspondingly extended from the first board 100 to the second board 500 and passes through the middle long-line transmission part 830. Then, the area where the second hole 501 intersects with the second board 500 is blocked by a glue nail, so as to form a fourth conductive part 821 extending from the first board 100 to the long-line transmission board 400 subsequently. Then, the glue nail is removed, thereby forming a fourth conductive part 821 without additional extension, which can reduce impedance discontinuity.

[0062] Based on the above implementation manner, the middle electromagnetic guiding part 610, the short-line electromagnetic guiding part 620, and the long-line electromagnetic guiding part 630 are all copper foil layers. The edges of the middle electromagnetic guiding part 610, the short-line electromagnetic guiding part 620, and the long-line electromagnetic guiding part 630 are all sprayed with a gradient silver nano layer, and a ferrite thin sheet 640 is embedded in the middle electromagnetic guiding part 610.

[0063] In this embodiment, as Figure 7 shown, the middle electromagnetic guiding part 610, the short-line electromagnetic guiding part 620, and the long-line electromagnetic guiding part 630 all use copper foil layers as materials to optimize the electromagnetic wave propagation path in signal transmission. By guiding and constraining electromagnetic waves, effective isolation between multiple signal channels is ensured, and interference is reduced. Copper, as the material of the electromagnetic guiding part, has good electrical conductivity and low impedance characteristics, and can effectively manage the electromagnetic field to ensure signal stability. To further optimize the electromagnetic guiding effect, the edge parts of the middle electromagnetic guiding part 610, the short-line electromagnetic guiding part 620, and the long-line electromagnetic guiding part 630 are all sprayed with a gradient silver nano-layer. This design further improves the electromagnetic performance of the guiding part through the gradient coating of the silver nano-layer. Silver has higher electrical conductivity and corrosion resistance. The gradient silver nano-layer not only enhances the electromagnetic shielding effect but also improves the signal transmission efficiency. The design of the gradient coating can provide better electromagnetic binding force at the edge part, reduce the electromagnetic wave leakage in signal transmission, and thus further improve the signal integrity and transmission quality. In addition, a ferrite thin sheet 640 is embedded in the middle electromagnetic guiding part 610 to enhance the electromagnetic interference suppression function of this part. Ferrite materials have good magnetic permeability and high-frequency electromagnetic wave absorption characteristics, and can effectively absorb and suppress the high-frequency noise transmitted through the middle electromagnetic guiding part 610. Such a design helps to further reduce the electromagnetic interference in the multi-chip interconnection structure and improve the stability and anti-interference ability of the system.

[0064] Embodiment Two:

[0065] The preparation method of the multi-chip interconnection structure provided in this embodiment is used to prepare the multi-chip interconnection structure in Embodiment One, and includes:

[0066] Step S100, as Figure 1 shown, prepare a chip mounting board. The chip mounting board includes a stacked first board 100 and a short-line transmission board 200. A short-line transmission channel 700 is provided on the short-line transmission board 200, and a short-line electromagnetic guiding part 620 is provided on the first board 100;

[0067] Among them, the short-line electromagnetic guiding part 620 can be formed on the first board 100 through processes such as electroplating, spraying, and lithography. The short-line transmission channel 700 is also formed on the short-line transmission board 200 through processes such as electroplating, spraying, and lithography. There is no limitation in this embodiment as long as the corresponding wiring pattern can be formed. Similarly, subsequent structures such as the middle electromagnetic guiding part 610, the middle long-line transmission part 830, the long-line electromagnetic guiding part 630, and the second conductive part 812 can all be preset wiring patterns. Then, the installation between the first board 100 and the short-line transmission board 200 includes, but is not limited to, bonding, welding, etc., and there is no limitation in this embodiment;

[0068] Step S200, asFigure 2 As shown, a chip carrier board is prepared. The chip carrier board includes a second board 500, a long-line transmission board 400, and an intermediate board 300 stacked in sequence. An intermediate electromagnetic guiding portion 610 is provided on the intermediate board 300, a long-line transmission channel 800 is provided on the long-line transmission board 400, and a long-line electromagnetic guiding portion 630 is provided on the second board 500;

[0069] Step S300: As Figure 3 shown, stack the chip mounting board on the intermediate board 300, connect the chip mounting board and the chip carrier board, and extend the long-line transmission channel 800 to the first board 100; in addition, when connecting the intermediate board 300 and the short-line transmission board 200, an insulating layer 310 can be provided as a medium;

[0070] Step S400: Electrically connect two chips 900 to the first board. The inner pins of the chips are electrically connected to the short-line transmission channels 700, and the outer pins of the chips are electrically connected to the long-line transmission channels 800.

[0071] Further, step S200 includes:

[0072] Step S210: Provide an intermediate board 300 provided with an intermediate electromagnetic guiding portion 610, provide a long-line transmission board 400 provided with an intermediate long-line transmission portion 830, and provide a second board 500 provided with a long-line electromagnetic guiding portion 630 and a second conductive portion 812;

[0073] Step S220: Press and connect the intermediate board 300, the long-line transmission board 400, and the second board 500 to obtain a chip carrier board;

[0074] Step S230: Drill a hole inward on the surface of the second board 500 to form a third hole 502 extending from the surface of the second board 500 to the long-line transmission board 400, and fill a third conductive portion 813 in the third hole 502. The third conductive portion 813 is electrically connected to the intermediate long-line transmission portion 830;

[0075] The process of extending the long-line transmission channel 800 to the first board 100 includes:

[0076] Step S311: Drill a hole inward on the surface of the second board 500 to form a second hole 501 penetrating the multi-chip interconnection structure, and fill a first conductive portion 811 in the second hole 501, so that the first conductive portion 811, the second conductive portion 812, and the third conductive portion 813 are electrically connected in sequence.

[0077] After step S311, it further includes:

[0078] Step S312: Etch an installation groove 814 on the second conductive portion 812, and mount an AC capacitor 840 in the installation groove 814.

[0079] It can be understood that the above steps S210 to S311 can be used to form the first long-line transmission part 810, and through steps S311 to S312, an AC capacitor 840 is set on the first long-line transmission part 810; for the second long-line transmission part 820, it can be formed through steps S210 to S311 to reduce the process complexity.

[0080] In addition, the second long-line transmission part 820 can also be formed through the following steps, specifically including:

[0081] Step S313: Drill a hole inward on the surface of the second board 500 to form a second hole 501 penetrating the multi-chip interconnection structure, and plug the area where the second hole 501 intersects with the second board 500 with a glue nail;

[0082] Step S314: Fill the fourth conductive part 821 into the second hole 501, and make the fourth conductive part 821 extend to the middle long-line transmission part 830; then remove the glue nail, thereby forming a fourth conductive part 821 without additional extension.

[0083] Step S200 also includes, after step S210: Step S221: Etch a groove on the middle electromagnetic guiding part 610;

[0084] Step S222: Spray a gradient silver nanolayer on the edge part of the bottom surface of the groove;

[0085] Step S223: Place a ferrite sheet 640 in the groove, and spray a gradient silver nanolayer on the edge part of the surface of the ferrite sheet 640;

[0086] Step S224: Deposit a copper layer in the groove to wrap the ferrite sheet 640;

[0087] Thus, gradient silver nanolayers are provided on both sides of the ferrite sheet 640 and it is wrapped with the middle electromagnetic guiding part 610. It can be understood that by etching a groove on the middle electromagnetic guiding part 610, electromagnetic waves can stably propagate on a specific path, optimizing the signal transmission efficiency. The coating of the silver nanolayer can significantly improve the conductivity, improve the electromagnetic shielding and conductive performance of the electromagnetic guiding part, effectively suppress high-frequency noise, and reduce electromagnetic interference, enhancing the overall stability of the system and the signal transmission quality; the addition of the ferrite sheet 640, using its high-frequency magnetic material characteristics, can effectively absorb and consume high-frequency noise during the transmission process, further suppressing electromagnetic interference. In addition, gradient silver nanolayers are sprayed on both sides of the ferrite sheet 640, which can provide an additional electromagnetic shielding effect, enhance the overall electromagnetic isolation ability, further optimize the stability of signal transmission, and have the advantage of a compact structure.

[0088] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-chip interconnection structure, characterized in that, It includes an intermediate plate (300) provided with an intermediate electromagnetic guiding portion (610) thereon; On one side of the intermediate plate (300), a short-line transmission plate (200) and a first plate (100) are sequentially stacked. A short-line transmission channel (700) is provided on the short-line transmission plate (200), and a short-line electromagnetic guiding portion (620) is provided on the first plate (100). On the other side of the intermediate plate (300), a long-line transmission plate (400) and a second plate (500) are sequentially stacked. A long-line transmission channel (800) is provided on the long-line transmission plate (400), and a long-line electromagnetic guiding portion (630) is provided on the second plate (500); The short-line transmission channel (700) is electrically connected between two chips and at least partially passes through a short-line guiding channel between the intermediate electromagnetic guiding portion (610) and the short-line electromagnetic guiding portion (620). The long-line transmission channel (800) is electrically connected between two chips and at least partially passes through a long-line guiding channel between the intermediate electromagnetic guiding portion (610) and the long-line electromagnetic guiding portion (630); The short-line transmission channel (700) includes a first short-line transmission portion (710), an intermediate short-line transmission portion (730), and a second short-line transmission portion (720) that are electrically connected in sequence. Both the first short-line transmission portion (710) and the second short-line transmission portion (720) extend from the surface of the first plate (100) to the short-line transmission plate (200), and the intermediate short-line transmission portion (730) is disposed on the short-line transmission plate (200) and passes through the short-line guiding channel; The long-line transmission channel (800) includes a first long-line transmission portion (810), an intermediate long-line transmission portion (830), and a second long-line transmission portion (820) that are electrically connected in sequence. Both the first long-line transmission portion (810) and the second long-line transmission portion (820) extend from the surface of the first plate (100) to the long-line transmission plate (400), and the intermediate long-line transmission portion (830) is disposed on the long-line transmission plate (400) and passes through the long-line guiding channel; The intermediate electromagnetic guiding portion (610), the short-line electromagnetic guiding portion (620), and the long-line electromagnetic guiding portion (630) are all copper foil layers. Gradient silver nano-layers are sprayed on the edges of the intermediate electromagnetic guiding portion (610), the short-line electromagnetic guiding portion (620), and the long-line electromagnetic guiding portion (630), and a ferrite thin sheet (640) is embedded in the intermediate electromagnetic guiding portion (610).

2. The multi-chip interconnection structure according to claim 1, characterized in that, The first long-line transmission portion (810) includes a first conductive portion (811), a second conductive portion (812), and a third conductive portion (813) that are electrically connected in sequence. The first conductive portion (811) extends from the surface of the first plate (100) to the second plate (500), the second conductive portion (812) is disposed on the second plate (500), and the third conductive portion (813) extends from the surface of the second plate (500) to the long-line transmission plate (400); The second conductive part (812) is provided with a mounting groove (814), and an AC capacitor (840) is electrically connected in the mounting groove (814).

3. A multi-chip interconnection structure according to claim 1, characterized in that, The short - line transmission channel (700) is located between the first long - line transmission part (810) and the second long - line transmission part (820); the first short - line transmission part (710) is electrically connected to the inner pins of a chip, and the second short - line transmission part is electrically connected to the inner pins of another chip; the first long - line transmission part (810) is electrically connected to the outer pins of a chip, and the second long - line transmission part (820) is electrically connected to the outer pins of another chip.

4. A preparation method of a multi-chip interconnection structure, characterized in that A method for manufacturing a multi - chip interconnection structure as claimed in any one of claims 1 - 3, comprising: Step S100, preparing a chip mounting board, the chip mounting board includes a first board (100) and a short - line transmission board (200) stacked on each other, the short - line transmission board (200) is provided with a short - line transmission channel (700), and the first board (100) is provided with a short - line electromagnetic guiding part (620); Step S200, preparing a chip carrier board, the chip carrier board includes a second board (500), a long - line transmission board (400) and an intermediate board (300) stacked in sequence, the intermediate board (300) is provided with an intermediate electromagnetic guiding part (610), the long - line transmission board (400) is provided with a long - line transmission channel (800), and the second board (500) is provided with a long - line electromagnetic guiding part (630); Step S300, stacking the chip mounting board on the intermediate board (300), connecting the chip mounting board and the chip carrier board, and extending the long - line transmission channel (800) to the first board (100); Step S400, electrically connecting two chips to the first board, the inner pins of the chips are electrically connected to the short - line transmission channel (700), and the outer pins of the chips are electrically connected to the long - line transmission channel (800).

5. The manufacturing method of a multi-chip interconnection structure according to claim 4, characterized in that The step S200 includes: Step S210, providing an intermediate board (300) provided with an intermediate electromagnetic guiding part (610), providing a long - line transmission board (400) provided with an intermediate long - line transmission part (830), and providing a second board (500) provided with a long - line electromagnetic guiding part (630) and a second conductive part (812); Step S220, pressing and connecting the intermediate board (300), the long - line transmission board (400) and the second board (500) to obtain a chip carrier board; Step S230, drilling inward on the surface of the second board (500) to form a third hole (502) extending from the surface of the second board (500) to the long - line transmission board (400), and filling a third conductive part (813) in the third hole (502), the third conductive part (813) is electrically connected to the intermediate long - line transmission part (830); The process of extending the long - line transmission channel (800) to the first board (100) includes: Step S311: Drill a hole inward on the surface of the second board (500) to form a second hole (501) penetrating the multi-chip interconnect structure, and fill the first conductive part (811) into the second hole (501), so that the first conductive part (811), the second conductive part (812) and the third conductive part (813) are electrically connected in sequence.

6. The manufacturing method of a multi-chip interconnection structure according to claim 5, characterized in that After the step S311, the following steps are further included: Step S312: Etch and form a mounting groove (814) on the second conductive part (812), and mount an AC capacitor (840) in the mounting groove (814).

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