A reverse voltage protection circuit

Abstract

The present invention relates to the field of protection circuits, and particularly to a reverse voltage protection circuit, which includes a current modulation module, a reverse voltage detection module, a reverse blocking module, and a drive system; the drive system includes a charge pump boost module and a power transistor N1; after the load switch is enabled, the current modulation module operates to provide a first bias voltage VB101 and a second bias voltage VB102 for the reverse voltage detection module, and the charge pump boost module boosts the gate voltage Vgate of the power transistor N1 to drive the power transistor N1 into the linear region to supply power to an external load; the reverse voltage detection module continuously detects the magnitude of the output voltage V OUT and compares it with the input voltage VIN. If the V OUT of the output voltage is greater than VIN and exceeds a certain range, the reverse voltage controls the reverse blocking module to operate, clamp the gate voltage Vgate of the power transistor N1, turn off the power transistor N1, and block the input and output currents.

Description

Technical Field

[0001] The present invention relates to the field of protection circuits, and in particular to a reverse voltage protection circuit. Background Art

[0002] A protection circuit is a safety device specially designed to prevent a circuit from being damaged under abnormal circumstances. Its core purpose is to ensure that the circuit can take quick and effective measures when facing potential dangers such as overcurrent, overvoltage, overtemperature or short circuit, so as to protect the components, equipment and even the entire system in the circuit from damage. In the use of load switches, when the circuit controlled by the load switch contains inductive elements (such as relays, inductors, etc.), these inductive elements will store and release magnetic field energy when the switch is in action. If the switch is in action quickly, the energy released by the inductive element may cause a transient reverse voltage to be generated at the output end. And in a switching power supply or switching circuit, when the switch state changes, such as from on to off or from off to on, the change in current direction may cause a reverse voltage to be generated.

[0003] Typically, in a protection circuit for a load switch outputting a reverse voltage, a threshold or unidirectional conductivity of a diode is used to determine whether the output is reversed. However, the voltage drop of the diode is severely affected by temperature, resulting in poor judgment accuracy. Alternatively, a comparator is used to compare the output and input voltages. However, a series of circuit designs are required for the comparator, resulting in a high cost. Summary of the invention

[0004] The purpose of the present invention is to provide a reverse voltage protection circuit, aiming to improve the problems of poor accuracy and high use cost of the reverse voltage protection circuit.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A reverse voltage protection circuit includes a current modulation module, a reverse voltage detection module, a reverse blocking module and a driving system; the driving system includes a charge pump boost module, a power tube N1, a capacitor CL and a resistor RL;

[0007] The external power supply outputs VIN to the current modulation module, the reverse voltage detection module, the charge pump boost module, the reverse blocking module and the drain of the power tube N1;

[0008] The output end of the current modulation module outputs the first bias voltage VB101 and the second bias voltage VB102 to the reverse voltage detection module. The control end of the charge pump boost module is electrically connected to the gate of the power tube N1. The source of the power tube N1 outputs V OUTTo the input end of the reverse voltage detection module, one end of the capacitor CL, one end of the resistor RL and the charge pump boost module; the output end of the reverse voltage detection module outputs a protection signal RVP to the input end of the reverse blocking module, and the output end of the reverse blocking module is electrically connected to the input end of the charge pump boost module;

[0009] The grounding end of the current modulation module, the grounding end of the reverse voltage detection module, the grounding end of the reverse blocking module, the other end of the capacitor CL, the other end of the resistor RL and the substrate of the power tube N1 are all grounded.

[0010] Further, the current modulation module includes a current modulation unit and a current mirror output unit;

[0011] The current modulation unit includes an operational amplifier OP101, a MOS transistor P101, a MOS transistor N101, a MOS transistor N102, a MOS transistor N103, a MOS transistor N104, a MOS transistor N105, a MOS transistor N106, a triode Q101, a triode Q102, and a resistor R101, a resistor R102, and a resistor R103;

[0012] The external power supply output VIN is connected to the power supply terminal of the operational amplifier OP101, the source and substrate of the MOS tube P101, the base and collector of the transistor Q101, the base and collector of the transistor Q102, one end of the resistor R102, one end of the resistor R103 and the current mirror output unit;

[0013] The other end of the resistor R102 is electrically connected to the emitter of the transistor Q101, the drain of the MOS transistor N103 and the same-direction input terminal of the operational amplifier OP101, the other end of the resistor R103 is electrically connected to the reverse input terminal of the operational amplifier OP101, the output terminal of the operational amplifier OP101 is electrically connected to the gate of the MOS transistor P101, the drain of the MOS transistor P101 is electrically connected to the gate and drain of the MOS transistor N101, the gate of the MOS transistor N103, the gate of the MOS transistor N105 and the first input terminal of the current mirror output unit; the emitter of the transistor Q102 is electrically connected to one end of the resistor R101, the other end of the resistor R101 is electrically connected to the drain of the MOS transistor N105 and the reverse input terminal of the operational amplifier OP101;

[0014] The source of the MOS tube N101 is electrically connected to the drain and gate of the MOS tube N102, the gate of the MOS tube N104, the gate of the MOS tube N106, and the second input terminal of the current mirror output unit; the source of the MOS tube N103 is electrically connected to the drain of the MOS tube N104, and the source of the MOS tube N105 is electrically connected to the drain of the MOS tube N106;

[0015] The current mirror output unit outputs a bias voltage to a reverse voltage detection module;

[0016] The ground terminal of the operational amplifier OP101, the substrate of the MOS tube N101, the substrate of the MOS tube N103, the substrate of the MOS tube N105, the source and substrate of the MOS tube N102, the source and substrate of the MOS tube N104, and the source and substrate of the MOS tube N106 are all grounded.

[0017] Further, the current mirror output unit includes a MOS tube N107, a MOS tube N108, a MOS tube N109, a MOS tube N110, a MOS tube N111, a MOS tube N112 and a resistor R104;

[0018] The external power supply outputs VIN to one end of the resistor R104, and the other end of the resistor R104 is electrically connected to the drain of the MOS tube N107;

[0019] The drain of the MOS transistor P101 is electrically connected to the gates of the MOS transistor N107, the gates of the MOS transistor N109, and the gates of the MOS transistor N111, and outputs a first bias voltage VB101 to the reverse voltage detection module; the source of the MOS transistor N101 is electrically connected to the gates of the MOS transistor N108, the gates of the MOS transistor N110, and the gates of the MOS transistor N112, and outputs a second bias voltage VB102 to the reverse voltage detection module;

[0020] The source of the MOS tube N107 is electrically connected to the drain of the MOS tube N108, and the drain of the MOS tube N109 outputs an open-drain pull-down current I REF110 The source of the MOS tube N109 is electrically connected to the drain of the MOS tube N110, and the drain of the MOS tube N111 outputs an open-drain pull-down current I REF112 , the source of the MOS tube N111 is electrically connected to the drain of the MOS tube N112;

[0021] The substrate of the MOS tube N107, the substrate of the MOS tube N109, the substrate of the MOS tube N111, the source and substrate of the MOS tube N108, the source and substrate of the MOS tube N110, and the source and substrate of the MOS tube N112 are all grounded.

[0022] Further, the reverse voltage detection module includes a current mirror unit, a voltage comparison unit and a signal output unit;

[0023] The external power supply outputs VIN to the voltage comparison unit and the signal output unit; the output end of the current modulation module outputs the bias voltage to the current mirror module, and the source of the power tube N1 outputs V OUTTo the voltage comparison unit, the output end of the voltage comparison unit is electrically connected to the current mirror unit and the signal output unit, and the signal output unit outputs the protection signal RVP to the reverse blocking module.

[0024] Further, the current mirror unit includes MOS tube N201, MOS tube N202, MOS tube N203, MOS tube N204, MOS tube N205, and MOS tube N206;

[0025] The output end of the current modulation module outputs a first bias voltage VB101 to the gate of the MOS tube N201, the gate of the MOS tube N203, and the gate of the MOS tube N205; the output end of the current modulation module outputs a second bias voltage VB102 to the gate of the MOS tube N202, the gate of the MOS tube N204, and the gate of the MOS tube N206;

[0026] The source of the MOS tube N201 is electrically connected to the drain of the MOS tube N202, the source of the MOS tube N203 is electrically connected to the drain of the MOS tube N204, and the source of the MOS tube N205 is electrically connected to the drain of the MOS tube N206; the drain of the MOS tube N201, the drain of the MOS tube N203, and the drain of the MOS tube N205 are electrically connected to the voltage comparison unit;

[0027] The substrate of the MOS tube N201, the substrate of the MOS tube N203, the substrate of the MOS tube N205, the source and substrate of the MOS tube N202, the source and substrate of the MOS tube N204, and the source and substrate of the MOS tube N206 are all grounded.

[0028] Further, the voltage comparison unit includes MOS tube P201, MOS tube P202, MOS tube P203, MOS tube P204, MOS tube P205, and at least includes resistor R201, resistor R202, resistor R203, resistor R204, fuse FUSE201, fuse FUSE202;

[0029] The external power supply outputs VIN to one end of the resistor R204, the source and substrate of the MOS transistor P205, the substrate of the MOS transistor P201, and the substrate of the MOS transistor P202. The other end of the resistor R204 is electrically connected to the source of the MOS transistor P202, the drain of the MOS transistor P205, and the source and substrate of the MOS transistor P204. The gate of the MOS transistor P205 is electrically connected to the signal output unit.

[0030] The gate and drain of the MOS transistor P202 are electrically connected to the gate of the MOS transistor P201 and the current mirror unit, the gate of the MOS transistor P204 is electrically connected to the drain of the MOS transistor P201, the source of the MOS transistor P203 is electrically connected to the substrate, the drain of the MOS transistor P204 is electrically connected to the gate of the MOS transistor P203 and the current mirror unit, and the drain of the MOS transistor P203 is electrically connected to the signal output unit and the current mirror unit;

[0031] The resistor R201, the resistor R202 and the resistor R203 are sequentially connected in series between the source of the MOS tube P201 and the output end of the charge pump boost module, and the fuse FUSE201 and the fuse FUSE202 are connected to both ends of the resistor R202 and the resistor R203 respectively.

[0032] Further, the signal output unit includes MOS tube N207, MOS tube N208, MOS tube N209, MOS tube N210, MOS tube P206, MOS tube P207, inverter INV201, inverter INV202, inverter INV203, inverter INV204, inverter INV205, inverter INV206, inverter INV207, inverter INV208, inverter INV209, and NOR gate NOR201;

[0033] The external power supply outputs VIN to the source and substrate of the MOS transistor P206 and the source and substrate of the MOS transistor P207;

[0034] The output end of the current modulation module outputs the second bias voltage VB102 to the gate of the MOS tube N207, and the drain of the MOS tube N207 is electrically connected to the drain of the MOS tube P206; the inverter INV204, the inverter INV205, the inverter INV206, and the inverter INV207 are sequentially connected in series between the drain of the MOS tube P206 and the first input end of the NOR gate NOR201;

[0035] The gate of the MOS tube P207 is electrically connected to the gate of the MOS tube N208 and the gate of the MOS tube N209, and is electrically connected to the output end of the voltage comparison unit; the drain of the MOS tube P207 is electrically connected to the drain of the MOS tube N208 and the drain of the MOS tube N210; the inverter INV201, the inverter INV202, and the inverter INV203 are connected in series between the drain of the MOS tube P207 and the gate of the MOS tube P206; the drain of the MOS tube N209 is electrically connected to the drain of the MOS tube N208 and the drain of the MOS tube N210; The source of the MOS tube N210 is electrically connected, the gate of the MOS tube N210 is connected between the inverter INV201 and the inverter INV202, the output end of the inverter INV202 is electrically connected to the second input end of the NOR gate NOR201, the inverter INV208 and the inverter INV209 are sequentially connected in series to the output end of the NOR gate NOR201, the output end of the inverter INV209 outputs a protection signal RVP to the reverse blocking module, and the output end of the NOR gate NOR is electrically connected to the voltage comparison unit;

[0036] The substrate of the MOS tube N210, the source and substrate of the MOS tube N207, the source and substrate of the MOS tube N208, and the source and substrate of the MOS tube N209 are all grounded.

[0037] Further, the reverse blocking module includes MOS transistor P308, MOS transistor P309, MOS transistor P310, MOS transistor P311 and MOS transistor N301;

[0038] The external power supply outputs VIN to the substrates of the MOS tube P308, the substrates of the MOS tube P309, the substrates of the MOS tube P310, and the substrates of the MOS tube P311;

[0039] The output end of the reverse voltage detection module outputs a protection signal RVP to the gate of the MOS tube N301, the drain of the MOS tube N301 is electrically connected to the gate and drain of the MOS tube P311, the source of the MOS tube P311 is electrically connected to the gate and drain of the MOS tube P310, the source of the MOS tube P310 is electrically connected to the gate and drain of the MOS tube P309, the source of the MOS tube P309 is electrically connected to the gate and drain of the MOS tube P308, and the source of the MOS tube P308 is electrically connected to the charge pump boost module;

[0040] The source and substrate of the MOS tube N301 are both grounded.

[0041] Furthermore, the charge pump boost module includes a rectifying unit and a gate clamping unit;

[0042] The external power supply outputs VIN to the rectifier unit and the gate clamp unit, the external enable signal EN and the external clock signal CLK are input to the rectifier unit, the output end of the rectifier unit is electrically connected to the output end of the reverse blocking module, one end of the gate clamp unit and the gate of the power tube N1, and the other end of the gate clamp unit outputs V OUT To the input end of the reverse voltage detection module, one end of the capacitor CL, one end of the resistor RL and the source of the power tube N1.

[0043] Further, the rectifier unit includes a MOS tube P401 and a resistor R401, and at least includes a transistor Q401, a transistor Q402, a transistor Q403, a transistor Q404, a transistor Q405, a transistor Q406, a transistor Q407, a capacitor C401, a capacitor C402, a capacitor C403, a capacitor C404, a capacitor C405 and an inverter INV401, an inverter INV402, an inverter INV403, an inverter INV404, an inverter INV405, and an inverter INV406;

[0044] The external power supply outputs VIN to the source of the MOS tube P401, the gate of the MOS tube P401 is connected to the external enable signal EN, the drain of the MOS tube P401 is electrically connected to the collector, base and one end of the capacitor C401 of the transistor Q401, the emitter of the transistor Q401 is electrically connected to the collector, base and one end of the capacitor C402 of the transistor Q402, the emitter of the transistor Q402 is electrically connected to the collector, base and one end of the capacitor C403 of the transistor Q403, the emitter of the transistor Q403 is electrically connected to the collector of the transistor Q404, and the emitter of the transistor Q404 is electrically connected to the collector of the transistor Q404. The emitter of the transistor Q404 is electrically connected to the collector, base and one end of the capacitor C404, the emitter of the transistor Q404 is electrically connected to the collector, base and one end of the capacitor C405, the emitter of the transistor Q405 is electrically connected to the collector and base of the transistor Q406, the emitter of the transistor Q406 is electrically connected to the collector and base of the transistor Q407, the emitter of the transistor Q407 is electrically connected to one end of the resistor R401, and the other end of the resistor R401 is electrically connected to the output end of the reverse blocking module, one end of the gate clamping unit and the gate of the power tube N1;

[0045] The input end of the inverter INV401 is connected to the external clock signal CLK, the output end of the inverter INV401 is electrically connected to the input end of the inverter INV402, the output end of the inverter INV402 is electrically connected to the input end of the inverter INV403 and the other end of the capacitor C401, the output end of the inverter INV403 is electrically connected to the input end of the inverter INV404 and the other end of the capacitor C402, the output end of the inverter INV404 is electrically connected to the input end of the inverter INV405 and the other end of the capacitor C403, the output end of the inverter INV405 is electrically connected to the input end of the inverter INV406 and the other end of the capacitor C404, and the output end of the inverter INV406 is electrically connected to the other end of the capacitor C405;

[0046] The gate clamping unit includes a triode Q408, and at least includes a MOS transistor P402, a MOS transistor P403, a MOS transistor P404, a MOS transistor P405, a MOS transistor P406 and a MOS transistor P407;

[0047] The external power supply outputs VIN to the substrates of the MOS tube P402, the MOS tube P403, the MOS tube P404, the MOS tube P405, the MOS tube P406 and the MOS tube P407;

[0048] The base and collector of the transistor Q408 are electrically connected to the output end of the rectifier unit, the output end of the reverse blocking module and the gate of the power tube N1, the emitter of the transistor Q408 is electrically connected to the source of the MOS tube P402, the gate and drain of the MOS tube P402 are electrically connected to the source of the MOS tube P403, the gate and drain of the MOS tube P403 are electrically connected to the source of the MOS tube P404, the gate and drain of the MOS tube P404 are electrically connected to the source of the MOS tube P405, the gate and drain of the MOS tube P405 are electrically connected to the source of the MOS tube P406, the gate and drain of the MOS tube P406 are electrically connected to the source of the MOS tube P407, and the gate and drain of the MOS tube P407 output V OUT To the input end of the reverse voltage detection module, one end of the capacitor CL, one end of the resistor RL and the source of the power tube N1.

[0049] After adopting the above technical solution, the present invention has the following advantages compared with the background technology:

[0050] After the load switch is enabled, the current modulation module works to provide the first bias voltage VB101 and the second bias voltage VB102 for the reverse voltage detection module. The charge pump boost module boosts the gate voltage Vgate of the power tube N1 and drives the power tube N1 into the linear region to supply power to the external load. The reverse voltage detection module continuously detects the output voltage V OUT The output voltage VIN is compared with the input voltage VIN to accurately determine whether the output is reverse. OUT If it is greater than VIN and exceeds a certain range, the reverse voltage controls the reverse blocking module to work, clamps the gate Vgate voltage of the power tube N1, cuts off the power tube N1, blocks the input and output currents, and accurately judges the reverse voltage, providing timely protection for the circuit. Without using a comparator, the overall circuit structure is simple and the cost of use is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a block diagram of the reverse voltage protection circuit of the present invention;

[0052] Figure 2 A circuit diagram of a current modulation module of the reverse voltage protection circuit of the present invention;

[0053] Figure 3 A circuit diagram of a reverse voltage detection module of the reverse voltage protection circuit of the present invention;

[0054] Figure 4 A circuit diagram of a reverse blocking module and a charge pump boost module of the reverse voltage protection circuit of the present invention;

[0055] Figure 5 The reverse voltage protection circuit of the present invention has a Ta of 26°C, and the current modulation module generates I BIAS Current simulation diagram;

[0056] Figure 6 This is a simulation diagram of the protection signal RVP threshold value of the reverse voltage protection circuit of the present invention when VIN=5V, Ta=26°C;

[0057] Figure 7 This is a simulation diagram of the protection signal RVP threshold value of the reverse voltage protection circuit of the present invention when VIN=5V, Ta=-40°C;

[0058] Figure 8 This is a simulation diagram of the protection signal RVP threshold value of the reverse voltage protection circuit of the present invention when VIN=5V, Ta=125°C;

[0059] Fig. 9 This is a simulation diagram of the protection signal RVP threshold value of the reverse voltage protection circuit of the present invention when VIN=3V, Ta=26°C;

[0060] Fig.10 This is a simulation diagram of the protection signal RVP threshold value of the reverse voltage protection circuit of the present invention when VIN=3V, Ta=-40°C;

[0061] Fig.11 This is a simulation diagram of the protection signal RVP threshold when VIN=3V, Ta=125°C of the reverse voltage protection circuit of the present invention. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0063] In addition, it should be noted that the terms "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element of the present invention must have a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0064] When an element is referred to as being “fixed to” or “disposed on” or “provided on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0065] Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances. Example

[0066] Please refer to Figure 1-11 As shown, this embodiment provides a reverse voltage protection circuit, please refer to Figure 1As shown, it includes a current modulation module, a reverse voltage detection module, a reverse blocking module and a driving system; the driving system includes a charge pump boost module, a power tube N1, a capacitor CL and a resistor RL. The external power supply outputs VIN to the current modulation module, the reverse voltage detection module, the charge pump boost module, the reverse blocking module and the drain of the power tube N1. The output end of the current modulation module outputs the first bias voltage VB101 and the second bias voltage VB102 to the reverse voltage detection module, the control end of the charge pump boost module is electrically connected to the gate of the power tube N1, and the source of the power tube N1 outputs V OUT To the input end of the reverse voltage detection module, one end of the capacitor CL, one end of the resistor RL and the charge pump boost module. The output end of the reverse voltage detection module outputs a protection signal RVP to the input end of the reverse blocking module, and the output end of the reverse blocking module is electrically connected to the input end of the charge pump boost module. The ground end of the current modulation module, the ground end of the reverse voltage detection module, the ground end of the reverse blocking module, the other end of the capacitor CL, the other end of the resistor RL and the substrate of the power tube N1 are all grounded.

[0067] After the load switch is enabled, the current modulation module works to provide the first bias voltage VB101 and the second bias voltage VB102 for the reverse voltage detection module. The charge pump boost module boosts the gate voltage Vgate of the power tube N1 and drives the power tube N1 into the linear region to supply power to the external load. The reverse voltage detection module continuously detects the output voltage V OUT The output voltage VIN is compared with the input voltage VIN to accurately determine whether the output is reverse. OUT If it is greater than VIN and exceeds a certain range, the reverse voltage controls the reverse blocking module to work, clamps the gate voltage Vgate of the power tube N1, cuts off the power tube N1, blocks the input and output currents, and accurately judges the reverse voltage, providing timely protection for the circuit. Without using a comparator, the overall circuit structure is simple and the cost of use is low.

[0068] Please refer to Figure 2 As shown, specifically, the current modulation module includes a current modulation unit and a current mirror output unit; the current modulation unit includes an operational amplifier OP101, a MOS tube P101, a MOS tube N101, a MOS tube N102, a MOS tube N103, a MOS tube N104, a MOS tube N105, a MOS tube N106, a triode Q101, a triode Q102 and a resistor R101, a resistor R102, and a resistor R103.

[0069] The external power supply output VIN is connected to the power supply terminal of the operational amplifier OP101, the source and substrate of the MOS tube P101, the base and collector of the transistor Q101, the base and collector of the transistor Q102, one end of the resistor R102, one end of the resistor R103 and the current mirror output unit.

[0070] The other end of the resistor R102 is electrically connected to the emitter of the transistor Q101, the drain of the MOS transistor N103 and the non-inverting input terminal of the operational amplifier OP101, the other end of the resistor R103 is electrically connected to the reverse input terminal of the operational amplifier OP101, the output terminal of the operational amplifier OP101 is electrically connected to the gate of the MOS transistor P101, the drain of the MOS transistor P101 is electrically connected to the gate and drain of the MOS transistor N101, the gate of the MOS transistor N103, the gate of the MOS transistor N105 and the first input terminal of the current mirror output unit; the emitter of the transistor Q102 is electrically connected to one end of the resistor R101, and the other end of the resistor R101 is electrically connected to the drain of the MOS transistor N105 and the reverse input terminal of the operational amplifier OP101.

[0071] The source of the MOS tube N101 is electrically connected to the drain and gate of the MOS tube N102, the gate of the MOS tube N104, the gate of the MOS tube N106, and the second input end of the current mirror output unit; the source of the MOS tube N103 is electrically connected to the drain of the MOS tube N104, and the source of the MOS tube N105 is electrically connected to the drain of the MOS tube N106.

[0072] The current mirror output unit outputs the bias voltage to the reverse voltage detection module. The ground terminal of the operational amplifier OP101, the substrate of the MOS tube N101, the substrate of the MOS tube N103, the substrate of the MOS tube N105, the source and substrate of the MOS tube N102, the source and substrate of the MOS tube N104, and the source and substrate of the MOS tube N106 are all grounded.

[0073] Furthermore, the current mirror output unit includes MOS tubes N107, N108, N109, N110, N111, N112 and resistor R104. The external power supply output VIN is electrically connected to one end of the resistor R104, and the other end of the resistor R104 is electrically connected to the drain of the MOS tube N107.

[0074] The drain of the MOS transistor P101 is electrically connected to the gates of the MOS transistor N107, the gates of the MOS transistor N109, and the gates of the MOS transistor N111, and outputs a first bias voltage VB101 to the reverse voltage detection module; the source of the MOS transistor N101 is electrically connected to the gates of the MOS transistor N108, the gates of the MOS transistor N110, and the gates of the MOS transistor N112, and outputs a second bias voltage VB102 to the reverse voltage detection module.

[0075] The source of MOS tube N107 is electrically connected to the drain of MOS tube N108, and the drain of MOS tube N109 outputs an open-drain pull-down current I REF110 , the source of MOS tube N109 is electrically connected to the drain of MOS tube N110, and the drain of MOS tube N111 outputs an open-drain pull-down current I REF112 , the source of the MOS tube N111 is electrically connected to the drain of the MOS tube N112.

[0076] The substrate of the MOS tube N107, the substrate of the MOS tube N109, the substrate of the MOS tube N111, the source and substrate of the MOS tube N108, the source and substrate of the MOS tube N110, and the source and substrate of the MOS tube N112 are all grounded.

[0077] In this embodiment, MOS transistors N101 and N102, MOS transistors N103 and N104, MOS transistors N105 and N106, MOS transistors N107 and N108, MOS transistors N109 and N110, and MOS transistors N111 and N112 form a common-source common-gate current mirror, and meet the following conditions:

[0078] (W / L)N101: (W / L)N103: (W / L)N105: (W / L)N107: (W / L)N109: (W / L)N111=1:1:1:1:a:b;

[0079] (W / L)N102: (W / L)N104: (W / L)N106: (W / L)N108: (W / L)N110: (W / L)N112=1:1:1:1:a:b;

[0080] Wherein (W / L)Nn is the width-to-length ratio of the MOS tube Nn, that is, (W / L)N101 is the width-to-length ratio of the MOS tube N101; that is, the width-to-length ratios of the MOS tubes N101, N103, N105 and N107 are the same, the width-to-length ratio of the MOS tube N109 is a times the width-to-length ratio of the MOS tube N101, and the width-to-length ratio of the MOS tube N111 is b times the width-to-length ratio of the MOS tube N101; that is, the width-to-length ratios of the MOS tubes N102, N104, N106 and N108 are the same, the width-to-length ratio of the MOS tube N110 is a times the width-to-length ratio of the MOS tube N102, and the width-to-length ratio of the MOS tube N112 is b times the width-to-length ratio of the MOS tube N102, wherein a and b are positive integers greater than or equal to 1.

[0081] In this embodiment, the number of transistors Q101 connected in parallel is m=1, and the number of transistors Q102 connected in parallel is m=x, where x is a positive integer greater than 1.

[0082] The resistance ratio of the resistor R102 to the resistor R103 is 1:1.

[0083] Since (W / L)N101:(W / L)N103:(W / L)N105:(W / L)N107=1:1:1:1, (W / L)N102:(W / L)N104:(W / L)N106:(W / L)N108=1:1:1:1, according to the saturation current formula of the MOS tube:

[0084]

[0085] Among them I BIASNn is the current size of the MOS tube Nn, that is, the current sizes of the MOS tube N102, the MOS tube N104, the MOS tube N106, and the MOS tube N108 are equal.

[0086] The virtual short effect of the operational amplifier OP101 makes the reverse input voltage of the operational amplifier OP101 equal to the same input voltage. Since the resistance ratio of the resistor R102 and the resistor R103 is 1:1, the current flowing through the resistor R102 is consistent with the current flowing through the resistor R103, and the current flowing through the transistor Q101 is consistent with the current flowing through the transistor Q102, that is:

[0087]

[0088]

[0089]

[0090] Where V IN- To make the reverse input voltage of the operational amplifier OP101, VIN+ To make the same-direction input voltage of the operational amplifier OP101, V BEn is the threshold voltage of transistor Qn, that is, V BE101 is the threshold voltage of transistor Q101, V BE102 is the threshold voltage of transistor Q102.

[0091] From this we can get:

[0092]

[0093] Since the transistor's V BE Voltage and collector current I C , saturation current I S It has the following features:

[0094]

[0095] From this we can get:

[0096]

[0097] Where V T for:

[0098]

[0099] Where k is the Boltzmann constant and q is the electron charge. T It is proportional to the temperature T, so V T has a positive temperature coefficient, and the V BE The voltage has a negative temperature coefficient that is known to vary with the process.

[0100] From the above formula, it can be obtained that when the number of transistors Q102 connected in parallel is greater than 1, that is, when x is greater than 1, the resistance ratio of resistor R101 to resistor R102 can be set to use V T The positive temperature coefficient of V BE101 The negative temperature coefficient of I BIASN102 The remaining value in the current formula is the reciprocal of the temperature coefficient of resistance, which is the temperature coefficient of the 1 / R term.

[0101] The current is copied to the MOS tube N107 and MOS tube N108 branches through the current mirror, and the voltage drop of the resistor R104 is:

[0102]

[0103] Because I BIASN102 The only temperature coefficient left in the current formula is the 1 / R term. The temperature coefficient of the R / 1 term is introduced through the resistor R104. Then the temperature coefficient of the 1 / R term and the temperature coefficient of the R / 1 term in the above formula cancel each other out. Therefore, V R104It is a voltage with zero temperature coefficient.

[0104] In addition, the current modulation module can also provide an open-drain pull-down current I REF , the current mirrors of MOS tube N109 and MOS tube N110, MOS tube N111 and MOS tube N112, MOS tube N101 and MOS tube N102 have the following relationship:

[0105] (W / L)N101: (W / L)N109: (W / L)N111=1:a:b;

[0106] (W / L)N102: (W / L)N110: (W / L)N112=1:a:b;

[0107] Therefore:

[0108]

[0109] And I REFN110 ,I REFN112 with I BIASN102 Have the same characteristics.

[0110] Please refer to Figure 3 As shown, specifically, the reverse voltage detection module includes a current mirror unit, a voltage comparison unit and a signal output unit. The external power supply outputs VIN to the voltage comparison unit and the signal output unit; the output end of the current modulation module outputs the bias voltage to the current mirror module, and the source of the power tube N1 outputs V OUT To the voltage comparison unit, the output end of the voltage comparison unit is electrically connected to the current mirror unit and the signal output unit, and the signal output unit outputs the protection signal RVP to the reverse blocking module.

[0111] The current mirror unit includes MOS tube N201, MOS tube N202, MOS tube N203, MOS tube N204, MOS tube N205, and MOS tube N206. The output end of the current modulation module outputs the first bias voltage VB101 to the gate of MOS tube N201, the gate of MOS tube N203, and the gate of MOS tube N205; the output end of the current modulation module outputs the second bias voltage VB102 to the gate of MOS tube N202, the gate of MOS tube N204, and the gate of MOS tube N206; that is, the drain of MOS tube P101 is electrically connected to the gate of MOS tube N201, the gate of MOS tube N203, and the gate of MOS tube N205, and the source of MOS tube N101 is electrically connected to the gate of MOS tube N202, the gate of MOS tube N204, and the gate of MOS tube N206.

[0112] The source of MOS tube N201 is electrically connected to the drain of MOS tube N202, the source of MOS tube N203 is electrically connected to the drain of MOS tube N204, and the source of MOS tube N205 is electrically connected to the drain of MOS tube N206; the drain of MOS tube N201, the drain of MOS tube N203, and the drain of MOS tube N205 are electrically connected to the voltage comparison unit. The substrate of MOS tube N201, the substrate of MOS tube N203, the substrate of MOS tube N205, the source and substrate of MOS tube N202, the source and substrate of MOS tube N204, and the source and substrate of MOS tube N206 are all grounded.

[0113] Further, the voltage comparison unit includes MOS transistors P201, P202, P203, P204, and P205, and at least includes resistors R201, R202, R203, R204, fuses FUSE201, and FUSE202.

[0114] The external power supply output VIN is connected to one end of the resistor R204, the source and substrate of the MOS tube P205, the substrate of the MOS tube P201, and the substrate of the MOS tube P202. The other end of the resistor R204 is electrically connected to the source of the MOS tube P202, the drain of the MOS tube P205, and the source and substrate of the MOS tube P204. The gate of the MOS tube P205 is electrically connected to the signal output unit.

[0115] The gate and drain of MOS transistor P202 are electrically connected to the gate and current mirror unit of MOS transistor P201, that is, the gate and drain of MOS transistor P202 are electrically connected to the gate of MOS transistor P201 and the drain of MOS transistor N203. The gate of MOS transistor P204 is electrically connected to the drain of MOS transistor P201, the source of MOS transistor P203 is electrically connected to the substrate, and the drain of MOS transistor P204 is electrically connected to the gate and current mirror unit of MOS transistor P203, that is, the drain of MOS transistor P204 is electrically connected to the gate of MOS transistor P203 and the drain of MOS transistor N205. The drain of MOS transistor P203 is electrically connected to the signal output unit and the current mirror unit, that is, the drain of MOS transistor P203 is electrically connected to the drain of MOS transistor N201 and the current mirror unit.

[0116] The resistor R201, the resistor R202 and the resistor R203 are sequentially connected in series between the source of the MOS tube P201 and the output end of the charge pump boost module, and the fuse FUSE201 and the fuse FUSE202 are respectively connected to both ends of the resistor R202 and the resistor R203. In this embodiment, a resistor Rn and a fuse FUSEm are also included, where n is a positive integer greater than 4 and is sequentially connected in series with the resistor R201, the resistor R202 and the resistor R203, and m is a positive integer greater than 2 and is connected to both sides of the resistor Rn in a one-to-one correspondence, that is, more resistors and fuses can be set.

[0117] Further, the signal output unit includes MOS tube N207, MOS tube N208, MOS tube N209, MOS tube N210, MOS tube P206, MOS tube P207, inverter INV201, inverter INV202, inverter INV203, inverter INV204, inverter INV205, inverter INV206, inverter INV207, inverter INV208, inverter INV209, and NOR gate NOR201.

[0118] The external power supply outputs VIN to the source and substrate of the MOS transistor P206 and the source and substrate of the MOS transistor P207.

[0119] The output end of the current modulation module outputs the second bias voltage VB102 to the gate of the MOS tube N207, that is, the source of the MOS tube N101 is electrically connected to the gate of the MOS tube N207. The drain of the MOS tube N207 is electrically connected to the drain of the MOS tube P206. The inverter INV204, the inverter INV205, the inverter INV206, and the inverter INV207 are sequentially connected in series between the drain of the MOS tube P206 and the first input end of the NOR gate NOR201.

[0120] The gate of MOS transistor P207 is electrically connected to the gate of MOS transistor N208 and the gate of MOS transistor N209, and is electrically connected to the output end of the voltage comparison unit, that is, the gate of MOS transistor P207 is also electrically connected to the drain of MOS transistor P203. The drain of MOS transistor P207 is electrically connected to the drain of MOS transistor N208 and the drain of MOS transistor N210. Inverter INV201, inverter INV202, and inverter INV203 are sequentially connected in series between the drain of MOS transistor P207 and the gate of MOS transistor P206. The drain of MOS transistor N209 is electrically connected to the source of MOS transistor N210, and the gate of MOS transistor N210 is connected between inverter INV201 and inverter INV202. The output end of the inverter INV202 is electrically connected to the second input end of the NOR gate NOR201, the inverter INV208 and the inverter INV209 are sequentially connected in series to the output end of the NOR gate NOR201, and the output end of the inverter INV209 outputs the protection signal RVP to the reverse blocking module. The output end of the NOR gate NOR is electrically connected to the voltage comparison unit, that is, the output end of the NOR gate NOR is electrically connected to the gate of the MOS tube P205.

[0121] The substrate of the MOS tube N210, the source and substrate of the MOS tube N207, the source and substrate of the MOS tube N208, and the source and substrate of the MOS tube N209 are all grounded.

[0122] In this embodiment, the MOS transistor N101, the MOS transistor N102, the MOS transistor N201, the MOS transistor N202, the MOS transistor N203, the MOS transistor N204, the MOS transistor N205, the MOS transistor N206, and the MOS transistor N207 satisfy the following conditional formula:

[0123] (W / L)N101: (W / L)N201: (W / L)N203: (W / L)N205=2:4:4:1;

[0124] (W / L)N102: (W / L)N202: (W / L)N204: (W / L)N206: (W / L)N207=2:4:4:1:1.

[0125] MOS tube P201 and MOS tube P202 meet the following conditions:

[0126] (W / L)P201:(W / L)P202=1:1.

[0127] In this embodiment, MOS transistors P204, P205, and P206 form a common source amplifier, and MOS transistor P203 is connected with the common source amplifier in a negative feedback form to form a linear regulator, through which the voltage at node A is made equal to the voltage at node B. MOS transistors P207, N208, N209, and N210 form a hysteresis trigger.

[0128] When the source voltage of P201 is equal to the source voltage of P202, IBIASP201 is equal to IBIASP202. When the source voltage of P201 is less than the source voltage of P202, IBIASP201 is less than IBIASP202. When the source voltage of P201 is greater than the source voltage of P202, IBIASP201 is greater than IBIASP202.

[0129] According to I BIASN202 The formula is:

[0130]

[0131] Let V OUT Much smaller than V IN , then the source voltage of MOS tube P201 is so low that MOS tube P201 is cut off, so the D node is logic zero, and the linear voltage regulator circuit composed of MOS tube P204, MOS tube N207, MOS tube N208, and MOS tube P203. According to the current of the branch where MOS tube P203 is located, the on-resistance of MOS tube P203 is adaptively changed to keep the voltage of node A stable. However, no current flows through MOS tube P203, so the on-resistance Ro203 of MOS tube P203 is infinite, which means that the C node is logic high and MOS tube P203 is cut off. At the same time, MOS tube P201 is also cut off, causing node A to float, so the voltage of node A is any value that can make the common source amplifier output logic high, and this state will continue until V OUT Until the MOS tube P201 can be turned on.

[0132] With V OUT Slowly rising, MOS tube P201 gradually enters the saturation region, set V OUT This is equal to V IN . Because I BIASN202 :I BIASN204 =1:1andI BIASP201 :I BIASP202 =1:1, and at this time due to V OUT The current in the branch will generate a voltage drop on the resistor R201, so the source voltage of the MOS tube P201 is smaller than the source voltage of the MOS tube P202.

[0133] Then I BIASP201 <IBIASP202 =I BIASN204 =I BIASN202 At this time, the linear voltage regulator circuit will adaptively change the on-resistance Ro203 of the MOS tube P203 according to the current flowing through the MOS tube P203 to maintain the voltage at the A node equal to the voltage at the B node. The MOS tube P201 and the MOS tube P203 are regarded as a current source as a whole. The current I BIASP201 Less than I BIASN202 Therefore, at this time, the current mirrors of MOS tube N201 and MOS tube N202 are forced to enter linear mode, and node D outputs logic zero. Through the signal output unit, it can be known that the protection signal RVP outputs logic zero with the same polarity as the D node, and MOS tube P205 and MOS tube P206 are turned on when the protection signal RVP is logic zero.

[0134] With V OUT Then it rises until the source voltage of MOS tube P201 is equal to the source voltage of MOS tube P202. In this process, the linear voltage regulator circuit adjusts the resistance of MOS tube P203 to make the voltage of node A equal to the voltage of node B. Then the voltage drop of MOS tube P203 will become smaller and smaller, that is, the voltage of node D will continue to rise until the voltage of node D can trigger the subsequent hysteresis trigger to realize logic flip. Then the balance condition when the protection is triggered is:

[0135]

[0136] At the moment of protection triggering, the branch current is determined by MOS tube N201 and MOS tube N202. From the current modulation module, we can know that V OUT The voltage is a zero temperature coefficient voltage, that is, the protection triggering threshold is a zero temperature coefficient voltage.

[0137] Let V OUT When the source voltage of MOS tube P201 and MOS tube P202 is the same, it continues to increase. BIASP201 >I BIASP202 =I BIASN202 =I BIASN204, then the overall current source formed by MOS tube P201 and MOS tube P203 is greater than the current provided by MOS tube N201 and MOS tube N202, thereby forcing MOS tube P201 and MOS tube P203 to enter linear mode, causing node D to rise to the power supply voltage level. In addition, the voltage of node A will also rise during this process. Through the function of the amplifier, node C will accelerate the decline, causing MOS tube P203 to accelerate its entry into linear mode. Since the high resistance above node D is provided by MOS tube P201 and MOS tube P203 at the same time when the branch is balanced before, it can reach a balance with the high resistance of MOS tube N201 and MOS tube N202, and MOS tube P203 quickly enters linear mode, which accelerates the reduction of impedance above node D. Therefore, MOS tube P204, MOS tube P205, MOS tube P206, and MOS tube P203 strengthen the speed of node D rising when flipping upward, that is, the gain from node A to node D is positive, and the protection is triggered.

[0138] After the protection is triggered, the output feedback signal of the NOR gate NOR201 turns off the MOS tube P205, thereby reducing the source voltage of the MOS tube P202 and accelerating I BIASP201 Greater than I BIASP202 The process plays a positive feedback role to avoid V OUT 、V IN Signal fluctuations cause oscillations.

[0139] When the protection is triggered, V OUT When it starts to drop, the source voltage of MOS tube P202 will decrease by one V because the MOS tube P205 is cut off after the protection is triggered. R204 , and the current of resistor R204 is I BIASN204 with I BIASN206 Therefore, the equilibrium condition when the protection is released is:

[0140]

[0141] Through the current modulation module, it can be known that the protection release threshold is the zero temperature coefficient voltage. At this time, V OUT Specifically:

[0142]

[0143] When the protection is restored, the protection signal RVP is logic zero, causing the MOS tube P205 to be turned on, and the source voltage of the MOS tube P202 is V IN -V R204 It is instantly raised to V IN , which speeds up the process that the source voltage of MOS tube P201 is lower than the source voltage of MOS tube P202. OUT 、V IN Signal fluctuations cause oscillations.BIASP201 The current is less than I BIASN202 The current, then I BIASP201 with I BIASN202 The conflict will cause MOS tubes N201 and N202 to enter linear mode, and the impedance reduction below the D node will cause the voltage of the A node to drop. Therefore, the amplifier will increase the resistance of the MOS tube P203 to maintain the stability of the A node, and the impedance of the MOS tube P201 is approximately equal to the impedance of the MOS tube P202. Roughly speaking, the impedance of the MOS tube P203 is approximately equal to the impedance of the cascode current mirror of the MOS tube N203 and the MOS tube N204. In this way, an additional Ro203 high resistance is introduced above the D node. Therefore, when the MOS tubes P204, P205, P206, and P203 are flipped, the speed of the D node drop is enhanced, that is, the gain from the A node to the D node is positive, and the protection is fully restored.

[0144] At the same time, the reverse voltage detection module realizes off-chip adjustment. FUSE201, FUSE202, FUSEm, R202, R203, and Rn constitute a fuse adjustment circuit. The resistance value of resistor R201 is increased by blowing the fuse and connecting a resistor in series, so that the trigger threshold is increased. At the same time, the protection trigger threshold is still a zero temperature coefficient voltage after adjustment; the protection release threshold is adjusted by setting a fuse for resistor R204. Similarly, the protection release threshold is still a zero temperature coefficient voltage after adjustment.

[0145] Please refer to Figure 4 As shown, specifically, the reverse blocking module includes MOS transistors P308, P309, P310, P311 and N301. The external power supply outputs VIN to the substrates of MOS transistors P308, P309, P310 and P311.

[0146] The output end of the reverse voltage detection module outputs a protection signal RVP to the gate of the MOS tube N301, that is, the output end of the inverter INV209 is electrically connected to the gate of the MOS tube N301. The drain of the MOS tube N301 is electrically connected to the gate and drain of the MOS tube P311, the source of the MOS tube P311 is electrically connected to the gate and drain of the MOS tube P310, the source of the MOS tube P310 is electrically connected to the gate and drain of the MOS tube P309, the source of the MOS tube P309 is electrically connected to the gate and drain of the MOS tube P308, and the gate and source of the MOS tube P308 are electrically connected to the charge pump boost module. The source and substrate of the MOS tube N301 are both grounded.

[0147] Please refer to Figure 4As shown, specifically, the charge pump boost module includes a rectifier unit and a gate clamp unit. The external power supply outputs VIN to the rectifier unit and the gate clamp unit, the external enable signal EN and the external clock signal CLK are input to the rectifier unit, the output end of the rectifier unit is electrically connected to the output end of the reverse blocking module, one end of the gate clamp unit and the gate of the power tube N1, and the other end of the gate clamp unit outputs V OUT To the input end of the reverse voltage detection module, one end of the capacitor CL, one end of the resistor RL and the source of the power tube N1.

[0148] Specifically, the rectifier unit includes a MOS tube P401 and a resistor R401, and at least includes a transistor Q401, a transistor Q402, a transistor Q403, a transistor Q404, a transistor Q405, a transistor Q406, a transistor Q407, a capacitor C401, a capacitor C402, a capacitor C403, a capacitor C404, a capacitor C405 and an inverter INV401, an inverter INV402, an inverter INV403, an inverter INV404, an inverter INV405, and an inverter INV406.

[0149] The external power supply outputs VIN to the source of the MOS tube P401, and the gate of the MOS tube P401 is connected to the external enable signal EN. The drain of the MOS tube P401 is electrically connected to the collector, base and one end of the capacitor C401 of the transistor Q401. The emitter of transistor Q401 is electrically connected to the collector, base and one end of capacitor C402 of transistor Q402, the emitter of transistor Q402 is electrically connected to the collector, base and one end of capacitor C403 of transistor Q403, the emitter of transistor Q403 is electrically connected to the collector, base and one end of capacitor C404 of transistor Q404, the emitter of transistor Q404 is electrically connected to the collector, base and one end of capacitor C405 of transistor Q405, the emitter of transistor Q405 is electrically connected to the collector and base of transistor Q406, the emitter of transistor Q406 is electrically connected to the collector and base of transistor Q407, and the emitter of transistor Q407 is electrically connected to one end of resistor R401. The other end of the resistor R401 is electrically connected to the output end of the reverse blocking module, one end of the gate clamping unit and the gate of the power tube N1; that is, the other end of the resistor R401 is electrically connected to the gate and source of the MOS tube P308, one end of the gate clamping unit and the gate of the power tube N1.

[0150] The input end of the inverter INV401 is connected to the external clock signal CLK. The output end of the inverter INV401 is electrically connected to the input end of the inverter INV402, the output end of the inverter INV402 is electrically connected to the input end of the inverter INV403 and the other end of the capacitor C401, the output end of the inverter INV403 is electrically connected to the input end of the inverter INV404 and the other end of the capacitor C402, the output end of the inverter INV404 is electrically connected to the input end of the inverter INV405 and the other end of the capacitor C403, the output end of the inverter INV405 is electrically connected to the input end of the inverter INV406 and the other end of the capacitor C404, and the output end of the inverter INV406 is electrically connected to the other end of the capacitor C405. In this embodiment, it also includes a capacitor Cy, an inverter INVy, and a transistor Qy, where y is a positive integer greater than 7, and the base and collector of the transistor Qy-1 are electrically connected to the emitter of the previous transistor Qy-2, and the emitter of the transistor Qy-1 is electrically connected to the base and collector of the next transistor Qy; the capacitor Cy-1 is electrically connected between the output end of the inverter INVy-1 and the base of the transistor Qy-1, and the input end of the inverter INVy-1 is electrically connected to the output end of the previous inverter INVy-2, and the output end of the inverter INVy-1 is electrically connected to the input end of the next inverter INVy. That is, more groups of transistors, capacitors, and inverters can be set.

[0151] Further, the gate clamping unit includes a triode Q408 and at least includes a MOS transistor P402, a MOS transistor P403, a MOS transistor P404, a MOS transistor P405, a MOS transistor P406 and a MOS transistor P407.

[0152] The external power supply outputs VIN to the substrates of the MOS transistor P402 , the substrate of the MOS transistor P403 , the substrate of the MOS transistor P404 , the substrate of the MOS transistor P405 , the substrate of the MOS transistor P406 , and the substrate of the MOS transistor P407 .

[0153] The base and collector of transistor Q408 are electrically connected to the output end of the rectifier unit, the output end of the reverse blocking module and the gate of the power tube N1, that is, the collector and base of transistor Q408 are electrically connected to the gate of the power tube N1, the other end of the resistor R401 and the gate and source of MOS tube P308. The emitter of transistor Q408 is electrically connected to the source of MOS tube P402, the gate and drain of MOS tube P402 are electrically connected to the source of MOS tube P403, the gate and drain of MOS tube P403 are electrically connected to the source of MOS tube P404, the gate and drain of MOS tube P404 are electrically connected to the source of MOS tube P405, the gate and drain of MOS tube P405 are electrically connected to the source of MOS tube P406, the gate and drain of MOS tube P406 are electrically connected to the source of MOS tube P407, and the gate and drain of MOS tube P407 output V OUT To the input end of the reverse voltage detection module, one end of the capacitor CL, one end of the resistor RL and the source of the power tube N1.

[0154] In this embodiment, a MOS transistor Pz is further included, where z is a positive integer greater than 7, the source of the MOS transistor Pz-1 is electrically connected to the gate and drain of the previous MOS transistor Pz-2, the gate and drain of the MOS transistor Pz-1 are electrically connected to the source of the next MOS transistor Pz, and the gate and drain of the MOS transistor Pz output V OUT To the input end of the reverse voltage detection module, one end of the capacitor CL, one end of the resistor RL and the source of the power tube N1. That is, the gate clamping unit can be provided with more PMOS tubes.

[0155] Among them, transistors Q401, Q402, Q403, Q404, Q405, Qy, Q406 and Q407 act as rectifier diodes to V IN The voltage is rectified.

[0156] After the EN signal is enabled, the MOS tube P401 is turned on, and CLK is the clock signal. When the inverter connected to the capacitor outputs logic zero, these capacitors are charged by the power supply or the charge pumped by the previous stage. When the inverter outputs logic high, these capacitors pump charges to the next stage through the rectifier diode. Finally, the charge is accumulated through the resistor R401 to increase the gate voltage Vgate of the power tube N1.

[0157] When the gate voltage Vgate of the power tube N1 exceeds the set gate voltage threshold Vgate0:

[0158]

[0159] The gate charge of power tube N1 will be discharged to V through the gate clamp unit. OUTThe gate voltage Vgate of the power tube N1 is maintained at the gate voltage threshold Vgate0, and finally the power tube N1 works in the linear region:

[0160]

[0161] When the protection signal RVP is logic high, the MOS tube N301 is turned on, and the gate of the power tube N1 is discharged through the MOS tubes P308, P309, P310, P311, and N301, and the gate voltage Vgate is clamped at the Vgate1 level:

[0162]

[0163] When the output reverse voltage occurs, the output voltage, i.e., the source voltage of the power tube N1, is greater than the input voltage, i.e., the drain voltage of the power tube N1, and the input voltage V IN The minimum value is 3V, then the gate voltage of the power tube N1 is less than the source voltage of the power tube N1. The power tube is cut off, thereby blocking the input and output currents. In this embodiment, the substrate of the power tube N1 is connected to GND, so the voltages at both ends of the source and drain of the power tube N1 cannot pass through the parasitic body diode to the other end. When the output voltage drops and returns to normal, the protection signal RVP is logic zero to turn off the MOS tube N301, and the charge pump boost module boosts the gate voltage of the power tube N1 to Vgate0 to restore it to normal operation.

[0164] Please refer to Figure 5 As shown, attached Figure 5 is the I generated by the current modulation module when VIN=5V, Ta=26℃ BIASN202 ,I BIASN204 ,I BIASN206 The current size simulation diagram shows that I BIASN202 =2.7756uA, I BIASN204 =2.7756uA, I BIASN206 =702.51nA.

[0165] Please refer to Figure 6 As shown, attached Figure 6 This is the protection trigger and release threshold simulation diagram of the protection signal RVP when VIN=5V, Ta=26℃, resistance R201=84.565K, resistance R204=169.13K. Substitute the conditions into the threshold critical formula:

[0166]

[0167]

[0168] It is basically consistent with the simulation experiment diagram: VOUT V IN Trigger when high 0.233V, V OUT V IN Released at 0.353V.

[0169] Please refer to Figure 7 As shown, attached Figure 7 The protection signal RVP protection trigger and release threshold simulation diagram is shown in Figure 1 when VIN=5V, Ta=-40℃, and the resistance values ​​of resistors R201 and R204 are unchanged. It can be seen from the figure that the trigger threshold at -40℃ is 5.234V, and the release threshold is 4.647V, which is consistent with that at 26℃.

[0170] Please refer to Figure 8 As shown, attached Figure 8 The figure is a simulation diagram of the protection trigger and release threshold of the protection signal RVP when VIN=5V, Ta=125℃, and the resistance values ​​of resistors R201 and R204 are unchanged. It can be seen from the figure that the trigger threshold at 125℃ is 5.232V, and the release threshold is 4.648V, which is consistent with that at 26℃.

[0171] Please refer to Fig. 9 As shown, attached Fig. 9 The protection trigger and release threshold simulation diagram of the protection signal RVP when VIN=3V, Ta=26℃, and the resistance values ​​of resistors R201 and R204 are unchanged. IN =3V, Ta=26℃, the trigger threshold is 3.2333V, and the release threshold is 2.6477V, which is consistent with V IN =5V is consistent: V OUT V IN Trigger when high 0.233V, V OUT V IN Released at 0.353V.

[0172] Please refer to Fig.10 As shown, attached Fig.10 The protection trigger and release threshold simulation diagram of the protection signal RVP when VIN=3V, Ta=-40℃, and the resistance values ​​of resistors R201 and R204 are unchanged. IN =3V, the trigger threshold at Ta=-40℃ is 3.2337V, and the release threshold is 2.6481V, which is consistent with that at 26℃.

[0173] Please refer to Fig.11 As shown, attached Fig.11 The protection trigger and release threshold simulation diagram of the protection signal RVP when VIN=3V, Ta=125℃, and the resistance values ​​of resistors R201 and R204 are unchanged. IN=3V, the trigger threshold at Ta=125℃ is 3.2316V, and the release threshold is 2.647V, which is consistent with that at 26℃.

[0174] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A reverse voltage protection circuit, characterized in that: It includes a current modulation module, a reverse voltage detection module, a reverse blocking module and a driving system; the driving system includes a charge pump boost module, a power tube N1, a capacitor CL and a resistor RL; The external power supply outputs VIN to the current modulation module, the reverse voltage detection module, the charge pump boost module, the reverse blocking module and the drain of the power tube N1; The output end of the current modulation module outputs the first bias voltage VB101 and the second bias voltage VB102 to the reverse voltage detection module. The control end of the charge pump boost module is electrically connected to the gate of the power tube N1. The source of the power tube N1 outputs V OUT To the input end of the reverse voltage detection module, one end of the capacitor CL, one end of the resistor RL and the charge pump boost module; the output end of the reverse voltage detection module outputs a protection signal RVP to the input end of the reverse blocking module, and the output end of the reverse blocking module is electrically connected to the input end of the charge pump boost module; The ground end of the current modulation module, the ground end of the reverse voltage detection module, the ground end of the reverse blocking module, the other end of the capacitor CL, the other end of the resistor RL and the substrate of the power tube N1 are all grounded; The current modulation module includes a current modulation unit and a current mirror output unit; The current modulation unit includes an operational amplifier OP101, a MOS transistor P101, a MOS transistor N101, a MOS transistor N102, a MOS transistor N103, a MOS transistor N104, a MOS transistor N105, a MOS transistor N106, a triode Q101, a triode Q102, and a resistor R101, a resistor R102, and a resistor R103; The external power supply output VIN is connected to the power supply terminal of the operational amplifier OP101, the source and substrate of the MOS tube P101, the base and collector of the transistor Q101, the base and collector of the transistor Q102, one end of the resistor R102, one end of the resistor R103 and the current mirror output unit; The other end of the resistor R102 is electrically connected to the emitter of the transistor Q101, the drain of the MOS transistor N103 and the same-direction input terminal of the operational amplifier OP101, the other end of the resistor R103 is electrically connected to the reverse input terminal of the operational amplifier OP101, the output terminal of the operational amplifier OP101 is electrically connected to the gate of the MOS transistor P101, the drain of the MOS transistor P101 is electrically connected to the gate and drain of the MOS transistor N101, the gate of the MOS transistor N103, the gate of the MOS transistor N105 and the first input terminal of the current mirror output unit; the emitter of the transistor Q102 is electrically connected to one end of the resistor R101, the other end of the resistor R101 is electrically connected to the drain of the MOS transistor N105 and the reverse input terminal of the operational amplifier OP101; The source of the MOS tube N101 is electrically connected to the drain and gate of the MOS tube N102, the gate of the MOS tube N104, the gate of the MOS tube N106, and the second input terminal of the current mirror output unit; the source of the MOS tube N103 is electrically connected to the drain of the MOS tube N104, and the source of the MOS tube N105 is electrically connected to the drain of the MOS tube N106; The current mirror output unit outputs a bias voltage to a reverse voltage detection module; The ground terminal of the operational amplifier OP101, the substrate of the MOS tube N101, the substrate of the MOS tube N103, the substrate of the MOS tube N105, the source and substrate of the MOS tube N102, the source and substrate of the MOS tube N104, and the source and substrate of the MOS tube N106 are all grounded.

2. The reverse voltage protection circuit according to claim 1, characterized in that: The current mirror output unit includes a MOS tube N107, a MOS tube N108, a MOS tube N109, a MOS tube N110, a MOS tube N111, a MOS tube N112 and a resistor R104; The external power supply outputs VIN to one end of the resistor R104, and the other end of the resistor R104 is electrically connected to the drain of the MOS tube N107; The drain of the MOS transistor P101 is electrically connected to the gates of the MOS transistor N107, the gates of the MOS transistor N109, and the gates of the MOS transistor N111, and outputs a first bias voltage VB101 to the reverse voltage detection module; the source of the MOS transistor N101 is electrically connected to the gates of the MOS transistor N108, the gates of the MOS transistor N110, and the gates of the MOS transistor N112, and outputs a second bias voltage VB102 to the reverse voltage detection module; The source of the MOS tube N107 is electrically connected to the drain of the MOS tube N108, and the drain of the MOS tube N109 outputs an open-drain pull-down current I REF110 The source of the MOS tube N109 is electrically connected to the drain of the MOS tube N110, and the drain of the MOS tube N111 outputs an open-drain pull-down current I REF112 Until the source of the MOS tube N111 is electrically connected to the drain of the MOS tube N112; The substrate of the MOS tube N107, the substrate of the MOS tube N109, the substrate of the MOS tube N111, the source and substrate of the MOS tube N108, the source and substrate of the MOS tube N110, and the source and substrate of the MOS tube N112 are all grounded.

3. The reverse voltage protection circuit according to claim 1, characterized in that: The reverse voltage detection module includes a current mirror unit, a voltage comparison unit and a signal output unit; The external power supply outputs VIN to the voltage comparison unit and the signal output unit; the output end of the current modulation module outputs the bias voltage to the current mirror module, and the source of the power tube N1 outputs V OUT To the voltage comparison unit, the output end of the voltage comparison unit is electrically connected to the current mirror unit and the signal output unit, and the signal output unit outputs the protection signal RVP to the reverse blocking module.

4. The reverse voltage protection circuit according to claim 3, characterized in that: The current mirror unit includes MOS tube N201, MOS tube N202, MOS tube N203, MOS tube N204, MOS tube N205, and MOS tube N206; The output end of the current modulation module outputs a first bias voltage VB101 to the gate of the MOS tube N201, the gate of the MOS tube N203, and the gate of the MOS tube N205; the output end of the current modulation module outputs a second bias voltage VB102 to the gate of the MOS tube N202, the gate of the MOS tube N204, and the gate of the MOS tube N206; The source of the MOS tube N201 is electrically connected to the drain of the MOS tube N202, the source of the MOS tube N203 is electrically connected to the drain of the MOS tube N204, and the source of the MOS tube N205 is electrically connected to the drain of the MOS tube N206; the drain of the MOS tube N201, the drain of the MOS tube N203, and the drain of the MOS tube N205 are electrically connected to the voltage comparison unit; The substrate of the MOS tube N201, the substrate of the MOS tube N203, the substrate of the MOS tube N205, the source and substrate of the MOS tube N202, the source and substrate of the MOS tube N204, and the source and substrate of the MOS tube N206 are all grounded.

5. The reverse voltage protection circuit according to claim 3, characterized in that: The voltage comparison unit includes MOS tube P201, MOS tube P202, MOS tube P203, MOS tube P204, MOS tube P205, and at least includes resistor R201, resistor R202, resistor R203, resistor R204, fuse FUSE201, fuse FUSE202; The external power supply outputs VIN to one end of the resistor R204, the source and substrate of the MOS transistor P205, the substrate of the MOS transistor P201, and the substrate of the MOS transistor P202. The other end of the resistor R204 is electrically connected to the source of the MOS transistor P202, the drain of the MOS transistor P205, and the source and substrate of the MOS transistor P204. The gate of the MOS transistor P205 is electrically connected to the signal output unit. The gate and drain of the MOS transistor P202 are electrically connected to the gate of the MOS transistor P201 and the current mirror unit, the gate of the MOS transistor P204 is electrically connected to the drain of the MOS transistor P201, the source of the MOS transistor P203 is electrically connected to the substrate, the drain of the MOS transistor P204 is electrically connected to the gate of the MOS transistor P203 and the current mirror unit, and the drain of the MOS transistor P203 is electrically connected to the signal output unit and the current mirror unit; The resistor R201, the resistor R202 and the resistor R203 are sequentially connected in series between the source of the MOS tube P201 and the output end of the charge pump boost module, and the fuse FUSE201 and the fuse FUSE202 are connected to both ends of the resistor R202 and the resistor R203 respectively.

6. The reverse voltage protection circuit according to claim 3, characterized in that: The signal output unit includes MOS tube N207, MOS tube N208, MOS tube N209, MOS tube N210, MOS tube P206, MOS tube P207, inverter INV201, inverter INV202, inverter INV203, inverter INV204, inverter INV205, inverter INV206, inverter INV207, inverter INV208, inverter INV209, and NOR gate NOR201; The external power supply outputs VIN to the source and substrate of the MOS transistor P206 and the source and substrate of the MOS transistor P207; The output end of the current modulation module outputs the second bias voltage VB102 to the gate of the MOS tube N207, and the drain of the MOS tube N207 is electrically connected to the drain of the MOS tube P206; the inverter INV204, the inverter INV205, the inverter INV206, and the inverter INV207 are sequentially connected in series between the drain of the MOS tube P206 and the first input end of the NOR gate NOR201; The gate of the MOS tube P207 is electrically connected to the gate of the MOS tube N208 and the gate of the MOS tube N209, and is electrically connected to the output end of the voltage comparison unit; the drain of the MOS tube P207 is electrically connected to the drain of the MOS tube N208 and the drain of the MOS tube N210; the inverter INV201, the inverter INV202, and the inverter INV203 are connected in series between the drain of the MOS tube P207 and the gate of the MOS tube P206; the drain of the MOS tube N209 is electrically connected to the drain of the MOS tube N208 and the drain of the MOS tube N210; The source of the MOS tube N210 is electrically connected, the gate of the MOS tube N210 is connected between the inverter INV201 and the inverter INV202, the output end of the inverter INV202 is electrically connected to the second input end of the NOR gate NOR201, the inverter INV208 and the inverter INV209 are sequentially connected in series to the output end of the NOR gate NOR201, the output end of the inverter INV209 outputs a protection signal RVP to the reverse blocking module, and the output end of the NOR gate NOR is electrically connected to the voltage comparison unit; The substrate of the MOS tube N210, the source and substrate of the MOS tube N207, the source and substrate of the MOS tube N208, and the source and substrate of the MOS tube N209 are all grounded.

7. The reverse voltage protection circuit according to claim 1, characterized in that: The reverse blocking module includes MOS transistor P308, MOS transistor P309, MOS transistor P310, MOS transistor P311 and MOS transistor N301; The external power supply outputs VIN to the substrates of the MOS tube P308, the substrates of the MOS tube P309, the substrates of the MOS tube P310, and the substrates of the MOS tube P311; The output end of the reverse voltage detection module outputs a protection signal RVP to the gate of the MOS tube N301, the drain of the MOS tube N301 is electrically connected to the gate and drain of the MOS tube P311, the source of the MOS tube P311 is electrically connected to the gate and drain of the MOS tube P310, the source of the MOS tube P310 is electrically connected to the gate and drain of the MOS tube P309, the source of the MOS tube P309 is electrically connected to the gate and drain of the MOS tube P308, and the source of the MOS tube P308 is electrically connected to the charge pump boost module; The source and substrate of the MOS tube N301 are both grounded.

8. The reverse voltage protection circuit according to claim 1, characterized in that: The charge pump boost module includes a rectifying unit and a gate clamping unit; The external power supply outputs VIN to the rectifier unit and the gate clamp unit, the external enable signal EN and the external clock signal CLK are input to the rectifier unit, the output end of the rectifier unit is electrically connected to the output end of the reverse blocking module, one end of the gate clamp unit and the gate of the power tube N1, and the other end of the gate clamp unit outputs V OUT To the input end of the reverse voltage detection module, one end of the capacitor CL, one end of the resistor RL and the source of the power tube N1.

9. The reverse voltage protection circuit according to claim 8, characterized in that: The rectifier unit includes a MOS tube P401 and a resistor R401, and at least includes a transistor Q401, a transistor Q402, a transistor Q403, a transistor Q404, a transistor Q405, a transistor Q406, a transistor Q407, a capacitor C401, a capacitor C402, a capacitor C403, a capacitor C404, a capacitor C405 and an inverter INV401, an inverter INV402, an inverter INV403, an inverter INV404, an inverter INV405, and an inverter INV406; The external power supply outputs VIN to the source of the MOS tube P401, the gate of the MOS tube P401 is connected to the external enable signal EN, the drain of the MOS tube P401 is electrically connected to the collector, base and one end of the capacitor C401 of the transistor Q401, the emitter of the transistor Q401 is electrically connected to the collector, base and one end of the capacitor C402 of the transistor Q402, the emitter of the transistor Q402 is electrically connected to the collector, base and one end of the capacitor C403 of the transistor Q403, the emitter of the transistor Q403 is electrically connected to the collector of the transistor Q404, and the emitter of the transistor Q404 is electrically connected to the collector of the transistor Q404. The emitter of the transistor Q404 is electrically connected to the collector, base and one end of the capacitor C404, the emitter of the transistor Q404 is electrically connected to the collector, base and one end of the capacitor C405, the emitter of the transistor Q405 is electrically connected to the collector and base of the transistor Q406, the emitter of the transistor Q406 is electrically connected to the collector and base of the transistor Q407, the emitter of the transistor Q407 is electrically connected to one end of the resistor R401, and the other end of the resistor R401 is electrically connected to the output end of the reverse blocking module, one end of the gate clamping unit and the gate of the power tube N1; The input end of the inverter INV401 is connected to the external clock signal CLK, the output end of the inverter INV401 is electrically connected to the input end of the inverter INV402, the output end of the inverter INV402 is electrically connected to the input end of the inverter INV403 and the other end of the capacitor C401, the output end of the inverter INV403 is electrically connected to the input end of the inverter INV404 and the other end of the capacitor C402, the output end of the inverter INV404 is electrically connected to the input end of the inverter INV405 and the other end of the capacitor C403, the output end of the inverter INV405 is electrically connected to the input end of the inverter INV406 and the other end of the capacitor C404, and the output end of the inverter INV406 is electrically connected to the other end of the capacitor C405; The gate clamping unit includes a triode Q408, and at least includes a MOS transistor P402, a MOS transistor P403, a MOS transistor P404, a MOS transistor P405, a MOS transistor P406 and a MOS transistor P407; The external power supply outputs VIN to the substrates of the MOS tube P402, the MOS tube P403, the MOS tube P404, the MOS tube P405, the MOS tube P406 and the MOS tube P407; The base and collector of the transistor Q408 are electrically connected to the output end of the rectifier unit, the output end of the reverse blocking module and the gate of the power tube N1, the emitter of the transistor Q408 is electrically connected to the source of the MOS tube P402, the gate and drain of the MOS tube P402 are electrically connected to the source of the MOS tube P403, the gate and drain of the MOS tube P403 are electrically connected to the source of the MOS tube P404, the gate and drain of the MOS tube P404 are electrically connected to the source of the MOS tube P405, the gate and drain of the MOS tube P405 are electrically connected to the source of the MOS tube P406, the gate and drain of the MOS tube P406 are electrically connected to the source of the MOS tube P407, and the gate and drain of the MOS tube P407 output V OUT To the input end of the reverse voltage detection module, one end of the capacitor CL, one end of the resistor RL and the source of the power tube N1.

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