Wireless energy supply receiving circuit

Abstract

The invention discloses a wireless energy supply receiving circuit, which relates to the technical field of integrated circuits, and comprises an active rectifier of which the input end is connected with two ends of a receiving coil on an in-vivo chip, the active rectifier comprises a pair of PMOS (P-channel Metal Oxide Semiconductor) power tubes and NMOS (N-channel Metal Oxide Semiconductor) power tubes NM1 and NM2 which are cross-coupled, and two adaptive voltage feedback circuits of which the input ends are respectively connected with grid electrodes of the NMOS power tubes NM1 and NM2, and each hybrid grid control circuit comprises a common-gate comparator, a rising edge detection circuit, a voltage-controlled delay circuit, a first SR latch and a driving circuit. The implant is a complete implant, no extra battery is needed for power supply, the size of the implant is greatly reduced, and the burden on the body of a patient is smaller.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a wireless power supply receiving circuit. Background Art

[0002] In the past few decades, with the rapid development of semiconductor technology, wireless technology, and the introduction of emerging technologies and concepts such as the Internet of Things, big data, and artificial intelligence, implantable medical devices have gradually entered people's field of vision and played a huge role. In the application of invasive brain-computer interfaces, it is only necessary to implant a highly integrated medical device into the body, and the electrical signals generated by the brain can be monitored and utilized through the chip. At present, most implantable medical devices are driven by batteries with limited life (i.e., the energy supply is active), and the batteries must be replaced regularly or the batteries integrated in the implanted devices must be wirelessly charged. Such devices are too large and will impose a burden on the patient's body and economy. Summary of the invention

[0003] Based on the above defects of the prior art, the present invention provides a wireless energy receiving circuit, which solves the problem that the existing implantable medical devices are too large and will bring physical and financial burdens to patients.

[0004] The present invention adopts the following technical solutions:

[0005] The present invention provides a wireless energy supply receiving circuit, comprising:

[0006] The active rectifier has an input end connected to the two ends of the receiving coil L2 on the chip in the body. The active rectifier includes a pair of cross-coupled PMOS power tubes and NMOS power tubes NM1 and NM2. The drains of the NMOS power tubes NM1 and NM2 are respectively used to receive the AC input signal V WP and V WN The source of the PMOS power tube is used to generate a DC voltage V REC ;

[0007] Two adaptive voltage feedback circuits, whose input terminals are connected to the gates of NMOS power tubes NM1 and NM2 respectively, adjust V WP and V WN Sampling is performed and based on V WP and V WN Generates the feedback voltage V at the turn-on time FB ON and the feedback voltage V at the turn-off time FB OFF ;

[0008] Two hybrid gate control circuits, each of which includes a common gate comparator, a rising edge detection circuit, a voltage-controlled delay circuit, a first SR latch and a drive circuit; the common gate comparator is used to receive V FB_ON , according to V FB_ON With the corresponding V WP or V WN The comparison generates the delay when the NMOS power tubes NM1 and NM2 are turned on, and the delay is connected to the set end of the first SR latch after passing through the rising edge detection circuit; the voltage-controlled delay chain circuit is used to receive V FB_OFF , according to V FB_OFF Generate a delay when the NMOS power tubes NM1 and NM2 are turned off, and the delay is connected to the reset end of the first SR latch; the output end of the first SR latch drives the gate voltage V of the NMOS power tubes NM1 and NM2 after passing through the driving circuit GP and V GN .

[0009] Preferably, the receiving coil L2 is used to receive an AC signal transmitted by an external wireless function transmitting circuit, and the wireless function transmitting circuit includes an MCU, a power amplifier and an LC network. The MCU controls the power amplifier to transmit the AC signal, and the AC signal is coupled to the receiving coil L2 on the internal chip through the transmitting coil L1 of the LC network.

[0010] Preferably, the drains of the two PMOS power tubes are respectively connected to the drains of the NMOS power tubes NM1 and NM2, the gates are respectively connected to the drains of the NMOS power tubes NM1 and NM2 after crossing, and the sources of the NMOS power tubes NM1 and NM2 are grounded.

[0011] Preferably, each of the adaptive voltage feedback circuits includes a sampling and holding circuit, a level shifting circuit, a window voltage comparator and an integrator; the sampling and holding circuit includes a switching capacitor circuit, a rising edge pulse generator, a falling edge pulse generator and a second SR latch; the gate voltages of the NMOS power tubes NM1 and NM2 generate a timing control voltage after passing through the pulse generator and the second SR latch; the output of the second SR latch is connected to and controls the switch of the switching capacitor circuit; the input of the switching capacitor circuit is connected to the two ends of the receiving coil, and the voltages at the two ends are sampled and held according to the timing changes; the output of the sampling and holding circuit is connected to the input of the level shifter; the level shifter is composed of four PMOS source followers, and its output is connected to the input of the window comparator; the window comparator is composed of two open-loop error amplifiers, and its output is connected to the input of the integrator; the integrator is composed of a PMOS tube, an NMOS tube, a current source and a load capacitor, and its output is connected to the mixed gate control circuit as the output of the adaptive feedback circuit.

[0012] Preferably, the positive input terminal of the common gate comparator is used to receive VFB_ON , the negative input terminal corresponds to V WP or V WN The output end is connected to one end of the rising edge detection circuit and one end of the voltage-controlled delay circuit; the other end of the rising edge detection circuit is connected to the set end of the first SR latch; one end of the voltage-controlled delay circuit is also used to receive V FB_OFF , and the other end is connected to the reset end of the first SR latch; the output end of the drive circuit is connected to the gate of the NMOS power tube NM1 or NM2.

[0013] Preferably, the output end of the active rectifier is connected in parallel with a load capacitor C L As well as the load resistors R1 and R2, the load capacitor C L One end is connected to the source of the PMOS power tube, and the other end is grounded; the load resistors R1 and R2 are connected in series, one end of R1 is connected to the source of the PMOS power tube, and the other end is grounded.

[0014] Preferably, the wireless power supply receiving circuit further includes a load power detection and modulation circuit, and the load power detection and modulation circuit includes a resistor R3, a load power detection tube N OVP , error amplifier and analog-to-digital converter, one end of the resistor R3 is connected to the source of the PMOS power tube, and the other end is connected to the load power detection tube N OVP The drain terminal V OVP Connection; the positive input terminal of the error amplifier is connected between the load resistors R1 and R2, and the negative input terminal is connected to the reference voltage V ref The load power detection tube N OVP The source of the current is grounded, the gate is connected to the output of the error amplifier, the drain and the output of the active rectifier are connected to the input of the analog-to-digital converter, and the output of the analog-to-digital converter D OUT , which is used to reflect the change of load power and feed back to the MCU of the wireless power supply transmission circuit to generate corresponding logic output to control the output power of the power amplifier.

[0015] Compared with the prior art, at least one of the above technical solutions adopted by the present invention can achieve the following beneficial effects:

[0016] The wireless power supply receiving circuit of the present invention is a receiving end of a wireless power transmission circuit based on a single coil, including an active rectifier, an adaptive voltage feedback circuit and a hybrid gate control circuit, receiving an AC input signal of an in vitro chip through a single coil, inputting the AC input signal to the active rectifier, the active rectifier including a cross-coupled PMOS power tube and NMOS power tubes NM1 and NM2, inputting the gate voltage of the NMOS power tubes NM1 and NM2 to the adaptive voltage feedback circuit, controlling its timing to sample the AC input signal and generate a feedback voltage at the turn-on time and a feedback voltage at the turn-off time, inputting the feedback voltage at the turn-on time and the feedback voltage at the turn-off time to the hybrid gate control circuit to drive the gate voltage of the NMOS power tubes NM1 and NM2 in the active rectifier, and finally outputting a DC voltage through the PMOS power tube of the active rectifier. The present invention is a complete implant, does not require an additional battery to power, greatly saves the volume of the implant, and brings less physical burden to the patient. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of an application environment of a wireless energy supply receiving circuit of the present invention;

[0019] Figure 2 A transistor-level schematic diagram of a wireless energy receiving circuit of the present invention;

[0020] Figure 3 The hybrid gate control circuit and the adaptive voltage feedback circuit schematic diagram and timing sequence of the present invention;

[0021] Figure 4 is a circuit schematic diagram of the level shift circuit of the present invention;

[0022] Figure 5 is a circuit schematic diagram of a window voltage comparator of the present invention;

[0023] Figure 6 is a circuit schematic diagram of an integrator of the present invention;

[0024] Figure 7 is a transistor-level circuit diagram of a common-gate comparator of the present invention;

[0025] Figure 8 It is a transistor-level circuit diagram of the voltage-controlled delay circuit of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In order to solve the deficiencies of the prior art, the present invention provides a wireless power supply receiving circuit.

[0028] like Figure 1 As shown, this embodiment provides a wireless power supply circuit of an invasive brain-computer interface and its application environment. The user controls the first MCU in the external chip to control the power amplifier to transmit a signal. The AC signal passing through the LC network is coupled to the receiving coil L2 on the internal chip through the transmitting coil L1, and the signal V at both ends of the receiving coil WP and V WN The AC input signal of the present invention includes an adaptively regulated active rectifier (composed of an active rectifier, two hybrid gate control circuits and two adaptive voltage feedback circuits) and a load power detection and modulation circuit. WP and V WN After processing, it is converted into a DC output signal V REC The structures of the two hybrid gate control circuits are identical and symmetrical to each other, and the structures of the two adaptive voltage feedback circuits are identical and symmetrical to each other.

[0029] Furthermore, to further explain the working principle of the wireless power supply receiving circuit in detail, Figure 2 The transistor-level schematic diagram of the wireless power supply receiving circuit used in invasive brain-computer interface is shown. The input end of the active rectifier is connected to the two ends of the receiving coil L2 on the chip in the body. It includes a pair of cross-coupled PMOS power tubes and NMOS power tubes NM1 and NM2. The drains of the NMOS power tubes NM1 and NM2 are used to receive the AC input signal V WP and V WN , the source of the PMOS power tube is used to generate a DC voltage V REC The gate voltage V of NMOS power tubes NM1 and NM2 GP and V GN As the input of the adaptive voltage feedback circuit, it controls the sampling timing and samples the other two inputs VWP and VWN.

[0030] Reference Figure 2The input terminals of the two adaptive voltage feedback circuits are connected to the gates of the NMOS power tubes NM1 and NM2 respectively. The gate voltages of NM1 and NM2 are changed to adjust the voltage of V WP and V WN Sampling is performed and based on V WP and V WN Generates the feedback voltage V at the turn-on time FB_ON and the feedback voltage V at the turn-off time FB_OFF .

[0031] The adaptive voltage feedback circuit generates the feedback voltage V at the turn-on time. FB_ON , determines the comparator's discrimination level to compensate for the transmission delay during the conduction process; the feedback voltage V at the turn-off time FB_OFF Determines how long the comparator rising edge is delayed, controls the first SR latch to output a low level, and turns off the NMOS power tube. For the conduction process, when the active diode is turned on ahead of the ideal conduction time, the V generated by the adaptive feedback circuit FB_ON The comparator starts to compare later, and the conduction time of the active diode is delayed, so that it gradually approaches the ideal conduction time. When the active diode is turned on later than the ideal conduction time, V FB_ON When the active diode turns off earlier than the ideal turn-off time, the V generated by the adaptive feedback circuit FB_OFF When V increases, the delay of the voltage-controlled delay circuit increases, and the turn-off time of the active diode is delayed, approaching the ideal turn-off time; when the active diode is turned off later than the ideal turn-off time, V FB_OFF The hybrid delayed gate voltage control structure avoids the problem of multiple pulses and can establish stability in a shorter time.

[0032] During the on-process, after detecting the rising edge of the comparator, the rising edge detection circuit generates a pulse to control the first SR latch to output a high level, turning on the NMOS power tube. During the off-process, the rising edge of the comparator is delayed by the voltage-controlled delay circuit, causing the first SR latch to output a low level, turning off the NMOS power tube. Therefore, the rising edge of the comparator determines the on-time, and the delay generated by the voltage-controlled delay circuit determines the off-time.

[0033] Each hybrid gate control circuit includes a common gate comparator, a rising edge detection circuit, a voltage-controlled delay circuit, a first SR latch and a driving circuit; the common gate comparator is used to receive V FB_ON , according to V FB_ON With the corresponding V WP or V WN The comparison generates the delay when the NMOS power tubes NM1 and NM2 are turned on. The delay is connected to the set end of the first SR latch after passing through the rising edge detection circuit; the voltage-controlled delay chain circuit is used to receive VFB_OFF , according to V FB_OFF Generate a delay when the NMOS power tubes NM1 and NM2 are turned off, and the delay is connected to the reset end of the first SR latch; the output end of the first SR latch drives the gate voltage V of the NMOS power tubes NM1 and NM2 after passing through the driving circuit GP and V GN The common gate comparator’s discrimination level and the delay of the voltage-controlled delay circuit are adjusted by adaptive feedback voltage. The positive input of the common gate comparator is used to receive V FB_ON , the negative input terminal corresponds to V WP or V WN The output end is connected to one end of the rising edge detection circuit and one end of the voltage-controlled delay circuit; the other end of the rising edge detection circuit is connected to the set end of the first SR latch; one end of the voltage-controlled delay circuit is also used to receive V FB_OFF , and the other end is connected to the reset end of the first SR latch; the output end of the drive circuit is connected to the gate of the NMOS power tube NM1 or NM2.

[0034] Load capacitance C L , load resistors R1 and R2 are connected in parallel at the output of the active rectifier, and load capacitor C L One end is connected to the source of the PMOS power tube, and the other end is grounded; the load resistors R1 and R2 are connected in series, one end of R1 is connected to the source of the PMOS power tube, and the other end is grounded.

[0035] Reference Figure 3-Figure 6 Each adaptive voltage feedback circuit includes a sampling and holding circuit, a level shifting circuit, a window voltage comparator and an integrator. The sampling and holding circuit includes a switching capacitor circuit, a rising edge pulse generator, a falling edge pulse generator and a second SR latch. The gate voltage of the NMOS power tubes NM1 and NM2 generates a timing control voltage after passing through the pulse generator and the second SR latch. The output of the second SR latch is connected to and controls the switch of the switching capacitor circuit. The input of the switching capacitor circuit is connected to the two ends of the receiving coil, and the voltages at the two ends are sampled and held according to the timing change; the output of the sampling and holding circuit is connected to the input of the level shifter; the level shifter is composed of four PMOS source followers, and its output is connected to the input of the window comparator; the window comparator is composed of two open-loop error amplifiers, and its output is connected to the input of the integrator; the integrator is composed of a PMOS tube, an NMOS tube, a current source and a load capacitor, and its output is connected to the hybrid gate control circuit as the output of the adaptive feedback circuit.

[0036] In order to show the working timing of the circuit more clearly, Figure 3 The circuit diagram is simplified and the timing of the circuit is shown. At the turn-on moment of NM1, that is, V GP The rising edge of V WP Sampling, VWP If the actual turn-on time is ahead of the ideal turn-on time, V WP If it is negative, the actual turn-on time is later than the ideal turn-on time. At the turn-off time of NM1, that is, V GP At the falling edge of V WP If it is negative, the actual shutdown time is ahead of the ideal shutdown time, V WP If the actual turn-on time is positive, it is later than the ideal turn-off time. The judgment of the turn-on and turn-off time of NM2 can be obtained in the same way. GN The rising edge of V WN sampling.

[0037] To V WP Take the sample and hold circuit as an example. Figure 3 As shown, at V GN The falling edge will ON_P / S OFF_P Open, the voltage on C1 and C2 follows V WP . In V GP The rising edge turns off S ON_P , C1 is sampled to get V GP V at the rising edge WP Voltage V SH_ON ; In V GP The falling edge turns off S OFF_P , C2 upsamples to get V GP V at the falling edge WP Voltage V SH_OFF In the next cycle V GN When high, turn on S HOLD_P , C1 and C3 share the charge, and the sampled voltage at the turn-on time is stored in C3; C2 and C4 share the charge, and the sampled voltage at the turn-off time is stored in C4. Similarly, we can get V WN The sample and hold circuit logic.

[0038] In V GP / V GN The V sampled on the rising and falling edges SH_ON / V SH_OFF The voltage is close to zero, and the comparator cannot be used directly to determine the magnitude relationship with the zero level. A level shift circuit is needed to move the sampling level and the zero level to the appropriate common mode. The structure of the level shift circuit is as follows: Figure 4 As shown. Under the same current bias, the 0 level is passed through a large source follower input tube to generate V L ; Then use a small source follower input tube to generate V H ; V SH_ON / V SH_OFF Through an input tube of intermediate size, V LS_ON / V LS_OFF, by adjusting the input tube size, set a reasonable V H With V L Interval: If the interval is too small, it is difficult to establish a stable feedback loop. If the interval is too large, there will be a large error in the turn-on and turn-off times, causing the PCE to decrease.

[0039] The window voltage comparator and integrator structures are as follows: Figure 5 and Figure 6 As shown. After level shifting, the sampled voltage is combined with the two window voltages V H / V L By comparing, we can determine whether the turn-on and turn-off moments of the active diode are ahead or behind. Taking the turn-on moment as an example, when V LS_ON In V H and V L In the middle, the active diode is considered to be turned on at the ideal time, and the window comparator outputs V DN / V UP are low level and high level respectively, the capacitor is not charged or discharged, V FB The voltage remains stable. When V LS Greater than V H When the active diode is considered to be turned on first, the window comparator outputs V DN / V UP Both are high level, the capacitor is discharged, V FB Voltage drops. When V LS Less than V L When the active diode is considered to be turned on with hysteresis, the window comparator outputs V DN / V UP Both are low level, the capacitor is charged, V FB The voltage rises. The integrator generates V FB The voltage is used as the input of the hybrid gate control circuit to control the hybrid gate control circuit to generate compensation delay until V WP / V WN It approaches 0 at the turn-on and turn-off moments, or is controlled within the window voltage.

[0040] The key circuits in the hybrid gate control circuit are the common gate comparator and the voltage-controlled delay circuit. Figure 7 This is the common gate comparator of the present invention. The two sources on the right are V WP or V WN The left source is connected to the V generated by the adaptive feedback circuit. FB_ON , but the feedback voltage has no driving capability, so the leftmost circuit is added to provide a driving capability and output voltage that follows V FB_ON The current flowing through PM1 / PM2 is the same as I. When V W Higher than V FB_ON When V G1 Higher than VG2 , the current of NM4 is higher than the current of NM2, that is, higher than I; the current of NM3 is lower than the current of NM2, that is, lower than I. From the mirror image relationship of the current mirror, it can be seen that the current of PM4 is lower than I. For NM4 and PM4, NM4 is a strong current source, so the comparator outputs V CMP_OUT V FB_ON , after passing through the buffer, the output is low level; similarly, when V W Lower than V FB_ON When V FB_ON is the discrimination level of the comparator, which can be adjusted by V FB_ON To adjust the comparator comparison time.

[0041] Figure 8 It is a voltage-controlled delay circuit, PM2 is equivalent to V FB_OFF The voltage-controlled current source is controlled. When the comparator level changes from low to high, NM1 is turned off, PM1 is turned on, and the current source charges the capacitor. D After reaching the buffer's flip level, the buffer outputs a high voltage. FB_OFF Adjust the current source current to adjust the delay.

[0042] Refer again Figure 1 , the load power detection and modulation circuit detects the voltage V on the load resistor R2 OVP , the detected data D OUT The signal is transmitted to the second MCU and controls transistor M after passing through the uplink data modulator. L The rectifier input is short-circuited, and the change of reflected impedance will cause the current of the transmitting coil L1 to increase rapidly, resulting in an increase in the swing of the AC signal on the transmitting coil L1. The signal will be filtered and rectified in the uplink data demodulator to obtain an average value. Once the average value exceeds a certain threshold, it means that the power at the load end is too large, and then the signal is fed back to the first MCU to reduce the transmitting power of the power amplifier, thereby achieving the purpose of adjusting the load power and saving energy.

[0043] Conventional active rectifiers can only achieve high power conversion efficiency under specific load conditions. Once the load changes, the working condition of the circuit will change. Therefore, the present invention adopts a load power detection and modulation circuit to meet high-efficiency operation under different load conditions. This circuit can adaptively adjust the active rectifier through a hybrid gate control circuit, so that the power conversion efficiency of the active rectifier reaches 94%; at the same time, the detected load power data is fed back to the wireless power supply transmitter to achieve the purpose of adjusting the transmitter power to save energy. At the same time, this circuit can be combined with related communication circuits to achieve a perfect combination of wireless power supply and communication.

[0044] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0045] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A wireless power supply receiving circuit, characterized in that: include: The active rectifier has an input end connected to the two ends of the receiving coil L2 on the chip in the body. The active rectifier includes a pair of cross-coupled PMOS power tubes and NMOS power tubes NM1 and NM2. The drains of the NMOS power tubes NM1 and NM2 are respectively used to receive the AC input signal V WP and V WN The source of the PMOS power tube is used to generate a DC voltage V REC ; Two adaptive voltage feedback circuits, whose input terminals are connected to the gates of NMOS power tubes NM1 and NM2 respectively, adjust V WP and V WN Sampling is performed and based on V WP and V WN Generates the feedback voltage V at the turn-on time FB_ON and the feedback voltage V at the turn-off time FB_OFF ; Two hybrid gate control circuits, each of which includes a common gate comparator, a rising edge detection circuit, a voltage-controlled delay circuit, a first SR latch and a drive circuit; the common gate comparator is used to receive V FB_ON , according to V FB_ON With the corresponding V WP or V WN The comparison generates the delay when the NMOS power tubes NM1 and NM2 are turned on, and the delay is connected to the set end of the first SR latch after passing through the rising edge detection circuit; the voltage-controlled delay chain circuit is used to receive V FB_OFF , according to V FB_OFF Generate a delay when the NMOS power tubes NM1 and NM2 are turned off, and the delay is connected to the reset end of the first SR latch; the output end of the first SR latch drives the gate voltage V of the NMOS power tubes NM1 and NM2 after passing through the driving circuit GP and V GN .

2. A wireless power supply receiving circuit as claimed in claim 1, characterized in that: The receiving coil L2 is used to receive the AC signal transmitted by the wireless function transmitting circuit outside the body. The wireless function transmitting circuit includes an MCU, a power amplifier and an LC network. The MCU controls the power amplifier to transmit the AC signal, and the AC signal is coupled to the receiving coil L2 on the chip inside the body through the transmitting coil L1 of the LC network.

3. A wireless power supply receiving circuit as claimed in claim 1, characterized in that: The drains of the two PMOS power tubes are respectively connected to the drains of the NMOS power tubes NM1 and NM2, the gates are respectively connected to the drains of the NMOS power tubes NM1 and NM2 after crossing, and the sources of the NMOS power tubes NM1 and NM2 are grounded.

4. A wireless power supply receiving circuit as claimed in claim 1, characterized in that: Each of the adaptive voltage feedback circuits includes a sampling and holding circuit, a level shifting circuit, a window voltage comparator and an integrator; the sampling and holding circuit includes a switching capacitor circuit, a rising edge pulse generator, a falling edge pulse generator and a second SR latch; the gate voltages of the NMOS power tubes NM1 and NM2 generate a timing control voltage after passing through the pulse generator and the second SR latch; the output of the second SR latch is connected to and controls the switch of the switching capacitor circuit; the input of the switching capacitor circuit is connected to the two ends of the receiving coil, and the voltages at the two ends are sampled and held according to the timing change; the output of the sampling and holding circuit is connected to the input of the level shifter; the level shifter is composed of four PMOS source followers, and its output is connected to the input of the window comparator; the window comparator is composed of two open-loop error amplifiers, and its output is connected to the input of the integrator; the integrator is composed of a PMOS tube, an NMOS tube, a current source and a load capacitor, and its output is connected to the mixed gate control circuit as the output of the adaptive feedback circuit.

5. A wireless power supply receiving circuit as claimed in claim 1, characterized in that: The positive input of the common-gate comparator is used to receive V FB_ON , the negative input terminal corresponds to V WP or V WN The output end is connected to one end of the rising edge detection circuit and one end of the voltage-controlled delay circuit; the other end of the rising edge detection circuit is connected to the set end of the first SR latch; one end of the voltage-controlled delay circuit is also used to receive V FB_OFF , and the other end is connected to the reset end of the first SR latch; the output end of the drive circuit is connected to the gate of the NMOS power tube NM1 or NM2.

6. A wireless power supply receiving circuit as claimed in claim 2, characterized in that: The output end of the active rectifier is connected in parallel with a load capacitor C L As well as the load resistors R1 and R2, the load capacitor C L One end is connected to the source of the PMOS power tube, and the other end is grounded; the load resistors R1 and R2 are connected in series, one end of R1 is connected to the source of the PMOS power tube, and the other end is grounded.

7. A wireless power supply receiving circuit as claimed in claim 6, characterized in that: The wireless power supply receiving circuit also includes a load power detection and modulation circuit, and the load power detection and modulation circuit includes a resistor R3, a load power detection tube N OVP , error amplifier and analog-to-digital converter, one end of the resistor R3 is connected to the source of the PMOS power tube, and the other end is connected to the load power detection tube N OVP The drain terminal V OVP Connection; the positive input terminal of the error amplifier is connected between the load resistors R1 and R2, and the negative input terminal is connected to the reference voltage V ref The load power detection tube N OVP The source of the current is grounded, the gate is connected to the output of the error amplifier, the drain and the output of the active rectifier are connected to the input of the analog-to-digital converter, and the output of the analog-to-digital converter D OUT , which is used to reflect the change of load power and feed back to the MCU of the wireless power supply transmission circuit to generate corresponding logic output to control the output power of the power amplifier.

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