Two-phase clamping intermittent pulse width modulation method of three-phase two-level converter

Abstract

The invention discloses a two-phase clamping intermittent pulse width modulation method of a three-phase two-level converter, belongs to the technical field of converter control, and relates to a method for solving the problem of how to realize two-phase clamping in a vector approximate synthesis mode and judging a sector where a reference output voltage vector is located in a control vector diagram. Respectively drawing vertical lines from the vertex of the reference output voltage vector to the three sides of the adjacent triangle, and replacing the reference output voltage vector with a voltage vector corresponding to a vertical foot on the side closest to the reference output voltage vector, so that two phases are clamped; two-phase clamping is achieved in a vector approximate synthesis mode, error accumulation exists after calculation of multiple periods, and therefore vector synthesis errors caused by the previous periods need to be considered in voltage vector calculation of the current period so as to achieve the purpose of eliminating error accumulation. Compared with a traditional modulation method, the switching device has no switching action in the 2 / 3 fundamental wave period, the switching loss is reduced, and the efficiency of the converter is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of converter control and relates to a two-phase clamped discontinuous pulse width modulation method of a three-phase two-level converter. Background Art

[0002] Due to its simple topology, few switching devices and low manufacturing cost, the three-phase two-level converter has become one of the most widely used power electronic converters. Nowadays, the three-phase two-level converter has been widely used in renewable energy generation, electric drive, active power filter, electric vehicle traction, adjustable speed motor drive, photovoltaic grid-connected system and other fields.

[0003] Switching loss is a very important performance indicator of the converter. Switching loss accounts for a large proportion of the switching device loss and is also the main factor limiting the increase in the system switching frequency. As the switching frequency of the device increases, the switching loss of the system will increase significantly, which not only reduces the system efficiency, but also increases the size of the heat sink. In addition, the increase in switching loss will also reduce the reliability and service life of the switching device. Therefore, it is very necessary to reduce the switching loss of the system.

[0004] In order to reduce switching losses, discontinuous pulse width modulation (DPWM) was proposed. The DPWM method clamps one phase and modulates the other two phases, so that the switching devices of each phase have no switching action within 1 / 3 of the fundamental wave period, thus effectively reducing switching losses and improving converter efficiency. From the perspective of space vectors, DPWM can be achieved by discarding redundant zero vectors and synthesizing the reference output voltage vector with three vectors; from the perspective of carriers, DPWM can be achieved by injecting zero-sequence voltage into the modulation wave; however, it is worth noting that traditional DPWM only clamps one phase and cannot further reduce the switching losses of the converter. Summary of the invention

[0005] The technical solution of the present invention is used to solve the problem of how to achieve two-phase clamping by means of vector approximate synthesis, thereby reducing switching losses and improving converter efficiency.

[0006] The present invention solves the above technical problems through the following technical solutions:

[0007] The present invention provides a two-phase clamped discontinuous pulse width modulation method for a three-phase two-level converter, comprising the following steps:

[0008] Step 1: According to the reference output voltage vector u ref The angle determines the sector it is in;

[0009] Step 2: According to the reference output voltage vector u ref The sector in which the reference output voltage vector uref Draw a perpendicular line from the vertex to the determined edge, and use the vector corresponding to the foot of the perpendicular as the edge voltage vector u′ ref , so that the two-phase output voltage is clamped;

[0010] 1) From the reference output voltage vector u ref Draw perpendicular lines from the vector vertex to the three sides of the sector;

[0011] 2) Find the edge corresponding to the shortest perpendicular line and select the vector corresponding to the foot of the perpendicular as the edge voltage vector u′ ref ;

[0012] 3) Let the edge voltage vector u′ ref =u ref +u err , then the vector synthesis error u err =u′ ref -u ref ;

[0013] Step 3: Consider the vector synthesis error u caused by the previous cycle err ′, correct the reference output voltage vector of the current cycle to the final output voltage vector u′ * ref , u′ * ref =u ref +u err ′;

[0014] 4) Assign the vector synthesis error of the current cycle to the previous cycle;

[0015] Step 4: According to the output voltage vector u′ * ref Get the three-phase modulation voltage u′ A,ref , u′ B,ref , u′ C,ref .

[0016] Furthermore, the output voltage vector u′ * ref Get the three-phase modulation voltage u′ A,ref , u′ B,ref , u′ C,ref The method is as follows:

[0017] The two-level converter has a total of 8 output states, corresponding to 6 basic voltage vectors and 2 zero voltage vectors in the complex plane; the 6 basic voltage vectors are: 1 [1,0,0],u 2 [1,1,0],u 3 [0,1,0],u 4 [0,1,1],u5 [0,0,1],u 6 [1,0,1]; the two zero voltage vectors are u′ 0 [0,0,0],u″ 0 [1,1,1], these vectors constitute the space vector diagram of the two-level converter. The basic voltage vector length is defined as unit value. The six basic voltage vectors divide the regular hexagon into six sectors. In the α / β axis system, the reference output voltage vector u ref Denoted as:

[0018] u ref =u α +ju β

[0019] In the formula, u α 、u β They are the α and β axis components of the voltage vector respectively;

[0020] With reference to the output voltage vector u ref Taking the I sector as an example, the I sector is divided into three parts, namely SI_1 area, SI_2 area and SI_3 area. When the reference output voltage vector u ref When in SI_1 region, the reference output voltage vector u ref from u′ 0 and u 2 The connection l 1 At this time, both phases A and B should be clamped to level 1, and phase C should be modulated; when the reference output voltage vector u ref When in SI_2 area, the reference output voltage vector u ref away from u 1 and u 2 The connection l 2 At this time, phase A should be clamped to level 1, phase C should be clamped to level 0, and phase B should be modulated; when the reference output voltage vector u ref When in SI_3 area, the reference output voltage vector u ref from u′ 0 and u 1 The connection l 3 Recently, at this time, both phases B and C should be clamped to 0 level, and phase A should be modulated;

[0021] When the edge reference vector u′ is used ref Instead of the reference output voltage vector u ref When , the synthesis error is minimized; for this purpose, the vector synthesis error evaluation function is defined as:

[0022] g err =[u ref,α -u′ α ] 2 +[uref,β -u′ β ] 2

[0023] In the formula, u ref,α 、u ref,β are the α and β axis components of the output voltage vector, u′ α , u′ β They are the α and β axis components of the edge voltage vector respectively;

[0024] The vector composite error is defined as:

[0025] u err =u ref -u′ ref

[0026] With reference to the output voltage vector u ref For example, in sector I, if the reference output voltage vector u ref The vertices of 1 , l 2 and l 3 Draw a perpendicular line, and the vector corresponding to the perpendicular line is the synthetic error vector u err1 、u err2 and u err3 , the vector corresponding to the foot of the perpendicular is the three edge reference vectors u′ ref1 , u′ ref2 and u′ ref3 ; In the α / β axis system, the three edge reference vectors u′ ref1 , u′ ref2 and u′ ref3 The corresponding expressions of the vector synthesis error evaluation function are:

[0027]

[0028] When the reference output voltage vector u ref When it is in SI_1 area, that is, g err1 Minimum, at this time u err1 It is expressed as:

[0029]

[0030] According to the above two equations, the edge voltage vector u′ can be obtained ref The corresponding three-phase output voltage is expressed as:

[0031]

[0032] Where u′ A,ref , u′ B,ref , u′ C,ref are the three-phase components A, B, and C corresponding to the edge voltage vectors, uA,ref ,u B,ref ,u C,ref They are the three-phase components A, B and C corresponding to the output voltage vector respectively;

[0033] At this time, the two phases AB have not been clamped to the positive bus. Injecting zero-sequence voltage into the three phases will not change the position of the voltage vector. Injecting zero-sequence voltage makes the two phases AB clamped to the positive bus. Therefore, the three-phase modulation voltage is written as:

[0034]

[0035] Similarly, find the reference output voltage vector u ref Three-phase modulated voltage in SI_2 and SI_3 time zones;

[0036] When the reference output voltage vector u ref When the vertex of is located at the boundary between SI_1 and SI_2, it satisfies:

[0037]

[0038] In the formula, u A,ref is the A phase output voltage;

[0039] Similarly, the extension of the boundary line between SI_1 and SI_3 perpendicularly bisects l 2 , and l 2 It is parallel to the B phase axis, so when the reference output voltage vector u ref When the vertex of is located at the boundary between SI_1 and SI_3, it satisfies:

[0040] u B,ref =0

[0041] Therefore, the reference output voltage vector u ref The criteria for being in SI_1 area are:

[0042]

[0043] Similarly, find the reference output voltage vector u ref The judgment condition of being located in SI_2 area or SI_3 area;

[0044] In summary, the area criteria and modulation voltage corresponding to the modulation are shown in the following table:

[0045]

[0046] The present invention also provides an electronic device, comprising a memory and a processor, wherein the memory is used to store a program that supports the processor to execute the two-phase clamped intermittent pulse width modulation method of the above-mentioned three-phase two-level converter, and the processor is configured to execute the program stored in the memory.

[0047] The present invention also provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, executes the steps of the two-phase clamped discontinuous pulse width modulation method of the above-mentioned three-phase two-level converter.

[0048] The advantages of the present invention are:

[0049] The modulation method of the present invention first determines the sector where the reference output voltage vector is located in the control vector diagram; then, perpendicular lines are drawn from the vertex of the reference output voltage vector to the three sides of the adjacent triangles, and the reference output voltage vector is replaced by the voltage vector corresponding to the foot of the perpendicular on the side closest to the reference output voltage vector, so that the two phases are clamped; the two-phase clamping is achieved by vector approximate synthesis, and there will be error accumulation after multiple cycle calculations, so in the voltage vector calculation of the current cycle, the vector synthesis error caused by the previous cycle needs to be considered to achieve the purpose of eliminating the error accumulation; the present invention does not need to add any peripherals, the system cost is low, the control method is simple, and it is easy to implement; compared with the traditional DPWM, the switch device has no switching action within 2 / 3 of the fundamental wave cycle, which further reduces the switching loss and improves the converter efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a flow chart of a two-phase clamped discontinuous pulse width modulation method of a three-phase two-level converter according to an embodiment of the present invention;

[0051] Figure 2 A space vector diagram of a two-level converter of a two-phase clamped discontinuous pulse width modulation method for a three-phase two-level converter according to an embodiment of the present invention;

[0052] Figure 3 It is a principle diagram of a two-phase clamped discontinuous pulse width modulation method for a three-phase two-level converter according to an embodiment of the present invention;

[0053] Figure 4 A switching sequence diagram of a two-phase clamped discontinuous pulse width modulation method for a three-phase two-level converter according to an embodiment of the present invention;

[0054] Figure 5 A switching loss comparison diagram of a two-phase clamped discontinuous pulse width modulation method and a DPWM modulation method of a three-phase two-level converter according to an embodiment of the present invention;

[0055] Figure 6 The waveform diagram of the two-phase clamped discontinuous pulse width modulation method, the SPWM modulation method and the DPWM modulation method of the three-phase two-level converter according to the embodiment of the present invention when the modulation index is equal to 0.2;

[0056] Figure 7The waveform diagrams of the two-phase clamped discontinuous pulse width modulation method, the SPWM modulation method and the DPWM modulation method of the three-phase two-level converter according to the embodiment of the present invention when the modulation index is equal to 0.6;

[0057] Figure 8 The waveform diagrams are of the two-phase clamped discontinuous pulse width modulation method, the SPWM modulation method and the DPWM modulation method of the three-phase two-level converter according to the embodiment of the present invention when the modulation index is equal to 0.95. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and specific embodiments:

[0060] Embodiment 1

[0061] like Figure 1 As shown, the two-phase clamped discontinuous pulse width modulation method of the three-phase two-level converter according to the embodiment of the present invention comprises the following steps:

[0062] Step 1: According to the reference output voltage vector u ref The angle determines the sector it is in;

[0063] Step 2: According to the reference output voltage vector u ref The sector in which the reference output voltage vector u ref Draw a perpendicular line from the vertex to the determined edge, and use the vector corresponding to the foot of the perpendicular as the edge voltage vector u′ ref , so that the two-phase output voltage is clamped;

[0064] 1) From the reference output voltage vector u ref Draw perpendicular lines from the vector vertex to the three sides of the sector;

[0065] 2) Find the edge corresponding to the shortest perpendicular line and select the vector corresponding to the foot of the perpendicular as the edge voltage vector u′ ref ;

[0066] 3) Let the edge voltage vector u′ ref =u ref +u err , then the vector synthesis error u err =u′ ref -uref .

[0067] Step 3: Consider the vector synthesis error u caused by the previous cycle err ′, correct the reference output voltage vector of the current cycle to the final output voltage vector u′ * ref , u′ * ref =u ref +u err ′;

[0068] 4) Assign the vector synthesis error of the current cycle to the previous cycle.

[0069] Step 4: According to the output voltage vector u′ * ref Get the three-phase modulation voltage u′ A,ref , u′ B,ref , u′ C,ref .

[0070] like Figure 2 As shown, the two-level converter modulated by the modulation method of the present invention has a total of 8 output states, corresponding to 6 basic voltage vectors and 2 zero voltage vectors in the complex plane; the 6 basic voltage vectors are: 1 [1,0,0],u 2 [1,1,0],u 3 [0,1,0],u 4 [0,1,1],u 5 [0,0,1],u 6 [1,0,1]; the two zero voltage vectors are u′ 0 [0,0,0],u″ 0 [1,1,1]; these vectors constitute the space vector diagram of the two-level converter. The length of the basic voltage vector is defined as unit value. The six basic voltage vectors divide the regular hexagon into six sectors. In the α / β axis system, the reference output voltage vector u ref Denoted as:

[0071] u ref =u α +ju β

[0072] In the formula, u α 、u β They are the α and β axis components of the voltage vector respectively.

[0073] like Figure 3 As shown, with reference to the output voltage vector u refTaking the I sector as an example, the I sector is divided into three parts, namely SI_1, SI_2 and SI_3. It is not difficult to see that when the reference output voltage vector u ref When in SI_1 region, the reference output voltage vector u ref from u″ 0 and u 2 The connection l 1 At this time, both phases A and B should be clamped to level 1, and phase C should be modulated; when the reference output voltage vector u ref When in SI_2 area, the reference output voltage vector u ref away from u 1 and u 2 The connection l 2 At this time, phase A should be clamped to level 1, phase C should be clamped to level 0, and phase B should be modulated; when the reference output voltage vector u ref When in SI_3 area, the reference output voltage vector u ref from u′ 0 and u 1 The connection l 3 At this time, both phases B and C should be clamped to 0 level, and phase A should be modulated; the corresponding PWM sequence is as follows Figure 4 shown.

[0074] When the edge reference vector u′ is used ref Instead of the reference output voltage vector u ref When , the synthesis error should be minimized; for this purpose, the vector synthesis error evaluation function is defined as:

[0075] g err =[u ref,α -u′ α ] 2 +[u ref,β -u′ β ] 2

[0076] In the formula, u ref,α 、u ref,β are the α and β axis components of the output voltage vector, u′ α , u′ β They are the α and β axis components of the edge voltage vector respectively.

[0077] The vector composite error is defined as:

[0078] u err =u ref -u′ ref

[0079] The vector synthesis error evaluation function actually represents the modulus length of the synthesis error vector. refFor example, in sector I, if the reference output voltage vector u ref The vertices of 1 , l 2 and l 3 Draw a perpendicular line, and the vector corresponding to the perpendicular line is the synthetic error vector u err1 、u err2 and u err3 , the vector corresponding to the foot of the perpendicular is the three edge reference vectors u′ ref1 , u′ ref2 and u′ ref3 In the α / β axis system, the three edge reference vectors u′ ref1 , u′ ref2 and u′ ref3 The corresponding expressions of the vector synthesis error evaluation function are:

[0080]

[0081] When the reference output voltage vector u ref When it is in SI_1 area, that is, g err1 Minimum, at this time u err1 It can be expressed as:

[0082]

[0083] According to the above two equations, the edge voltage vector u′ can be obtained ref The corresponding three-phase output voltage can be expressed as:

[0084]

[0085] Where u′ A,ref , u′ B,ref , u′ C,ref are the three-phase components A, B, and C corresponding to the edge voltage vectors, u A,ref ,u B,ref ,u C,ref They are the A, B, and C three-phase components corresponding to the output voltage vector respectively.

[0086] It can be seen that at this time, phases AB have not been clamped to the positive bus. Injecting zero-sequence voltage into the three phases will not change the position of the voltage vector. Injecting zero-sequence voltage causes phases AB to be clamped to the positive bus, so the three-phase modulation voltage can be written as:

[0087]

[0088] Similarly, when the reference output voltage vector u ref In the SI_2 and SI_3 time zones, the three-phase modulation voltage can be calculated similarly, which will not be elaborated here.

[0089] like Figure 3 As shown, it can be seen that the extension line of the boundary line between SI_1 and SI_2 vertically bisects l 3 , and l 3 It also coincides with the A phase axis. Therefore, when the reference output voltage vector u ref When the vertex of is located at the boundary between SI_1 and SI_2, it satisfies:

[0090]

[0091] In the formula, u A,ref is the A phase output voltage.

[0092] Similarly, it is found that the extension of the boundary line between SI_1 and SI_3 perpendicularly bisects l 2 , and l 2 It is parallel to the B phase axis, so when the reference output voltage vector u ref When the vertex of is located at the boundary between SI_1 and SI_3, it satisfies:

[0093] u B,ref =0

[0094] Therefore, the reference output voltage vector u ref The criteria for being in SI_1 area are:

[0095]

[0096] When the reference output voltage vector u ref The judgment conditions for being in the SI_2 area or the SI_3 area can also be obtained similarly. Table 1 shows the area judgment criteria and modulation voltage corresponding to the modulation method of the present invention.

[0097] Table 1 Regional criteria and modulation voltage

[0098]

[0099] If we directly use the edge voltage vector u′ ref As a modulation voltage, the synthesis error will be relatively large and the output current quality will be relatively poor, so further improvement is needed.

[0100] In actual control systems, digital signal processors can only process discrete digital signals and use edge voltage vector u′ in the current cycle. ref Instead of the reference output voltage vector u ref , the synthetic error introduced is:

[0101] u err (n) = u ref (n)-u′ ref (n)

[0102] In the formula, u ref (n),u′ ref (n) are the output voltage vector and edge voltage vector of the current cycle respectively.

[0103] If we directly use the edge reference vector u′ ref When modulated as a modulation voltage, a synthetic error is introduced in each switching cycle. Assume that the reference output voltage vector u is ref All are located in SI_1 area, Figure 5 It can be seen that the minimum synthetic error vector (u err_min(1) , ..., u err_min(k) ) are in the same direction and perpendicular to l 1 , the gradually increasing error accumulation within k switching cycles is the main reason for the deterioration of the converter output waveform. If the vector synthesis error caused by the previous cycle can be taken into account in the calculation of the voltage vector of the current cycle, the error accumulation can be eliminated. To this end, the reference output voltage vector is modified as:

[0104]

[0105] in, is the reference output voltage vector taking into account the historical synthetic error.

[0106] The edge reference vector considering the historical synthesis error is calculated by the two-phase clamped discontinuous pulse width modulation method (2PCDPWM) of the three-phase two-level converter of the present invention. At the same time, the synthetic error is:

[0107]

[0108] Test verification

[0109] In order to verify the performance of the modulation method of the present invention,

[0110] Figure 5 The switching losses of the modulation method of the present invention and the traditional DPWM modulation method under the whole operation conditions are given. It can be seen that the switching loss of DPWM is as low as 0.5 and as high as 0.86. For the modulation method of the present invention, since two-phase voltages are clamped, it can be seen that the switching losses are all below 0.5. When the power factor is low and the modulation degree is low, the switching loss can reach about 0.15.

[0111] Then, the output current qualities are compared, mainly comparing the output current qualities of SVPWM, DPWM and the modulation method of the present invention when the power factor angle φ=π / 12 and the modulation degree m are 0.2, 0.6 and 0.95. Figure 6 , Figure 7 and Figure 8The corresponding experimental waveforms are given. Table 2 lists the current THD of different modulation methods under different modulation indices.

[0112] Table 2 Current THD of different methods under different modulation degrees

[0113]

[0114] Embodiment 2

[0115] An electronic device comprises a memory and a processor, wherein the memory is used to store a program supporting the processor to execute the two-phase clamped discontinuous pulse width modulation method of the above-mentioned three-phase two-level converter, and the processor is configured to execute the program stored in the memory.

[0116] Embodiment 3

[0117] A storage medium stores a computer program, which, when executed by a processor, executes the steps of the two-phase clamped discontinuous pulse width modulation method of the three-phase two-level converter.

[0118] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A two-phase clamped discontinuous pulse width modulation method for a three-phase two-level converter, characterized in that: The following steps are involved: Step 1: According to the reference output voltage vector u ref The angle determines the sector it is in; Step 2: According to the reference output voltage vector u ref The sector in which the reference output voltage vector u ref Draw a perpendicular line from the vertex to the determined edge, and use the vector corresponding to the foot of the perpendicular as the edge voltage vector u′ ref , so that the two-phase output voltage is clamped; 1) From the reference output voltage vector u ref Draw perpendicular lines from the vector vertex to the three sides of the sector; 2) Find the edge corresponding to the shortest perpendicular line and select the vector corresponding to the foot of the perpendicular as the edge voltage vector u′ ref ; 3) Let the edge voltage vector u′ ref =u ref +u err , then the vector synthesis error u err =u′ ref -u ref ; Step 3: Consider the vector synthesis error u caused by the previous cycle err ′, correct the reference output voltage vector of the current cycle to the final output voltage vector u′ * ref , u′ * ref =u ref +u err ′; 4) Assign the vector synthesis error of the current cycle to the previous cycle; Step 4: According to the output voltage vector u′ * ref Get the three-phase modulation voltage u′ A,ref , u′ B,ref , u′ C,ref .

2. The two-phase clamped discontinuous pulse width modulation method of a three-phase two-level converter according to claim 1, characterized in that: The output voltage vector u′ * ref Get the three-phase modulation voltage u′ A,ref , u′ B,ref , u′ C,ref The method is as follows: The two-level converter has a total of 8 output states, corresponding to 6 basic voltage vectors and 2 zero voltage vectors in the complex plane; the 6 basic voltage vectors are: u1[1,0,0], u2[1,1,0], u3[0,1,0], u4[0,1,1], u5[0,0,1], u6[1,0,1]; the 2 zero voltage vectors are u0′[0,0,0], u0″[1,1,1]. These vectors constitute the space vector diagram of the two-level converter. The length of the basic voltage vector is defined as unit value. The 6 basic voltage vectors divide the regular hexagon into 6 sectors. In the α / β axis system, the reference output voltage vector u ref Denoted as: you ref =u α +you β In the formula, u α 、u β They are the α and β axis components of the voltage vector respectively; With reference to the output voltage vector u ref Taking the I sector as an example, the I sector is divided into three parts, namely SI_1 area, SI_2 area and SI_3 area. When the reference output voltage vector u ref When in SI_1 region, the reference output voltage vector u ref It is closest to the line l1 connecting u0″ and u2. At this time, both phases A and B should be clamped to level 1, and phase C should be modulated; When the reference output voltage vector u ref When in SI_2 area, the reference output voltage vector u ref The line l2 that is closest to u1 and u2 should clamp phase A to level 1, phase C to level 0, and phase B to modulate; When the reference output voltage vector u ref When in SI_3 area, the reference output voltage vector u ref The line l3 that is closest to u0′ and u1, at this time, both phases B and C should be clamped to 0 level, and phase A should be modulated; When the edge reference vector u r ' ef Instead of the reference output voltage vector u ref When , the synthesis error is minimized; To this end, the vector synthesis error evaluation function is defined: Mr err =[in ref,α -in' α ] 2 +[in ref,β -in' β ] 2 In the formula, u ref,α 、u ref,β are the α and β axis components of the output voltage vector, u′ α , u′ β They are the α and β axis components of the edge voltage vector respectively; The vector composite error is defined as: in err =in ref -in' ref With reference to the output voltage vector u ref For example, in sector I, if the reference output voltage vector u ref Draw perpendicular lines to l1, l2 and l3 respectively. The vector corresponding to the perpendicular line is the synthetic error vector u err1 、u err2 and u err3 , the vector corresponding to the foot of the perpendicular is the three edge reference vectors u′ ref1 , u′ ref2 and u′ ref3 ; In the α / β axis system, the three edge reference vectors u′ ref1 , u′ ref2 and u′ ref3 The corresponding expressions of the vector synthesis error evaluation function are: When the reference output voltage vector u ref When it is in SI_1 area, that is, g err1 Minimum, at this time u err1 It is expressed as: According to the above two equations, the edge voltage vector u can be obtained: r ' ef The corresponding three-phase output voltage is expressed as: In the formula, u′ A,ref , u′ B,ref , u′ C,ref are the three-phase components A, B, and C corresponding to the edge voltage vectors, u A,ref ,u B,ref ,u C,ref They are the three-phase components A, B and C corresponding to the output voltage vector respectively; At this time, the two phases AB have not been clamped to the positive bus. Injecting zero-sequence voltage into the three phases will not change the position of the voltage vector. Injecting zero-sequence voltage makes the two phases AB clamped to the positive bus. Therefore, the three-phase modulation voltage is written as: Similarly, find the reference output voltage vector u ref Three-phase modulated voltage in SI_2 and SI_3 time zones; When the reference output voltage vector u ref When the vertex of is located at the boundary between SI_1 and SI_2, it satisfies: In the formula, u A,ref is the A phase output voltage; Similarly, the extension line of the boundary line between SI_1 and SI_3 bisects l2 perpendicularly, and l2 is parallel to the axis of phase B. Therefore, when the reference output voltage vector u ref When the vertex of is located at the boundary between SI_1 and SI_3, it satisfies: u B,ref ＝0 Therefore, the reference output voltage vector u ref The criteria for being in SI_1 area are: Similarly, find the reference output voltage vector u ref The judgment condition of being located in SI_2 area or SI_3 area; In summary, the area criteria and modulation voltage corresponding to the modulation are shown in the following table:

3. An electronic device, comprising a memory and a processor, characterized in that: The memory is used to store a program that supports the processor to execute the two-phase clamped discontinuous pulse width modulation method of the three-phase two-level converter according to any one of claims 1 to 2, and the processor is configured to execute the program stored in the memory.

4. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the two-phase clamped discontinuous pulse width modulation method of the three-phase two-level converter according to any one of claims 1 to 2 are executed.

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