Control system of ANPC type three-level inverter and zero crossing point switching method

Abstract

The invention discloses a control system of an ANPC type three-level inverter and a zero crossing point switching method. The method comprises a processor, a programmable logic unit and the ANPC type three-level inverter. The processor is used for generating modulated waves as output signals of the processor based on internal signals of the processor, and the modulated waves comprise a first signal modulated wave PWMA, a second signal modulated wave PWMB and a periodic modulated wave PWMD; the programmable logic unit is used for generating a control signal of each switch tube in the ANPC type three-level inverter based on the modulation wave and an internal signal of the logic unit; and the ANPC type three-level inverter is used for performing on-off control on each switching tube based on the control signal of each switching tube output by the programmable logic unit. The operation of software in the processor can be simplified, the development difficulty and the maintenance cost of the software are reduced, and meanwhile subsequent updating iteration and troubleshooting work are facilitated.

Description

Technical Field

[0001] The present application relates to the technical field of ANPC type three-level inverter and internal tube high frequency modulation, and in particular to a control system and a zero-crossing switching method of an ANPC type three-level inverter. Background Art

[0002] In the prior art of the internal tube high frequency modulation technology, the internal tube high frequency chopping mode is a configuration scheme of 2 fast tubes and 4 slow tubes. The outer tube and the clamping tube work in the power frequency mode, and the inner tube works in the high frequency mode. The switching loss is concentrated on the inner tube. The outer tube and the clamping tube only bear part of the conduction loss, and only the inner tube uses a high-speed tube. When the internal tube high frequency modulation method is used, the zero-crossing switching needs to change the state of the outer tube and the clamping tube, and natural switching cannot be achieved. Switching needs to be done in a certain order, otherwise overvoltage damage may occur during zero-crossing switching.

[0003] In response to the problem of zero-crossing switching, this patent proposes an improved ANPC type three-level inverter control system and zero-crossing switching method, aiming to solve the problems existing in the prior art and help avoid system instability caused by frequent changes in the state of the switch tube during zero-crossing switching. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a control system and a zero-crossing switching method for an ANPC type three-level inverter.

[0005] According to one aspect of the present application, a control system of an ANPC type three-level inverter is provided, comprising: a processor, a programmable logic unit and an ANPC type three-level inverter;

[0006] The processor is used to generate a modulation wave as an output signal of the processor based on an internal signal of the processor, wherein the modulation wave includes a first signal modulation wave PWMA, a second signal modulation wave PWMB, and a periodic modulation wave PWMD;

[0007] The programmable logic unit is used to generate a control signal for each switch tube in the ANPC type three-level inverter based on the modulation wave and the internal signal of the logic unit;

[0008] The ANPC type three-level inverter is used to control the switching of each switch tube based on the control signal of each switch tube output by the programmable logic unit; the switch tubes in the ANPC type three-level inverter include a positive half-cycle outer tube T1, a positive half-cycle inner tube T2, a positive half-cycle clamping tube T5, a negative half-cycle outer tube T4, a negative half-cycle inner tube T3, and a negative half-cycle clamping tube T6;

[0009] The internal signals of the logic unit include a periodic state signal PWMD_ACTIVE and a locking signal LOCK; after the state of the periodic modulation wave PWMD changes, the periodic state signal PWMD_ACTIVE waits for a falling edge to appear in any one of the first signal modulation wave PWMA and the second signal modulation wave PWMB, and then switches the state, and at the same time sets the locking signal LOCK to enter a zero-crossing switching locking state; when the locking signal LOCK is in the set state, the control signal of the tube T2 in the positive half cycle and the control signal of the tube T3 in the negative half cycle no longer follow the state change of the signal modulation wave.

[0010] According to another aspect of the present application, a zero-crossing switching method of an ANPC type three-level inverter is provided, characterized in that it is applied to the control system of the above-mentioned ANPC type three-level inverter, comprising:

[0011] When a state change of the periodic modulation wave PWMD output by the processor is detected, the state is switched when a falling edge appears in any one of the first signal modulation wave PWMA and the second signal modulation wave PWMB, and the locking signal LOCK is set to enter a zero-crossing switching locking state from the first cycle to the second cycle;

[0012] The steps are executed in sequence: setting the tube enable signal in the first half cycle low to low the tube signal in the first half cycle, setting the tube forced setting signal in the second half cycle to force the tube signal in the second half cycle, setting the tube signal outside the first half cycle low, setting the first half cycle clamping tube signal, setting both the tube enable signal and the forced setting signal in the second half cycle low to force the tube signal in the second half cycle low, setting both the tube enable signal and the forced setting signal in the first half cycle to force the tube signal in the first half cycle to low, setting the tube enable signal and the forced setting signal in the first half cycle to force the tube signal in the first half cycle, setting the second half cycle clamping tube signal low, setting the tube signal outside the second half cycle, waiting for a falling edge in any one of the first signal modulation wave and the second signal modulation wave to low the tube forced setting signal in the first half cycle, setting the tube enable signal in the second half cycle, and setting the lock signal LOCK low.

[0013] According to another aspect of the present application, a storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the zero-crossing switching method of the ANPC type three-level inverter is implemented.

[0014] According to another aspect of the present application, a computer device is provided, including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein when the processor executes the program, the zero-crossing switching method of the ANPC type three-level inverter is implemented.

[0015] By means of the above technical scheme, a control system and a zero-crossing switching method of an ANPC type three-level inverter provided in an embodiment of the present application can effectively reduce the distortion of the output voltage waveform and improve the waveform quality by precisely controlling the logic of zero-crossing switching, waiting for the falling edge of PWMA or PWMB to switch after the state of the periodic modulation wave PWMD changes, and setting the locking signal LOCK. During the period when the locking signal LOCK is set, the control signals of the tube T2 in the positive half cycle and the tube T3 in the negative half cycle remain stable and do not follow the state change of the signal modulation wave, which helps to avoid system instability caused by frequent changes in the state of the switch tube during the zero-crossing switching. The use of a programmable logic unit makes the generation of control signals more flexible, and the control logic can be adjusted and optimized according to actual application requirements, thereby improving the adaptability and scalability of the system, and realizing complex control functions through software logic, reducing the dependence on hardware circuits and reducing hardware costs. In summary, the technical scheme of the present application effectively improves the output voltage waveform quality and system stability of the ANPC type three-level inverter by precisely controlling the logic of zero-crossing switching and the control signal of the switch tube, while enhancing the flexibility of control and reducing hardware costs.

[0016] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 A schematic diagram of the structure of a control system of an ANPC type three-level inverter provided in an embodiment of the present application is shown;

[0019] Figure 2 A schematic diagram of the structure of an ANPC type three-level inverter topology provided in an embodiment of the present application is shown;

[0020] Figure 3 A schematic diagram of a zero-crossing switching process of an ANPC type three-level inverter provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0022] In this embodiment, an ANPC type three-level inverter is provided, such as Figure 1 As shown, including:

[0023] A processor, a programmable logic unit and an ANPC type three-level inverter (i.e., an ANPC inverter bridge);

[0024] The processor is used to generate a modulation wave as an output signal of the processor based on an internal signal of the processor, wherein the modulation wave includes a first signal modulation wave PWMA, a second signal modulation wave PWMB, and a periodic modulation wave PWMD;

[0025] The programmable logic unit is used to generate a control signal for each switch tube in the ANPC type three-level inverter based on the modulation wave and the internal signal of the logic unit;

[0026] The ANPC type three-level inverter is used to control the switching of each switch tube based on the control signal of each switch tube output by the programmable logic unit; the switch tubes in the ANPC type three-level inverter include a positive half-cycle outer tube T1, a positive half-cycle inner tube T2, a positive half-cycle clamping tube T5, a negative half-cycle outer tube T4, a negative half-cycle inner tube T3, and a negative half-cycle clamping tube T6;

[0027] The internal signals of the logic unit include a periodic state signal PWMD_ACTIVE and a locking signal LOCK; after the state of the periodic modulation wave PWMD changes, the periodic state signal PWMD_ACTIVE waits for a falling edge to appear in any one of the first signal modulation wave PWMA and the second signal modulation wave PWMB, and then switches the state, and at the same time sets the locking signal LOCK to enter a zero-crossing switching locking state; when the locking signal LOCK is in the set state, the control signal of the tube T2 in the positive half cycle and the control signal of the tube T3 in the negative half cycle no longer follow the state change of the signal modulation wave.

[0028] An embodiment of the present application provides a control system for an ANPC (active neutral point clamp) type three-level inverter, which is mainly composed of a processor, a programmable logic unit and an ANPC type three-level inverter. The processor is responsible for generating three modulation wave signals: a first signal modulation wave PWMA, a second signal modulation wave PWMB, and a periodic modulation wave PWMD, which are the basis for the subsequent generation of switch tube control signals. The programmable logic unit receives the modulation wave signal generated by the processor, and combines the internal signals of the logic unit (such as the periodic state signal PWMD_ACTIVE, the locking signal LOCK, and may also include a tube enable signal T2EN in the positive half cycle, a tube forced setting signal T2FORCE in the positive half cycle, a tube enable signal T3EN in the negative half cycle, and a tube forced setting signal T3FORCE in the negative half cycle) to generate each switch tube in the ANPC type three-level inverter (such as Figure 2 As shown, the control signals of the positive half-cycle outer tube T1, the positive half-cycle inner tube T2, the positive half-cycle clamp tube T5, the negative half-cycle outer tube T4, the negative half-cycle inner tube T3, and the negative half-cycle clamp tube T6). According to the control signals of each switch tube output by the programmable logic unit, the switch tubes in the ANPC type three-level inverter perform corresponding switching actions, thereby realizing the conversion and output of electric energy. After the state of the periodic modulation wave PWMD changes, the periodic state signal PWMD_ACTIVE waits for a falling edge in either PWMA or PWMB, switches the state, and sets the lock signal LOCK to enter the zero-crossing switching lock state, ensuring the stability of the system and the waveform quality of the output voltage during the zero-crossing switching. When LOCK is set, the control signals of the positive half-cycle inner tube T2 and the negative half-cycle inner tube T3 do not follow the state changes of the signal modulation wave, which helps to maintain the stability of the system during the zero-crossing switching.

[0029] By applying the technical solution of this embodiment, by accurately controlling the logic of zero-crossing switching, waiting for the falling edge of PWMA or PWMB to switch after the state of the periodic modulation wave PWMD changes, and setting the lock signal LOCK, the distortion of the output voltage waveform can be effectively reduced and the waveform quality can be improved. During the period when the lock signal LOCK is set, the control signals of the tube T2 in the positive half cycle and the tube T3 in the negative half cycle remain stable and do not follow the state change of the signal modulation wave, which helps to avoid system instability caused by frequent changes in the state of the switch tube during the zero-crossing switching. The use of the programmable logic unit makes the generation of the control signal more flexible, and the control logic can be adjusted and optimized according to the actual application requirements, which improves the adaptability and scalability of the system, and realizes complex control functions through software logic, reduces the dependence on hardware circuits, and reduces hardware costs. In summary, the technical solution of the present application effectively improves the output voltage waveform quality and system stability of the ANPC type three-level inverter by accurately controlling the logic of zero-crossing switching and the control signal of the switch tube, while enhancing the flexibility of control and reducing hardware costs.

[0030] In an embodiment of the present application, optionally, the periodic modulation wave PWMD is set when the internal signal of the processor is in a positive half cycle, and is set low when the internal signal of the processor is in a negative half cycle; the first signal modulation wave PWMA and the second signal modulation wave PWMB are generated based on a signal of an absolute value of the internal signal of the processor, and there is a dead time between the first signal modulation wave and the second signal modulation wave.

[0031] In this embodiment, if Figure 3As shown, when the internal signal Ux of the processor indicates that the current is the positive half cycle, the periodic modulation wave PWMD is set (usually set to a high level or logic "1"). When the internal signal of the processor indicates that the current is the negative half cycle, the periodic modulation wave PWMD is set low (usually set to a low level or logic "0"). It is ensured that the periodic modulation wave PWMD can accurately reflect the current working cycle of the inverter (positive half cycle or negative half cycle), thereby providing a basis for subsequent logical judgment and control signal generation. The two modulation waves of the first signal modulation wave PWMA and the second signal modulation wave PWMB are generated based on the signal Ux' that takes the absolute value of the internal signal of the processor. In order to avoid short circuit when the PWM signal is switched, the first signal modulation wave PWMA and the second signal modulation wave PWMB are designed with a dead time td. The dead time is a short time interval during which both modulation waves are at a low level or invalid state, thereby ensuring that the switch tube will not be turned on at the same time when switching. By setting the dead time between the PWM signals, the short circuit or transient high voltage problem caused by the simultaneous conduction of the switch tube during the switching process can be effectively avoided, thereby improving the safety and reliability of the system. Since the first signal modulation wave PWMA and the second signal modulation wave PWMB are generated based on the absolute value of the internal signal of the processor, the operation of the software in the processor can be simplified, the difficulty of software development and maintenance costs can be reduced, and subsequent updates, iterations and troubleshooting can be facilitated.

[0032] In the embodiment of the present application, optionally, when the locking signal LOCK is in a low state, the control signals of the positive half-cycle outer tube T1, the positive half-cycle clamp tube T5, the negative half-cycle outer tube T4, and the negative half-cycle clamp tube T6 remain unchanged, and the control signal of the positive half-cycle inner tube T2 and the control signal of the negative half-cycle inner tube T3 follow the state change of the corresponding signal modulation wave based on the current cycle type; the internal signal of the logic unit also includes a positive half-cycle inner tube enable signal T2EN, a positive half-cycle inner tube forced setting signal T2FORCE, a negative half-cycle inner tube enable signal T3EN, and a negative half-cycle inner tube forced setting signal T3FORCE; the positive half-cycle inner tube T 2, is always in the off state when the tube enable signal T2EN is set low in the positive half cycle, is allowed to become the on state when the tube enable signal T2EN is set in the positive half cycle, and becomes the on state when the tube enable signal T2EN is set in the positive half cycle and the tube forced setting signal T2FORCE is set in the positive half cycle; the control signal of the tube T3 in the negative half cycle is always in the off state when the tube enable signal T3EN is set low in the negative half cycle, is allowed to become the on state when the tube enable signal T3EN is set in the negative half cycle, and becomes the on state when the tube enable signal T3EN is set in the negative half cycle and the tube forced setting signal T3FORCE is set in the negative half cycle.

[0033] In this embodiment, the tube enable signal T2EN / T3EN in the positive / negative half cycle and the tube forced setting signal T2FORCE / T3FORCE in the positive / negative half cycle are used to control the switch action and state of the tube in the positive / negative half cycle to ensure the normal operation of the inverter bridge. When the tube enable signal T2EN in the positive half cycle is set low, the control signal of the tube T2 in the positive half cycle is always in the off state. That is, no matter how other signals change, as long as T2EN is at a low level, T2 will remain closed. When the tube enable signal T2EN in the positive half cycle is set (i.e., becomes a high level), the control signal of T2 is allowed to become the on state, but whether it is actually turned on at this time depends on the state of the tube forced setting signal T2FORCE in the positive half cycle. If the tube enable signal T2EN in the positive half cycle is set and the tube forced setting signal T2FORCE in the positive half cycle is also set, the control signal of T2 becomes the on state, and T2 is turned on. Similarly, when the tube enable signal T3EN in the negative half cycle is set low, the control signal of the tube T3 in the negative half cycle is always in the off state. When the tube enable signal T3EN in the negative half cycle is set, the control signal of T3 is allowed to become the on state. Whether it is turned on depends on the state of the tube forced setting signal T3FORCE in the negative half cycle. If the tube enable signal T3EN in the negative half cycle is set and the tube forced setting signal T3FORCE in the negative half cycle is also set, the control signal of T3 becomes the on state and T3 is turned on. In the embodiment of the present application, by introducing the tube enable signal T2EN in the positive half cycle and the tube enable signal T3EN in the negative half cycle, the system can more accurately control the switching state of T2 and T3, thereby avoiding unnecessary switching actions and reducing losses. When T2 and T3 need to be turned on or off quickly, by directly setting or lowering the T2FORCE and T3FORCE signals, their control states can be quickly changed without waiting for other complex logical judgments, thereby improving the response speed of the system.

[0034] In the embodiment of the present application, optionally, the control signal of the tube T2 in the positive half cycle follows the change of the first signal modulation wave PWMA when the tube enable signal T2EN in the positive half cycle is set, the tube forced setting signal T2FORCE in the positive half cycle is set low, and the periodic state signal PWMD_ACTIVE is set; the control signal of the tube T2 in the positive half cycle follows the change of the second signal modulation wave P when the tube enable signal T2EN in the positive half cycle is set, the tube forced setting signal T2FORCE in the positive half cycle is set low, and the periodic state signal PWMD_ACTIVE is set low. The control signal of the tube T3 in the negative half cycle follows the change of the second signal modulation wave PWMB when the tube enable signal T3EN in the positive half cycle is set, the tube forced setting signal T3FORCE in the negative half cycle is set low, and the periodic state signal PWMD_ACTIVE is set; the control signal of the tube T3 in the negative half cycle follows the change of the first signal modulation wave PWMA when the tube enable signal T3EN in the positive half cycle is set, the tube forced setting signal T3FORCE in the negative half cycle is set low, and the periodic state signal PWMD_ACTIVE is set low.

[0035] In this embodiment, when T2EN is set, T2FORCE is set low, and PWMD_ACTIVE is set, the control signal of T2 follows the change of the first signal modulation wave PWMA, and the opening and closing of T2 is determined by the amplitude of PWMA. When PWMA is set, T2 is turned on; when PWMA is set low, T2 is turned off. When T2EN is set, T2FORCE is set low, and PWMD_ACTIVE is set low, the control signal of T2 follows the change of the second signal modulation wave PWMB. In this case, the opening and closing of T2 is determined by the amplitude of PWMB, not PWMA. When T3EN is set, T3FORCE is set low, and PWMD_ACTIVE is set, the control signal of T3 follows the change of the second signal modulation wave PWMB, which means that the opening and closing of T3 is determined by the amplitude of PWMB. When T3EN is set, T3FORCE is set low, and PWMD_ACTIVE is set low, the control signal of T3 follows the change of the first signal modulation wave PWMA.

[0036] In an embodiment of the present application, optionally, after entering the zero-crossing switching lock state of switching from the first cycle to the second cycle, the tube enable signal within the first half cycle is sequentially set low to low the tube signal within the first half cycle, the tube forced setting signal within the second half cycle is set to force the tube signal within the second half cycle, the tube signal outside the first half cycle is set low, the first half cycle clamped tube signal is set, the tube enable signal and the forced setting signal within the second half cycle are both set low to force low the tube signal within the second half cycle, the tube enable signal and the forced setting signal within the first half cycle are both set to force the tube signal within the first half cycle, the second half cycle clamped tube signal is set low, the second half cycle outer tube signal is set, and when any one of the first signal modulation wave and the second signal modulation wave has a falling edge, the tube forced setting signal within the first half cycle is set low, the tube enable signal within the second half cycle is set, and the lock signal LOCK is set low.

[0037] In this embodiment, if Figure 3As shown, the zero-crossing switching lock state of switching from the first cycle to the second cycle is entered. This state is to ensure that the switching of the switch tube is safe and orderly during the cycle switching process. The tube enable signal in the first half cycle (for example, T2EN, assumed to be the tube enable signal in the positive half cycle) is set low to set the tube signal in the first half cycle (that is, the control signal of T2) to ensure that T2 remains in a closed state during the switching process. The tube forced setting signal in the second half cycle (for example, T3FORCE, assumed to be the tube forced setting signal in the negative half cycle) is set to force the tube signal in the second half cycle (that is, the control signal of T3) to prepare for the opening of T3. The outer tube signal in the first half cycle (for example, the outer tube control signal corresponding to T2) is set low to ensure that the outer tube also remains in a closed state during the switching process. The clamping tube signal in the first half cycle (for example, the switch tube control signal for clamping the midpoint potential) is set to stabilize the midpoint potential to prevent excessive voltage fluctuations during the switching process. The tube enable signal and the forced set signal in the second half cycle are both set low to force the tube signal in the second half cycle (i.e., the control signal of T3) to be low, ensuring that T3 can switch as expected in the subsequent steps. The tube enable signal and the forced set signal in the first half cycle are both set to force the tube signal in the first half cycle (i.e., the control signal of T2) to be set to prepare for the reopening of T2. The clamp tube signal in the second half cycle is set low to prepare for the clamp tube switching in the second cycle. The outer tube signal in the second half cycle is set to prepare for the opening of the outer tube in the second cycle. Wait for a falling edge to appear in any one of the first signal modulation wave and the second signal modulation wave. This falling edge is the opportunity to trigger the subsequent switching action. When the falling edge is detected, the tube forced set signal in the first half cycle is set low to end the forced set state of T2. The tube enable signal in the second half cycle is set to allow T3 to perform normal switching actions according to the modulation wave signal. The lock signal LOCK is set low, indicating that the zero-crossing switching lock state ends, and the system can normally enter the second cycle of operation. The embodiment of the present application improves the safety of the system by finely controlling the switching sequence and state of the switch tube to ensure that no transient high voltage or short circuit is generated during the cycle switching process. It also helps to reduce unnecessary switching of the switch tube, reduce losses, and maintain the stability of the midpoint potential, thereby enhancing the stability of the system.

[0038] In the embodiment of the present application, optionally, after entering the zero-crossing switching lock state of switching from the first cycle to the second cycle, the tube enable signal in the first half cycle is set low to low the tube signal in the first half cycle, the forced setting signal in the second half cycle is set after waiting for a delay t0 to force the tube signal in the second half cycle, the outer tube signal in the first half cycle is set low after waiting for a delay t1, the clamping tube signal in the first half cycle is set after waiting for a delay t2, and the tube enable signal and the forced setting signal in the second half cycle are set low after waiting for a delay t3 to force the tube signal in the second half cycle to low. Forcefully set the tube signal in the second half cycle to low, wait for delay t4 and then set both the tube enable signal and the forced set signal in the first half cycle to forcefully set the tube signal in the first half cycle, wait for delay t5 and then set the second half cycle clamp tube signal to low, wait for delay t6 and then set the second half cycle outer tube signal, wait for delay t7 and then wait for any one of the first signal modulation wave and the second signal modulation wave to have a falling edge, then set the tube forced set signal in the first half cycle to low, set the tube enable signal in the second half cycle, and set the lock signal LOCK to low.

[0039] In this embodiment, for the operation flow after the zero-crossing switching lock state of the ANPC type three-level inverter switching from the first cycle to the second cycle, a delay control (t0, t1, t2, t3, t4, t5, t6, t7) is introduced to ensure the smoothness and safety of the switching process. When it is detected that it is necessary to switch from the first cycle to the second cycle, the zero-crossing switching lock state is first entered to prepare for the subsequent switching operation. The tube enable signal (such as T2EN) in the first half cycle is set low to turn off the tube (such as T2) in the first half cycle. This is to ensure that T2 will not be accidentally turned on during the switching process. After the delay t0, the tube forced setting signal (such as T3FORCE) in the second half cycle is set to prepare to turn on the tube (such as T3) in the second half cycle. The delay t0 is to ensure that T2 is completely closed to avoid short circuit when T3 is turned on. After the delay t1, the first half cycle outer tube signal is set low to turn off the outer tube corresponding to T2. The delay t1 is to ensure that the off state of T2 has stabilized and to provide enough time for the outer tube to be turned off. After the delay t2, the first half-cycle clamping tube signal is set to stabilize the midpoint potential. The delay t2 is to ensure that the system state is stable before the clamping tube is turned on to avoid midpoint potential fluctuations. After the delay t3, the tube enable signal and the forced set signal in the second half-cycle are both set low to force the tube (such as T3) in the second half-cycle to be turned off. This step may be necessary in some cases to ensure that T3 can be switched as expected in subsequent steps. The delay t3 is to ensure that the off state of T3 has stabilized. After the delay t4, the tube enable signal and the forced set signal in the first half-cycle are both set to prepare to reopen the tube (such as T2) in the first half-cycle. The delay t4 is to ensure that the system state is stable before T2 is reopened. After the delay t5, the second half-cycle clamping tube signal is set low to prepare for the clamping tube switching in the second cycle. The delay t5 is to ensure that the system state is stable before the clamp tube is closed. After the delay t6, the second half cycle external tube signal is set to open the second cycle external tube. The delay t6 is to ensure that the system state is stable before the external tube is opened, and to provide enough time for the opening of the external tube. After the delay t7, wait for the first signal modulation wave and the second signal modulation wave to have a falling edge. This falling edge is the opportunity to trigger the subsequent switching action. The delay t7 is to ensure that the system state is stable before the falling edge is detected, and to provide enough time to prepare for the switching action. When the falling edge is detected, the tube forced setting signal in the first half cycle is set low to end the forced setting state of T2. This step is to allow T2 to switch according to the natural change of the modulation wave. The tube enable signal in the second half cycle is set to allow T3 to switch normally according to the modulation wave signal. This step marks the completion of the switching process, and T3 can now switch according to the change of the modulation wave.The lock signal LOCK is set low, indicating that the zero-crossing switching lock state is over. At this point, the system can normally enter the second cycle of operation. Through reasonable delay control, the switching process can be ensured to be smooth and safe, while optimizing the output waveform and improving the power quality and efficiency.

[0040] In addition, optionally, the switch tube includes any one of IGBT, MOSFET, and SIC MOSFET.

[0041] Specifically, in the zero-crossing switching process of the positive and negative half cycles: sequentially executing: setting the positive half cycle inner tube enable signal T2EN low to turn off the positive half cycle inner tube T2, waiting for the delay t0 and then setting the negative half cycle inner tube forced setting signal T3FORCE to force the negative half cycle inner tube T3 to be turned on, waiting for the delay t1 and then turning off the positive half cycle outer tube T1, waiting for the delay t2 and then turning on the positive half cycle clamp tube T5, waiting for the delay t3 and then setting the negative half cycle inner tube enable signal T3FORCE and the negative half cycle forced setting signal T3EN low to force the negative half cycle inner tube T3 to be turned off, waiting for the delay t4 and then turning on the positive half cycle inner tube T5. The enable signal T2FORCE and the positive half-cycle forced setting signal T2EN are both set to force the opening of the positive half-cycle inner tube T2, wait for the delay t5 to turn off the negative half-cycle clamping tube T6, wait for the delay t6 to turn on the negative half-cycle outer tube T4, wait for the delay t7 to wait for any one of the first signal modulation wave and the second signal modulation wave to have a falling edge, then set the positive half-cycle inner tube forced setting signal T2FORCE low to cancel the forced opening of the positive half-cycle inner tube T2, set the negative half-cycle inner tube enable signal T3EN to enable the negative half-cycle inner tube T3, and set the lock signal LOCK low to cancel the locked state.

[0042] During the zero-crossing switching process of the negative and positive half-cycles: sequentially set the negative half-cycle internal tube enable signal T3EN low to turn off the negative half-cycle internal tube T3, wait for the delay t0 and then set the positive half-cycle internal tube forced setting signal T2FORCE to force the positive half-cycle internal tube T2 to be turned on, wait for the delay t1 and then turn off the negative half-cycle external tube T4, wait for the delay t2 and then turn on the negative half-cycle clamp tube T6, wait for the delay t3 and then set both the positive half-cycle internal tube enable signal T2FORCE and the positive half-cycle forced setting signal T2EN low to force the positive half-cycle internal tube T2 to be turned off, wait for the delay t4 and then enable the negative half-cycle internal tube The signal T2FORCE and the negative half-cycle forced setting signal T3EN are both set to force the opening of the negative half-cycle inner tube T3, wait for the delay t5 to turn off the positive half-cycle clamping tube T5, wait for the delay t6 to turn on the positive half-cycle outer tube T1, wait for the delay t7 to wait for any one of the first signal modulation wave and the second signal modulation wave to have a falling edge, then set the negative half-cycle inner tube forced setting signal T3FORCE low to cancel the forced opening of the negative half-cycle inner tube T3, set the positive half-cycle inner tube enable signal T2EN to enable the positive half-cycle inner tube T2, and set the lock signal LOCK low to cancel the locked state.

[0043] Further, as a refinement and extension of the specific implementation of the above embodiment, in order to fully illustrate the specific implementation process of this embodiment, another zero-crossing switching method of an ANPC type three-level inverter is provided, the method comprising:

[0044] S1, when detecting the state change of the periodic modulation wave PWMD output by the processor, waiting for the falling edge of any one of the first signal modulation wave PWMA and the second signal modulation wave PWMB to appear, performing state switching, and setting the locking signal LOCK at the same time, entering the zero-crossing switching locking state of switching from the first cycle to the second cycle;

[0045] S2, sequentially execute the steps of setting the tube enable signal in the first half cycle low to low the tube signal in the first half cycle, setting the tube forced setting signal in the second half cycle to forcefully set the tube signal in the second half cycle, setting the tube signal outside the first half cycle low, setting the first half cycle clamping tube signal, setting both the tube enable signal and the forced setting signal in the second half cycle low to forcefully low the tube signal in the second half cycle, setting both the tube enable signal and the forced setting signal in the first half cycle to forcefully set the tube signal in the first half cycle, setting the second half cycle clamping tube signal low, setting the tube signal outside the second half cycle, waiting for a falling edge to appear in either the first signal modulation wave or the second signal modulation wave, setting the tube forced setting signal in the first half cycle low, setting the tube enable signal in the second half cycle, and setting the lock signal LOCK low.

[0046] In the embodiment of the present application, optionally, when the first cycle is a positive half cycle and the second cycle is a negative half cycle, S2 includes: sequentially executing the steps of setting the positive half cycle internal tube enable signal T2EN low to turn off the positive half cycle internal tube T2, waiting for a delay t0 and setting the negative half cycle internal tube forced setting signal T3FORCE to force the negative half cycle internal tube T3 to be turned on, waiting for a delay t1 and turning off the positive half cycle external tube T1, waiting for a delay t2 and turning on the positive half cycle clamping tube T5, waiting for a delay t3 and setting both the negative half cycle internal tube enable signal T3FORCE and the negative half cycle forced setting signal T3EN low to force the negative half cycle internal tube T3 to be turned off , after waiting for delay t4, set both the positive half-cycle tube enable signal T2FORCE and the positive half-cycle forced setting signal T2EN to force the opening of the positive half-cycle tube T2, wait for delay t5 to turn off the negative half-cycle clamp tube T6, wait for delay t6 to turn on the negative half-cycle external tube T4, wait for delay t7, wait for any one of the first signal modulation wave and the second signal modulation wave to have a falling edge, then set the positive half-cycle tube forced setting signal T2FORCE low to cancel the forced opening of the positive half-cycle tube T2, set the negative half-cycle tube enable signal T3EN to enable the negative half-cycle tube T3, and set the lock signal LOCK low to cancel the lock state.

[0047] In the embodiment of the present application, optionally, when the first cycle is the negative half cycle and the second cycle is the positive half cycle, S2 includes: sequentially executing the steps of setting the negative half cycle internal tube enable signal T3EN low to turn off the negative half cycle internal tube T3, waiting for the delay t0 and setting the positive half cycle internal tube forced setting signal T2FORCE to force the positive half cycle internal tube T2 to be turned on, waiting for the delay t1 and turning off the negative half cycle external tube T4, waiting for the delay t2 and turning on the negative half cycle clamping tube T6, waiting for the delay t3 and setting both the positive half cycle internal tube enable signal T2FORCE and the positive half cycle forced setting signal T2EN low to force the positive half cycle internal tube T2 to be turned off , after waiting for delay t4, set both the negative half-cycle internal tube enable signal T2FORCE and the negative half-cycle forced setting signal T3EN to force the negative half-cycle internal tube T3 to be turned on, wait for delay t5 to turn off the positive half-cycle clamp tube T5, wait for delay t6 to turn on the positive half-cycle external tube T1, wait for delay t7, wait for any one of the first signal modulation wave and the second signal modulation wave to have a falling edge, then set the negative half-cycle internal tube forced setting signal T3FORCE low to cancel the forced opening of the negative half-cycle internal tube T3, set the positive half-cycle internal tube enable signal T2EN to enable the positive half-cycle internal tube T2, and set the lock signal LOCK low to cancel the locked state.

[0048] It should be noted that for other corresponding descriptions of the zero-crossing switching method of an ANPC type three-level inverter provided in the embodiment of the present application, reference can be made to Figures 1 to 3 The corresponding description in the control system of the ANPC type three-level inverter will not be repeated here.

[0049] The processor involved in each embodiment provided in this application may be a general-purpose processor, a digital signal processor, a programmable logic device, etc., but is not limited thereto.

[0050] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A control system for an ANPC type three-level inverter, characterized in that: include: Processor, programmable logic unit and ANPC type three-level inverter; The processor is used to generate a modulation wave as an output signal of the processor based on an internal signal of the processor, wherein the modulation wave includes a first signal modulation wave PWMA, a second signal modulation wave PWMB, and a periodic modulation wave PWMD; The programmable logic unit is used to generate a control signal for each switch tube in the ANPC type three-level inverter based on the modulation wave and the internal signal of the logic unit; The ANPC type three-level inverter is used to control the switching of each switch tube based on the control signal of each switch tube output by the programmable logic unit; the switch tubes in the ANPC type three-level inverter include a positive half-cycle outer tube T1, a positive half-cycle inner tube T2, a positive half-cycle clamping tube T5, a negative half-cycle outer tube T4, a negative half-cycle inner tube T3, and a negative half-cycle clamping tube T6; The internal signals of the logic unit include a periodic state signal PWMD_ACTIVE and a locking signal LOCK; after the state of the periodic modulation wave PWMD changes, the periodic state signal PWMD_ACTIVE waits for a falling edge to appear in any one of the first signal modulation wave PWMA and the second signal modulation wave PWMB, and then switches the state, and at the same time sets the locking signal LOCK to enter a zero-crossing switching locking state; when the locking signal LOCK is in the set state, the control signal of the tube T2 in the positive half cycle and the control signal of the tube T3 in the negative half cycle no longer follow the state change of the signal modulation wave.

2. The control system of the ANPC type three-level inverter according to claim 1, characterized in that: The periodic modulation wave PWMD is set when the internal signal of the processor is in the positive half cycle, and is set low when the internal signal of the processor is in the negative half cycle; the first signal modulation wave PWMA and the second signal modulation wave PWMB are generated based on the signal of the absolute value of the internal signal of the processor, and there is a dead time between the first signal modulation wave and the second signal modulation wave.

3. The control system of the ANPC type three-level inverter according to claim 2, characterized in that: When the lock signal LOCK is in a low state, the control signals of the positive half-cycle outer tube T1, the positive half-cycle clamp tube T5, the negative half-cycle outer tube T4, and the negative half-cycle clamp tube T6 remain unchanged, and the control signal of the positive half-cycle inner tube T2 and the control signal of the negative half-cycle inner tube T3 follow the state change of the corresponding signal modulation wave based on the current cycle type; The logic unit internal signal also includes a tube enable signal T2EN in the positive half cycle, a tube forced set signal T2FORCE in the positive half cycle, a tube enable signal T3EN in the negative half cycle, and a tube forced set signal T3FORCE in the negative half cycle; The control signal of the tube T2 in the positive half cycle is always in the off state when the tube enable signal T2EN in the positive half cycle is set low, is allowed to become the on state when the tube enable signal T2EN in the positive half cycle is set, and becomes the on state when the tube enable signal T2EN in the positive half cycle is set and the tube forced setting signal T2FORCE in the positive half cycle is set; The control signal of the tube T3 in the negative half cycle is always in the off state when the tube enable signal T3EN in the negative half cycle is set low, is allowed to become the on state when the tube enable signal T3EN in the negative half cycle is set, and becomes the on state when the tube enable signal T3EN in the negative half cycle is set and the tube forced setting signal T3FORCE in the negative half cycle is set.

4. The control system of the ANPC type three-level inverter according to claim 3, characterized in that: The control signal of the tube T2 in the positive half cycle follows the change of the first signal modulation wave PWMA when the tube enable signal T2EN in the positive half cycle is set, the tube forced setting signal T2FORCE in the positive half cycle is set low, and the period state signal PWMD_ACTIVE is set; The control signal of the tube T2 in the positive half cycle follows the change of the second signal modulation wave PWMB when the tube enable signal T2EN in the positive half cycle is set, the tube forced setting signal T2FORCE in the positive half cycle is set low, and the period state signal PWMD_ACTIVE is set low; The control signal of the tube T3 in the negative half cycle follows the change of the second signal modulation wave PWMB when the tube enable signal T3EN in the positive half cycle is set, the tube forced setting signal T3FORCE in the negative half cycle is set low, and the cycle state signal PWMD_ACTIVE is set; The control signal of the tube T3 in the negative half cycle follows the change of the first signal modulation wave PWMA when the tube enable signal T3EN in the positive half cycle is set, the tube forced setting signal T3FORCE in the negative half cycle is set low, and the period state signal PWMD_ACTIVE is set low.

5. The control system of the ANPC type three-level inverter according to claim 4, characterized in that: After entering the zero-crossing switching lock state of switching from the first cycle to the second cycle, the tube enable signal in the first half cycle is set low to low the tube signal in the first half cycle, the tube forced setting signal in the second half cycle is set to force the tube signal in the second half cycle, the tube signal outside the first half cycle is set low, the clamped tube signal in the first half cycle is set, the tube enable signal and the forced setting signal in the second half cycle are both set low to force low the tube signal in the second half cycle, the tube enable signal and the forced setting signal in the first half cycle are both set to force the tube signal in the first half cycle, the clamped tube signal in the second half cycle is set low, the tube signal outside the second half cycle is set, and when any one of the first signal modulation wave and the second signal modulation wave has a falling edge, the tube forced setting signal in the first half cycle is set low, the tube enable signal in the second half cycle is set, and the lock signal LOCK is set low.

6. The control system of the ANPC type three-level inverter according to claim 5, characterized in that: After entering the zero-crossing switching lock state of switching from the first cycle to the second cycle, the first cycle half cycle tube enable signal is set low to low the tube signal in the first cycle half cycle, the second cycle half cycle tube forced setting signal is set after waiting for delay t0 to force the tube signal in the second cycle half cycle, the first cycle half cycle outer tube signal is set low after waiting for delay t1, the first cycle half cycle clamp tube signal is set after waiting for delay t2, and the second cycle half cycle tube enable signal and forced setting signal are set low after waiting for delay t3 to force the second cycle half cycle tube signal to low. The tube signal within the half cycle is set, and after waiting for delay t4, the tube enable signal and the forced set signal within the first half cycle are set to force the tube signal within the first half cycle, and after waiting for delay t5, the second half cycle clamp tube signal is set low, and after waiting for delay t6, the second half cycle outer tube signal is set, and after waiting for delay t7, when any one of the first signal modulation wave and the second signal modulation wave appears a falling edge, the tube forced set signal within the first half cycle is set low, the tube enable signal within the second half cycle is set, and the lock signal LOCK is set low.

7. The control system of the ANPC type three-level inverter according to any one of claims 1 to 6, characterized in that: The switch tube includes any one of IGBT, MOSFET and SIC MOSFET.

8. A zero-crossing switching method for an ANPC type three-level inverter, characterized in that: A control system for an ANPC type three-level inverter as claimed in any one of claims 1 to 7, comprising: When a state change of the periodic modulation wave PWMD output by the processor is detected, the state is switched when a falling edge appears in any one of the first signal modulation wave PWMA and the second signal modulation wave PWMB, and the locking signal LOCK is set to enter a zero-crossing switching locking state from the first cycle to the second cycle; The steps are executed in sequence: setting the tube enable signal in the first half cycle low to low the tube signal in the first half cycle, setting the tube forced setting signal in the second half cycle to force the tube signal in the second half cycle, setting the tube signal outside the first half cycle low, setting the first half cycle clamping tube signal, setting both the tube enable signal and the forced setting signal in the second half cycle low to force the tube signal in the second half cycle low, setting both the tube enable signal and the forced setting signal in the first half cycle to force the tube signal in the first half cycle to low, setting the tube enable signal and the forced setting signal in the first half cycle to force the tube signal in the first half cycle, setting the second half cycle clamping tube signal low, setting the tube signal outside the second half cycle, waiting for a falling edge in any one of the first signal modulation wave and the second signal modulation wave to low the tube forced setting signal in the first half cycle, setting the tube enable signal in the second half cycle, and setting the lock signal LOCK low.

9. The method according to claim 8, characterized in that In the case where the first cycle is a positive half cycle and the second cycle is a negative half cycle, the sequential execution of setting the tube enable signal in the first half cycle low to set the tube signal in the first half cycle low, setting the tube forced setting signal in the second half cycle to forcefully set the tube signal in the second half cycle, setting the tube signal outside the first half cycle low, setting the first half cycle clamped tube signal, setting both the tube enable signal and the forced setting signal in the second half cycle low to forcefully set the tube signal in the second half cycle low, setting both the tube enable signal and the forced setting signal in the first half cycle to forcefully set the tube signal in the first half cycle, setting the second half cycle clamped tube signal low, setting the tube signal outside the second half cycle, waiting for a falling edge in either the first signal modulation wave or the second signal modulation wave to set the tube forced setting signal in the first half cycle low, setting the tube enable signal in the second half cycle, and setting the lock signal LOCK low includes: The steps are as follows: set the positive half-cycle internal tube enable signal T2EN low to turn off the positive half-cycle internal tube T2; after waiting for delay t0, set the negative half-cycle internal tube forced set signal T3FORCE to force the negative half-cycle internal tube T3 to be turned on; after waiting for delay t1, turn off the positive half-cycle external tube T1; after waiting for delay t2, turn on the positive half-cycle clamp tube T5; after waiting for delay t3, set both the negative half-cycle internal tube enable signal T3FORCE and the negative half-cycle forced set signal T3EN low to force the negative half-cycle internal tube T3 to be turned off; after waiting for delay t4, set the positive half-cycle internal tube enable signal T2FORCE to high CE and the positive half-cycle forced setting signal T2EN are both set to force the opening of the positive half-cycle inner tube T2, wait for delay t5 to turn off the negative half-cycle clamping tube T6, wait for delay t6 to turn on the negative half-cycle outer tube T4, wait for delay t7 to wait for any one of the first signal modulation wave and the second signal modulation wave to have a falling edge, then set the positive half-cycle inner tube forced setting signal T2FORCE low to cancel the forced opening of the positive half-cycle inner tube T2, set the negative half-cycle inner tube enable signal T3EN to enable the negative half-cycle inner tube T3, and set the lock signal LOCK low to cancel the locked state.

10. The method according to claim 8, characterized in that In the case where the first cycle is a negative half cycle and the second cycle is a positive half cycle, the sequential execution of setting the tube enable signal in the first half cycle low to set the tube signal in the first half cycle low, setting the tube forced setting signal in the second half cycle to forcefully set the tube signal in the second half cycle, setting the tube signal outside the first half cycle low, setting the first half cycle clamped tube signal, setting both the tube enable signal and the forced setting signal in the second half cycle low to forcefully set the tube signal in the second half cycle low, setting both the tube enable signal and the forced setting signal in the first half cycle to forcefully set the tube signal in the first half cycle, setting the second half cycle clamped tube signal low, setting the tube signal outside the second half cycle, waiting for a falling edge in either the first signal modulation wave or the second signal modulation wave to set the tube forced setting signal in the first half cycle low, setting the tube enable signal in the second half cycle, and setting the lock signal LOCK low includes: The steps are as follows: set the negative half-cycle internal tube enable signal T3EN low to turn off the negative half-cycle internal tube T3; after waiting for delay t0, set the positive half-cycle internal tube forced set signal T2FORCE to force the positive half-cycle internal tube T2 to be turned on; after waiting for delay t1, turn off the negative half-cycle external tube T4; after waiting for delay t2, turn on the negative half-cycle clamp tube T6; after waiting for delay t3, set both the positive half-cycle internal tube enable signal T2FORCE and the positive half-cycle forced set signal T2EN low to force the positive half-cycle internal tube T2 to be turned off; after waiting for delay t4, set the negative half-cycle internal tube enable signal T2FORCE to high. CE and the negative half-cycle forced setting signal T3EN are both set to force the opening of the negative half-cycle inner tube T3, wait for the delay t5 to turn off the positive half-cycle clamping tube T5, wait for the delay t6 to turn on the positive half-cycle outer tube T1, wait for the delay t7 to wait for any one of the first signal modulation wave and the second signal modulation wave to have a falling edge, then set the negative half-cycle inner tube forced setting signal T3FORCE low to cancel the forced opening of the negative half-cycle inner tube T3, set the positive half-cycle inner tube enable signal T2EN to enable the positive half-cycle inner tube T2, and set the lock signal LOCK low to cancel the locked state.

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