Ultra-wideband passive delayer

Abstract

The invention relates to an ultra-wideband passive delayer, which comprises a plurality of delay units with different delay durations and a control unit, the first time delay unit receives a signal in a full frequency band range; each delay unit comprises two single-pole double-throw switches, and a passive delayer and a transmission unit which are arranged between the two single-pole double-throw switches; in one delay unit, the control ends of the two single-pole double-throw switches are connected with the control unit, and the passive delayer or the transmission unit is synchronously switched on in response to different control signals sent by the control unit, so that the passive delayer delays the signals input into the passive delayer; the signal after the time delay processing is transmitted to the next time delay unit; or, the transmission unit transmits the signal input into the transmission unit to the next delay unit. The device is not limited by bandwidth, can process radar signals in an ultra-wide range in a high-quality mode, and meets design requirements.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to an ultra-wideband passive delay device. Background Art

[0002] Ultra Wide Band (UWB) technology is a wireless carrier communication technology that does not use a sinusoidal carrier but uses nanosecond non-sinusoidal narrow pulses to transmit data, so it occupies a wide spectrum range. It solves the major propagation problems that have plagued traditional wireless communication technology for many years. It has the advantages of being insensitive to channel fading, low power spectrum density of transmitted signals, low interception rate, low system complexity, and being able to provide a positioning accuracy of several centimeters. With the development of ultra-wideband radar, traditional delay devices are limited by bandwidth and cannot process ultra-wide range radar signals, which can no longer meet the design requirements. Summary of the invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides an ultra-wideband passive delay device. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0004] The present invention provides an ultra-wideband passive delay device, comprising: a plurality of delay units with different delay time lengths, and a control unit; the control ends of the plurality of delay units are connected to the control unit; the first delay unit among the plurality of delay units receives signals in the full frequency band; wherein each delay unit comprises: two single-pole double-throw switches, and a passive delay device and a transmission unit arranged between the two single-pole double-throw switches; in one delay unit, the control ends of the two single-pole double-throw switches are connected to the control unit, and are used to synchronously turn on the passive delay device or the transmission unit in response to different control signals sent by the control unit, so that the passive delay device delays the signal input to the passive delay device, and transmits the delayed signal to the next delay unit; or, so that the transmission unit transmits the signal input to the transmission unit to the next delay unit.

[0005] Compared with the prior art, the present invention has the following beneficial effects:

[0006] Aiming at the problem that the traditional delay device is limited by bandwidth and cannot process ultra-wide range radar signals, and can no longer meet the design requirements, the present invention proposes an ultra-wideband passive delay device, which includes several delay units with different delay time lengths, and each delay unit is provided with two pass paths, one path can delay the input full-band signal, and the other can transmit the input signal to the next unit, wherein two single-pole double-throw switches are synchronously turned on or off in response to the control signal to determine the specific communication path of the signal, which can effectively improve the control accuracy of the delay device; based on the different conduction states of several units, the delay devices of different frequency bands are simulated to flexibly process the input full-band signal, which can greatly expand the bandwidth, and by setting the delay time length of each delay unit to be different, small delay units and large delay units can be covered, which helps to improve the delay flatness of the device, reduce insertion loss, well retain the characteristics and power of the input signal, and ensure the signal transmission quality. Based on the ultra-wideband passive delay device proposed by the present invention, it can process ultra-wide range radar signals with high quality without being limited by bandwidth, meeting the design requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a structural block diagram of an ultra-wideband passive delay device provided by an embodiment of the present invention;

[0008] Figure 2 is an example block diagram of an ultra-wideband passive delay device provided by an embodiment of the present invention;

[0009] Figure 3 is a circuit connection diagram of a first passive delay device provided by an embodiment of the present invention;

[0010] Figure 4 is a circuit connection diagram of a second passive delay device provided by an embodiment of the present invention;

[0011] Figure 5 is a circuit connection diagram of a fourth passive delay device provided in an embodiment of the present invention;

[0012] Figure 6 is a circuit connection block diagram of a fifth passive delay device provided by an embodiment of the present invention;

[0013] Figure 7 is a circuit connection block diagram of a sixth passive delay device provided by an embodiment of the present invention;

[0014] Figure 8 The embodiment of the present invention provides Figure 2 An example diagram of a normalized delay signal output by an ultra-wideband passive delay device when 12 single-pole double-throw switches turn on the passive delay device and / or the transmission unit;

[0015] Fig. 9The embodiment of the present invention provides Figure 2 The test example diagram of the maximum delay error and root mean square error corresponding to the ultra-wideband passive delay device when processing signals in the full frequency band;

[0016] Fig.10 The embodiment of the present invention provides Figure 2 An example diagram of the corresponding insertion loss changes when the ultra-wideband passive delay device in the figure processes signals in the full frequency band under different delay states. DETAILED DESCRIPTION

[0017] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0018] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0019] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0020] The ultra-wideband passive delay device proposed by the present invention is now described in detail with reference to the accompanying drawings. Figure 1 FIG. 1 is a block diagram of the structure of an ultra-wideband passive delay device provided by an embodiment of the present invention. Figure 1As shown, the ultra-wideband passive delay device includes: a plurality of delay units with different delay times, and a control unit; the control ends of the plurality of delay units are connected to the control unit; the first delay unit among the plurality of delay units receives signals in the full frequency band; wherein each delay unit includes: two single-pole double-throw switches, and a passive delay device and a transmission unit arranged between the two single-pole double-throw switches; in a delay unit, the control ends of the two single-pole double-throw switches are connected to the control unit, and are used to synchronously turn on the passive delay device or the transmission unit in response to different control signals sent by the control unit, so that the signal input to the passive delay device is delayed, and the signal after the delay processing is transmitted to the next delay unit; or, so that the transmission unit transmits the signal input to the transmission unit to the next delay unit.

[0021] Here, the preset bandwidth range is 2GHz to 18GHz. The control unit is a digital control unit, which determines the route of the signal by sending a digital control signal to the single-pole double-throw switch. The digital control signal includes a high-level signal and a low-level signal. When the digital control signal is a high-level signal, the passive delay device is turned on, and when the digital control signal is a low-level signal, the transmission unit is turned on. Exemplarily, the voltage of the high-level signal is 2.5V, and the voltage of the low-level signal is 0V.

[0022] Here, using a single-pole double-throw switch can achieve good matching with the overall circuit, have high isolation and low insertion loss, thereby effectively reducing the insertion loss of the overall circuit. It should be noted that the single-pole double-throw switch in each delay unit is of the same type.

[0023] Figure 2 FIG. 1 is an example block diagram of an ultra-wideband passive delay device provided by an embodiment of the present invention. Figure 2 As shown, in a possible implementation, several delay units include: a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a fifth delay unit and a sixth delay unit; wherein, the transmission units in the first delay unit to the fourth delay unit are all transmission lines, and the transmission units in the fifth delay unit and the sixth delay unit are all-pass networks; and, the delay duration of the first delay unit is the shortest, and the delay duration of the sixth delay unit is the longest.

[0024] It should be noted that the structure, material and type of the transmission lines in different passive delay devices are the same. The all-pass network is an APN model, including: a first inductor, a second inductor, a first capacitor and a second capacitor; the two ends of the first capacitor are respectively used as a signal input end and a signal output end, one end of the first inductor and one end of the second inductor are connected to the signal input end and the signal output end, the other end of the first inductor and the other end of the second inductor are both connected to one end of the second capacitor, and the second capacitor is grounded.

[0025] It should be noted that the delay time corresponding to each delay unit is a relative delay time. Since the signal will generate a delay time when passing through the transmission unit, the difference between the delay time generated by the signal passing through the transmission unit and the delay time generated by the signal passing through the passive delay device is the delay time corresponding to each delay unit. Taking the fourth delay unit as an example, the delay time of the fourth passive delay device inside it is 54ps, and the delay time of the transmission unit connected in parallel with the fourth passive delay device is 6ps. The difference between the two is the relative delay time of the fourth delay unit (48ps).

[0026] Exemplarily, the (relative) delay time length of the first delay unit is 6ps, the (relative) delay time length of the second delay unit is 12ps, the (relative) delay time length of the third delay unit is 24ps, the (relative) delay time length of the fourth delay unit is 48ps, the (relative) delay time length of the fifth delay unit is 96ps, and the (relative) delay time length of the sixth delay unit is 192ps. When all six delay units are turned on, the input signal will be relatively delayed by (6+12+24+48+96+192)ps. When the six delay units are partially turned on, the delay time length corresponding to the turned-on delay unit is the delay time length of the input signal.

[0027] It should be understood that the delay time length corresponding to each delay unit here can be adjusted according to actual design requirements by adjusting the inductance or capacitance inside the delay unit to change the delay time length corresponding to the delay unit. For example, in order to improve the delay accuracy, the delay time length of the first delay unit is reduced to 3ps, and in order to provide a longer delay time length, the delay time length of the sixth delay unit can be increased to 220ps.

[0028] It should be understood that this is only an example, and in actual operation, the number of delay units can be increased or decreased according to needs.

[0029] In a possible implementation, in the first delay unit, the first passive delay device is connected in parallel with the transmission line line1 between the single-pole double-throw switch S1 and the single-pole double-throw switch S2. Figure 3 Schematic diagram of the circuit connection of the first passive delay device provided by the embodiment of the present invention. Figure 3 As shown, the first passive delay device includes: a capacitor C1, a capacitor C2 and an inductor L1; wherein, the inductor L1 is arranged between the single-pole double-throw switch S1 and the single-pole double-throw switch S2, the capacitor C1 is arranged between the inductor L1 and the single-pole double-throw switch S1, and one end of the capacitor C1 is grounded; the capacitor C2 is arranged between the inductor L1 and the single-pole double-throw switch S2, and one end of the capacitor C2 is grounded.

[0030] Here, the first passive delay device adopts an ATL model with a π-type CLC structure, which has a small model layout area and a simple structure. It only has an inductor L1 and two identical capacitors C1 and C2. It has high delay flatness and low insertion loss in the entire frequency band of 2-18GHz.

[0031] In a possible implementation, in the second delay unit, the second passive delay device is connected in parallel with the transmission line line2 between the single-pole double-throw switch S3 and the single-pole double-throw switch S4; in the third delay unit, the third passive delay device is connected in parallel with the transmission line line3 between the single-pole double-throw switch S5 and the single-pole double-throw switch S6; wherein the second passive delay device and the third passive delay device have the same structure. Specifically, the second passive delay device and the third passive delay device both adopt the APN structure, which occupies a smaller layout area than the ATL structure, has high delay flatness and low insertion loss in the full frequency band of 2GHz-18GHz.

[0032] Figure 4 Schematic diagram of the circuit connection of the second passive delay device provided by the embodiment of the present invention. Figure 4 As shown, the second passive delay device includes: a capacitor C3, a capacitor C4, an inductor L3 and an inductor L4; the capacitor C3 is arranged between the single-pole double-throw switch S3 and the single-pole double-throw switch S4, one end of the inductor L3 is arranged between the capacitor C3 and the single-pole double-throw switch S3, and the other end is connected to one end of the capacitor C4, one end of the inductor L4 is arranged between the capacitor C3 and the single-pole double-throw switch S4, and the other end is also connected to one end of the capacitor C4; the other end of the capacitor C4 is grounded.

[0033] Similarly, the third passive delay device includes: capacitor C5, capacitor C6, inductor L5 and inductor L6; capacitor C5 is arranged between single-pole double-throw switch S3 and single-pole double-throw switch S4, one end of inductor L5 is arranged between capacitor C5 and single-pole double-throw switch S3, and the other end is connected to one end of capacitor C6, one end of inductor L6 is arranged between capacitor C5 and single-pole double-throw switch S4, and the other end is also connected to one end of capacitor C6; the other end of capacitor C6 is grounded.

[0034] In a possible implementation, in the fourth delay unit, the fourth passive delay device is connected in parallel with the transmission line line4 between the single-pole double-throw switch S7 and the single-pole double-throw switch S8; Figure 5 is a circuit connection diagram of a fourth passive delay device provided in an embodiment of the present invention, such as Figure 5 As shown, the fourth passive delay device includes: a first delay module and a second delay module connected in sequence; the delay time of the first delay module is less than the delay time of the second delay module. Exemplarily, the delay time corresponding to the first delay module is 20ps, the delay time of the second delay module is 32ps, and the delay time of the transmission line line4 is 6ps.

[0035] Here, the first delay module includes two ATL models of π-type CLC structures connected in sequence. Specifically, the first delay module includes: inductor L7, inductor L8, inductor L9, inductor L10, inductor L11, inductor L12, capacitor C7, capacitor C8, capacitor C9 and capacitor C10; inductor L7 and inductor L8 are connected in sequence between single-pole double-throw switch S7 and the second delay module, capacitor C7 and inductor L9 are connected in series between inductor L7 and single-pole double-throw switch S7, and one end of inductor L9 is grounded; capacitor C8 and inductor L10 are connected in series between inductor L7 and inductor L8, and one end of inductor L10 is grounded; capacitor C9, inductor L11 are connected in parallel with capacitor C8 and inductor L10, and one end of inductor L11 is grounded; capacitor C10 and inductor L12 are connected in series between inductor L8 and the second delay module, and one end of inductor L12 is grounded.

[0036] Here, the capacitors C7, C8, C9 and C10 have the same structure, and the inductors L9, L10, L11 and L12 have the same value. This setting can ensure that the signal delay has a good flatness.

[0037] Here, the second delay module includes an APN model. Specifically, the second delay module includes: capacitor C11, capacitor C12, inductor L13 and inductor L14; capacitor C11 is arranged between inductor L8 and single-pole double-throw switch S8, one end of inductor L13 is connected to one end of capacitor C11, the other end of inductor L13 is connected to one end of capacitor C12, one end of inductor L14 is connected to the other end of capacitor C11, the other end of inductor L14 is connected to one end of capacitor C12, and the other end of capacitor C12 is grounded.

[0038] In one possible implementation, Figure 6 : is a circuit connection block diagram of a fifth passive delay device provided by an embodiment of the present invention, such as Figure 6 As shown, in the fifth delay unit, the fifth passive delay device and the all-pass network Ref-APN1 are connected in parallel between the single-pole double-throw switch S9 and the single-pole double-throw switch S10; the third delay module, the fourth delay module, the fifth delay module and the sixth delay module are connected in sequence; the structure of the third delay module and the fourth delay module is the same as the second delay module, and the structure of the fifth delay module and the sixth delay module is the same as the first delay module. Here, the delay length of the all-pass network Ref-APN1 is set to 12ps.

[0039] In one possible implementation, Figure 7 : is a circuit connection block diagram of a sixth passive delay device provided by an embodiment of the present invention, such as Figure 7As shown, in the sixth delay unit, the sixth passive delay device and the all-pass network Ref-APN2 are connected in parallel between the single-pole double-throw switch S11 and the single-pole double-throw switch S12; the sixth passive delay device includes: the seventh delay module, the eighth delay module, the ninth delay module, the tenth delay module, the eleventh delay module, the twelfth delay module, the thirteenth delay module and the fourteenth delay module; wherein, the structures of the seventh delay module, the eighth delay module, the ninth delay module and the tenth delay module are the same as those of the first delay module, and the structures of the eleventh delay module, the twelfth delay module, the thirteenth delay module and the fourteenth delay module are the same as those of the second delay module. Here, the delay length of the all-pass network Ref-APN2 is set to 24ps.

[0040] In order to verify the output effect of the ultra-wideband passive delay device provided by the present invention, a Figure 2 The circuit chip of the ultra-wideband passive delay device in the embodiment is soldered on the test fixture PCB to test it. Figure 8 The embodiment of the present invention provides Figure 2 An example diagram of the normalized delay signal output by the ultra-wideband passive delay device when 12 single-pole double-throw switches turn on the passive delay device and / or the transmission unit is shown in FIG. Figure 8 As shown, the vertical axis is the normalized group delay signal output by the ultra-wideband passive delay device, and the horizontal axis is the signal frequency range. The 6 delay units can produce 64 different delay states. Under different delay states, the adjustable effect of the normalized group delay changes approximately linearly with the signal frequency value, is less affected by the signal frequency, and has excellent flatness.

[0041] Fig. 9 The embodiment of the present invention provides Figure 2 The maximum delay error and RMS error of the ultra-wideband passive delay device in the test diagram when processing signals in the full frequency band. Fig. 9 As shown, the root mean square error (i.e. Fig. 9 The average value of RMS ERROR in is 4.1ps, and the maximum delay error (i.e. Fig. 9 The average value of MAX ERROR in is 8ps, which indicates that the ultra-wideband passive delay device provided in the embodiment of the present invention has extremely high control accuracy.

[0042] Fig.10 The embodiment of the present invention provides Figure 2 The following is an example of the insertion loss change when the ultra-wideband passive delay device in the figure processes the full-band signal under different delay states. Fig.10 As shown, under 64 different delay states, the insertion loss (S21) is in the range of 5dB to 18dB, and the RMS error of the delay is less than 6ps of the minimum delay unit, which can well preserve the characteristics and power of the input signal and ensure the quality of signal transmission.

[0043] Aiming at the problem that the traditional delay device is limited by bandwidth and cannot process ultra-wide range radar signals, and can no longer meet the design requirements, the present invention proposes an ultra-wideband passive delay device, which includes several delay units with different delay time lengths, and each delay unit is provided with two pass paths, one path can delay the input full-band signal, and the other can transmit the input signal to the next unit, wherein two single-pole double-throw switches are synchronously turned on or off in response to the control signal to determine the specific communication path of the signal, which can effectively improve the control accuracy of the delay device; based on the different conduction states of several units, the delay devices with different frequency bands are simulated to flexibly process the input full-band signal, which can greatly expand the bandwidth, and by setting the delay time length of each delay unit to be different, small delay units and large delay units can be covered, which helps to improve the delay flatness of the device, reduce insertion loss, well retain the characteristics and power of the input signal, and ensure the signal transmission quality. Based on the ultra-wideband passive delay device proposed by the present invention, it can process ultra-wide range radar signals with high quality without being limited by bandwidth, meeting the design requirements.

[0044] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. An ultra-wideband passive delay device, characterized in that: include: A plurality of delay units with different delay times, and a control unit; control ends of the plurality of delay units are connected to the control unit; a first delay unit among the plurality of delay units receives a signal in the full frequency band; wherein each delay unit comprises: two single-pole double-throw switches, and a passive delay device and a transmission unit arranged between the two single-pole double-throw switches; In a delay unit, the control ends of the two single-pole double-throw switches are connected to the control unit, and are used to synchronously turn on the passive delay device or the transmission unit in response to different control signals sent by the control unit, so that the passive delay device delays the signal input to the passive delay device and passes the delayed signal to the next delay unit; or, so that the transmission unit passes the signal input to the transmission unit to the next delay unit.

2. The ultra-wideband passive delay device according to claim 1, characterized in that: The several delay units include: a first delay unit, a second delay unit, a third delay unit, a fourth delay unit, a fifth delay unit and a sixth delay unit; wherein, the transmission units from the first delay unit to the fourth delay unit are all transmission lines, and the transmission units in the fifth delay unit and the sixth delay unit are all-pass networks; and, the delay duration of the first delay unit is the shortest, and the delay duration of the sixth delay unit is the longest.

3. The ultra-wideband passive delay device according to claim 2, characterized in that: In the first delay unit, the first passive delay device is connected in parallel with the transmission line line1 between the single-pole double-throw switch S1 and the single-pole double-throw switch S2; the first passive delay device includes: a capacitor C1, a capacitor C2 and an inductor L1; The inductor L1 is arranged between the single-pole double-throw switch S1 and the single-pole double-throw switch S2, the capacitor C1 is arranged between the inductor L1 and the single-pole double-throw switch S1, and one end of the capacitor C1 is grounded; the capacitor C2 is arranged between the inductor L1 and the single-pole double-throw switch S2, and one end of the capacitor C2 is grounded.

4. The ultra-wideband passive delay device according to claim 2, characterized in that: In the second delay unit, the second passive delay device is connected in parallel with the transmission line line2 between the single-pole double-throw switch S3 and the single-pole double-throw switch S4; in the third delay unit, the third passive delay device is connected in parallel with the transmission line line3 between the single-pole double-throw switch S5 and the single-pole double-throw switch S6; wherein the second passive delay device and the third passive delay device have the same structure.

5. The ultra-wideband passive delay device according to claim 4, characterized in that: The second passive delay device comprises: a capacitor C3, a capacitor C4, an inductor L3 and an inductor L4; The capacitor C3 is arranged between the single-pole double-throw switch S3 and the single-pole double-throw switch S4, one end of the inductor L3 is arranged between the capacitor C3 and the single-pole double-throw switch S3, and the other end is connected to one end of the capacitor C4, one end of the inductor L4 is arranged between the capacitor C3 and the single-pole double-throw switch S4, and the other end is also connected to one end of the capacitor C4; the other end of the capacitor C4 is grounded.

6. The ultra-wideband passive delay device according to claim 2, characterized in that: In the fourth delay unit, the fourth passive delay device is connected in parallel with the transmission line line4 between the single-pole double-throw switch S7 and the single-pole double-throw switch S8; wherein the fourth passive delay device includes: a first delay module and a second delay module connected in sequence; the delay duration of the first delay module is less than the delay duration of the second delay module.

7. The ultra-wideband passive delay device according to claim 6, characterized in that: The first delay module includes: inductor L7, inductor L8, inductor L9, inductor L10, inductor L11, inductor L12, capacitor C7, capacitor C8, capacitor C9 and capacitor C10; The inductor L7 and the inductor L8 are connected in sequence between the single-pole double-throw switch S7 and the second delay module; the capacitor C7 and the inductor L9 are connected in series between the inductor L7 and the single-pole double-throw switch S7, and one end of the inductor L9 is grounded; the capacitor C8 and the inductor L10 are connected in series between the inductor L7 and the inductor L8, and one end of the inductor L10 is grounded; the capacitor C9 and the inductor L11 are connected in parallel with the capacitor C8 and the inductor L10, and one end of the inductor L11 is grounded; the capacitor C10 and the inductor L12 are connected in series between the inductor L8 and the second delay module, and one end of the inductor L12 is grounded.

8. The ultra-wideband passive delay device according to claim 7, characterized in that: The second delay module includes: a capacitor C11, a capacitor C12, an inductor L13 and an inductor L14; The capacitor C11 is arranged between the inductor L8 and the single-pole double-throw switch S8, one end of the inductor L13 is connected to one end of the capacitor C11, the other end of the inductor L13 is connected to one end of the capacitor C12, one end of the inductor L14 is connected to the other end of the capacitor C11, the other end of the inductor L14 is connected to one end of the capacitor C12, and the other end of the capacitor C12 is grounded.

9. The ultra-wideband passive delay device according to claim 6, characterized in that: In the fifth delay unit, the fifth passive delay device and the all-pass network Ref-APN1 are connected in parallel between the single-pole double-throw switch S9 and the single-pole double-throw switch S10; The fifth passive delay device includes: a third delay module, a fourth delay module, a fifth delay module and a sixth delay module connected in sequence; the structure of the third delay module and the fourth delay module is the same as that of the second delay module, and the structure of the fifth delay module and the sixth delay module is the same as that of the first delay module.

10. The ultra-wideband passive delay device according to claim 6, characterized in that: In the sixth delay unit, the sixth passive delay device and the all-pass network Ref-APN2 are connected in parallel between the single-pole double-throw switch S11 and the single-pole double-throw switch S12; The sixth passive delay device includes: a seventh delay module, an eighth delay module, a ninth delay module, a tenth delay module, an eleventh delay module, a twelfth delay module, a thirteenth delay module and a fourteenth delay module connected in sequence; wherein, the structures of the seventh delay module, the eighth delay module, the ninth delay module and the tenth delay module are the same as those of the first delay module, and the structures of the eleventh delay module, the twelfth delay module, the thirteenth delay module and the fourteenth delay module are the same as those of the second delay module.

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