Electronic circuit and method

Abstract

The present specification relates to an electronic circuit and a method, the electronic circuit comprising: a first circuit configured to generate a plurality of second signals having offset voltage levels based on a first periodic analog signal; a second circuit configured to generate a third periodic digital signal in accordance with the second signal correspondingly crossing at least one threshold; and a third circuit configured to determine an amplitude range in which the first periodic analog signal is located according to the number of third periodic digital signals.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to French patent application No. 2310834, filed on October 10, 2023, entitled “Circuitélectronique,” ​​which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic circuits and methods of operating the same. Background Art

[0004] Electronic circuits, in particular microcontrollers, use periodic signals. These periodic signals may, for example, originate from an oscillator, in particular a crystal oscillator. Measurement and control of the oscillation amplitude helps to provide consistent operation from one circuit to another. Current circuits use a large chip surface area to perform this operation. Summary of the invention

[0005] There is a need to obtain an electronic circuit enabling measurement and control of the oscillation amplitude of a periodic signal while reducing the chip surface area used.

[0006] Embodiments overcome all or part of the disadvantages of known electronic circuits.

[0007] An embodiment provides an electronic circuit comprising: a first circuit configured to generate a plurality of second signals having offset voltage levels based on a first periodic analog signal; a second circuit configured to generate a third periodic digital signal in accordance with the second signal crossing at least one threshold; and a third circuit configured to determine an amplitude range in which the first signal is located based on the number of third signals present.

[0008] An embodiment provides an operating method for an electronic circuit, the operating method comprising: a first circuit of the electronic circuit generating a plurality of second signals having offset voltage levels based on a first periodic analog signal; a second circuit generating a third periodic digital signal in accordance with the second signal crossing at least one threshold; and a third circuit determining an amplitude range in which the first signal is located in accordance with the number of third signals present.

[0009] In an embodiment, each third signal is generated when the corresponding second signal crosses two thresholds.

[0010] In an embodiment, the electronic circuit comprises a fourth circuit configured to enable adjusting the amplitude of the first signal in dependence on the determination of the amplitude range.

[0011] In an embodiment, the third circuit includes three branches, each branch includes a plurality of flip-flops connected in series, and each branch is configured to receive one of the third signals at a clock input of the flip-flops of the branch, respectively.

[0012] In an embodiment, each branch includes at least two D-type flip-flops connected in series.

[0013] In an embodiment, the third circuit includes a first logic block configured to perform an AND function based on outputs of the series of flip-flops of a first one of the branches and based on outputs of the series of flip-flops of a second one of the branches.

[0014] In an embodiment, the third circuit includes a second logic block configured to perform an AND function based on outputs of the series of flip-flops of the second branch and based on outputs of the series of flip-flops of a third one of the branches.

[0015] In an embodiment, the third circuit is configured to generate a pulse on the first path when the states of the outputs of the first branch and the second branch are the same as a high logic state.

[0016] In an embodiment, the third circuit is configured to generate a pulse on the second path when the states of the outputs of the second branch and the third branch are the same as a high logic state.

[0017] In an embodiment, a pulse is generated when the state of the signal at the output of the second branch is a high state.

[0018] In an embodiment, the fourth circuit is configured to generate a control signal enabling modification of the amplitude of the first signal depending on the presence or absence of pulses on the first path and the second path.

[0019] In an embodiment, each third signal is generated by a comparator having a corresponding voltage of a trigger threshold, which has two thresholds as trigger thresholds.

[0020] In an embodiment, each voltage comparator is of the Schmitt trigger type.

[0021] In an embodiment, each voltage comparator has an input node coupled via a respective capacitive element to a first node intended to receive the signal to be analyzed, each input node of each comparator being intended to receive respectively one of the second signals.

[0022] In an embodiment, the first circuit comprises resistors connected in series between a power supply node intended to receive a power supply voltage and ground, and each of the second signals is generated based on voltages present at different nodes corresponding to junctions of two adjacent resistors in the series of resistors.

[0023] In an embodiment, the first circuit includes a PMOS transistor and an NMOS transistor, each having a conduction node connected to a reference node, control nodes of the PMOS transistor and the NMOS transistor are connected to the reference node, another conduction node of the PMOS transistor is connected to a power supply node, and another conduction node of the NMOS transistor is connected to ground.

[0024] In an embodiment, the reference node is coupled to ground via one of the series resistors.

[0025] In an embodiment, each comparator includes a dual inverter circuit coupled to a power supply node and ground, the dual inverter circuit including two PMOS transistors and two NMOS transistors connected in series; a control node common to the PMOS and NMOS transistors of the dual inverter is coupled to a reference node.

[0026] In an embodiment, the first signal is derived from a crystal oscillator.

[0027] An embodiment provides an NFC microcontroller comprising a circuit such as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above features and advantages and others will be described in detail in the remainder of the disclosure of specific embodiments which are given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0029] Figure 1 An example of an electronic circuit of the type to which the described embodiments apply is illustrated very schematically in block form;

[0030] Figure 2 According to the example Figure 1 The circuit of the block;

[0031] Figure 3 Shows Figure 2 The operation curve of the circuit;

[0032] Figure 4 Very schematically shows a Figure 1 The circuit of the block;

[0033] Figure 5 It shows that according to the embodiment Figure 4 Circuit;

[0034] Figure 6 It shows that according to the embodiment Figure 4 Circuit;

[0035] Figure 7 It shows that according to the embodiment Figure 4 Circuit;

[0036] Figure 8 Shows Figure 4 A timing diagram of the operation of the circuit; and

[0037] Fig. 9 Shows Figure 4 A timing diagram of the operation of the circuit. DETAILED DESCRIPTION

[0038] In the various drawings, similar features have been designated by similar reference numerals. In particular, common structural and / or functional features between the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0039] For clarity, only the steps and elements useful for understanding the described embodiments have been illustrated and described in detail.

[0040] Unless otherwise indicated, when reference is made to two elements being connected together, this means a direct connection without any intervening elements other than conductors, and when reference is made to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0041] In the following description, when reference is made to terms that qualify an absolute position (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or a relative position (such as terms "above", "below", "upper", "lower", etc.) or terms that qualify a direction (such as terms "horizontal", "vertical", etc.), unless otherwise specified, it refers to the orientation in the drawing.

[0042] Unless otherwise specified, the expressions "about", "approximately", "substantially" and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0043] Figure 1 An example of an electronic device 100 of the type to which the described embodiments apply is shown very schematically in block form.

[0044] The device 100 , which is for example a microcontroller, for example integrates a processing unit 104 (CTRL) comprising for example one or more processors under the control of instructions stored in an instruction memory (not shown).

[0045] The device 100 also includes a module 106 (REF) having a periodic signal generation block, which includes one or more oscillators. The generated signal is used to generate a reference signal, such as a clock signal, for example. Block 106 includes, for example, one or more crystal oscillators (XO) or voltage controlled oscillators (VCO). For example, block 106 includes a circuit for measuring the envelope of the generated periodic signal to verify the amplitude of the generated signal and, if necessary, apply feedback to the generated signal to keep it within a desired amplitude range.

[0046] The device 100 may also integrate an antenna circuit 110 (antenna), which includes, for example, an antenna and an impedance matching circuit. The device 100 is, for example, compatible with the near field communication protocol NFC.

[0047] The device 100 may be integrated with Figure 1 Block 102 (FCT) in the MCU represents other circuits (eg, one or more volatile and / or non-volatile memories, other processing units, input / output interfaces I / O) for implementing other functions.

[0048] Blocks 102, 104, 106, and 110 are coupled together and / or to the rest of device 100, for example, via a bus 108 that communicates the necessary signals.

[0049] The present disclosure more particularly relates to module 106 having a periodic signal generated therein that is used, for example, in processes implemented by other blocks 102 , 104 , and 110 .

[0050] Figure 2 According to the example Figure 1 More specifically, Figure 2 A circuit 206 is shown which is configured to measure the envelope of a signal Vxo generated by one of the oscillators of block 106 .

[0051] The illustrated circuit 206 comprises a diode D coupled to ground via a parallel associated capacitive element C and a resistor R. A voltage Vxo_out corresponding to the oscillation amplitude of the signal Vxo is measured between the cathode of the diode D and ground.

[0052] Figure 3 Shows Figure 2 More specifically, Figure 3The voltage Vxo_out is illustrated. At each oscillation of the signal Vxo, the capacitive element C is charged in the rising part and then slowly discharged in the falling part when the diode is no longer conducting until the next rising part of the oscillation, which provides a rectified voltage with residual periodic variation (ripple). The voltage Vxo_out is then estimated more accurately with the aid of one or more differential comparators (not shown in this document), one of the inputs of which will be a comparison DC voltage level to provide a stable result, even with ripple. In this example, as many comparators as the DC voltage levels to be compared should be implemented.

[0053] As circuits become smaller, the chip surface area necessary to implement the components of circuit 206 and the differential comparator must decrease.

[0054] For this purpose, the described embodiments provide an electronic circuit comprising: a first circuit configured to generate a plurality of second signals having offset DC voltage levels based on a first periodic analog signal; a second circuit configured to generate a third periodic digital signal based on the second signals crossing at least one threshold; and a third circuit configured to determine an amplitude range in which the first signal is located based on the number of third signals present.

[0055] This enables a simplification of the design and a reduction of the necessary chip surface area by more than a factor of two.

[0056] Figure 4 A very schematic diagram of a Figure 1 The circuit of the block.

[0057] More specifically, Figure 4 An embodiment of an electronic circuit 400 of block 106 is illustrated.

[0058] The circuit 400 includes a first circuit 410 configured to generate a plurality of second signals Vhigh, Vlow and Vref having offset voltage levels at nodes N2, N3 and N4, respectively, based on a first periodic analog signal Vxo emitted by an oscillator 404 (XO) of the block 106.

[0059] In the example shown, the circuit 410 includes three capacitive elements 401 , 403 , 405 , which respectively couple nodes N2 , N3 , and N4 to a node N1 , to which the signal Vxo arrives.

[0060] Circuit 410 includes a resistor 407 that couples node N2 and node N2a via a first optional switch 415. Resistor 407 also optionally couples node N2 and node N2b via a second switch 413. The control signal sel_vhigh for the first and second switches is inverted between the two switches. The use of optional switches 413 and 415 enables the start of feedback on the oscillator implemented by circuit 440 to be regulated based on a threshold different from the final target voltage.

[0061] The circuit 410 further includes a resistor 409 coupling the node N3 and the node N3 a and a resistor 411 coupling the node N4 and the node N4 a .

[0062] In the example shown, nodes N2a, N2b, N3a and N4a are coupled to circuit 412, which is configured to generate voltages offset relative to each other. Capacitive elements 401, 403, 405 enable cutting off the DC voltage level of the oscillating signal Vxo, and resistors 407, 409 and 411 enable applying a corresponding offset of the voltage present on nodes N2a, N2b, N3a and N4a to the signal Vxo that does not include a DC voltage. Therefore, voltages Vhigh, Vlow and Vref are images of signal Vxo with offset voltages, which are the same as the voltages present on nodes N2a or N2b, N3a and N4a.

[0063] In the example shown, the circuit 400 also includes a second circuit 420, which is configured to generate a third periodic digital signal Vouthigh, Voutlow and Voutref according to the second signal Vhigh, Vlow and Vref crossing at least one threshold value (preferably, two threshold values). The circuit 420 includes an input coupled to the node N2, an input coupled to the node N3 and another input coupled to the node N4. The circuit 420 includes: a first voltage comparator 421, which couples the node N2 to the first input of the third circuit 430; a second voltage comparator 422, which couples the node N3 to the second input of the circuit 430; and a third voltage comparator 423, which couples the node N4 to the third input of the circuit 430. In the example, each of the voltage comparators has two trigger thresholds Vhyst_l, Vhyst_h, and is, for example, of the Schmitt trigger type. In operation, each third signal is generated independently of the other signals from the moment when the corresponding second signal crosses the two threshold values ​​Vhyst_l, Vhyst_h. Each of the third signals Vouthigh, Voutlow, and Voutref is a periodic square pulse signal alternating between a high state and a low state, thus forming a digital signal having a different duty cycle.

[0064] In the example shown, the circuit 400 includes a third circuit 430 configured to determine the amplitude range in which the first signal Vxo is located according to the number of third signals present.

[0065] In an example, circuit 430 is configured to be coupled to a reference signal ( ca l c lk) synchronously verifies which of the third signals exists. Therefore, when the third signal Voutlow is in step with the signal cal c When the third signal Vouthigh is periodically established at the same frequency as the frequency of the signal cal clk in the high state, a pulse is generated on the first path (state low). Similarly, when the third signal Vouthigh is periodically established at the same frequency as the frequency of the signal cal clk in the high state, a pulse is generated on the second path (state high).

[0066] If only the third signal Voutref is periodically generated without periodically generating the third signals Voutlow and Vouthigh, this means that the amplitude of the signal Vxo is within a first amplitude range lower than 2*(Vlow-Vref)+Vhyst_1. In another example, if only the third signals Voutref and Voutlow are periodically generated without periodically generating the third signal Vouthigh, this means that the amplitude of the signal Vxo is within a second amplitude range between 2*(Vhigh-Vref)+Vhyst_1 and 2*(Vlow-Vref)+Vhyst_1. In another example, if the third signals Vouthigh, Voutref, and Voutlow are periodically generated, this means that the amplitude of the signal Vxo is within a third amplitude range higher than 2*(Vhigh-Vref)+Vhyst_1.

[0067] In the example shown, the circuit 400 includes a fourth circuit 440 configured to enable adjustment of the amplitude of the signal Vxo according to the determination of the amplitude range of the signal Vxo.

[0068] The fourth circuit receives as input the first path and the second path and the signal cal clk. At its output, it is coupled to, preferably connected to, the oscillator 404. In the example, the fourth circuit 440 generates a control signal that enables the amplitude of the signal Vxo to be modified synchronously with the signal cal clk according to the presence or absence of a pulse on the first path and the second path (respectively, state low, state high). In the example, if a pulse is simultaneously present on cal clk, on the first path (state low) and on the second path (state high), this means that the amplitude of the signal Vxo is within the third amplitude range, and the oscillator power supply control signal should be reduced, for example, to reduce the oscillation amplitude. If a pulse is simultaneously present on cal clk and on the first path (state low) but not on the second path (state high), this means that the amplitude of the signal Vxo is within the second amplitude range and the supply current of the oscillator does not have to be modified. If the pulse is present on cal clk but not on the first path (state low) or the second path (state high), this means that the amplitude of signal Vxo is within the first amplitude range and feedback should be applied to the oscillator, for example by increasing the bias current of oscillator 404.

[0069] In an example, to improve the robustness of the circuit 106 and, for example, to eliminate the possibility of parasitic pulses on the third signal, the presence of the third signal may be checked within a time range of multiple consecutive cycles of the signal Voutref.

[0070] The chip surface area required to implement circuit 400 is smaller than that required for example Figure 2 The surface area of ​​the envelope detector shown in is at least twice smaller.

[0071] Figure 5 It shows that according to the embodiment Figure 4 More specifically, Figure 5 An embodiment of a circuit 430 is illustrated.

[0072] In the example shown, the circuit 430 includes a first branch 512 having, for example, four flip-flops 536 in series, whose clock inputs are coupled together and coupled to a node NVouthigh configured to receive a third signal Vouthigh. The term "flip-flops in series" means that the input of one of the flip-flops is coupled to the output of the previous flip-flop. The last flip-flop in the series of flip-flops 536 is coupled to, preferably connected to, a node N5.

[0073] The circuit 430 comprises, for example, a second branch 514 having, for example, four flip-flops 534 connected in series, whose clock inputs are coupled together and to a node NVoutref configured to receive a third signal Voutref. The last flip-flop in the series 534 of flip-flops is coupled to, preferably connected to, a node N6.

[0074] In the example, the second branch 514 also includes two other flip-flops 547, 548 connected in series with the series of flip-flops 534, whose clock inputs are coupled together and to the node NVoutref. The data input of the flip-flop 548 is connected to the node N6, for example. The signal at the output of the flip-flop 548 is, for example, the signal cal clk.

[0075] Circuit 430 includes, for example, a third branch 516 having, for example, four flip-flops 532 connected in series, their clock inputs coupled together and coupled to a node NVoutlow configured to receive signal Voutlow. The last flip-flop in the series of flip-flops 532 is coupled to, preferably connected to, node N7.

[0076] In the example shown, in each of branches 512 , 514 , and 516 , the number of flip-flops connected in series must be the same for groups 532 , 534 , and 536 .

[0077] In the example, the reset inputs of the series of flip-flops in the same branch are connected together.

[0078] In another example, the inverter 522 is connected in series with the data input of the first flip-flop in the series 534 of flip-flops in the second branch 514, for example. In this case, the data inputs of the first flip-flops in the series 532 and 536 are coupled to a high logic level together, and the reset inputs of the flip-flops in the series 532 and 536 are also coupled to the input of the inverter 522.

[0079] In the example shown, circuit 430 also includes a first logic function formed by a NAND logic gate 542 connected in series with an inverter 543 and a second logic function formed by a NAND logic gate 544 connected in series with an inverter 545. The association of circuits 542 and 543 forms an AND function based on signals present on nodes N5 and N6. The association of circuits 544 and 545 is configured to perform an AND function based on signals present on nodes N6 and N7. Those skilled in the art will be able to implement other logic gates in addition to the NAND gate in series with the inverter to obtain the AND logic function. The generated signals will be defined on nodes NVoutref and NVoutlow, respectively, and on NVoutref and NVouthigh while synchronizing the signals.

[0080] In the example shown, circuit 430 also includes flip-flops 546, 551, and 552. Flip-flop 552 has its clock input coupled to the output of the logic function formed by logic gates 542, 543 and has its output coupled to node N12. Flip-flop 551 has its data input coupled to the output of the logic function provided by the association of circuits 544 and 545 and has its clock input coupled to node N6. A signal state low may be found at the output of flip-flop 551. Flip-flop 546 has its clock input coupled to node N6. A signal state high may be found at the output of flip-flop 546.

[0081] In the example shown, circuit 430 also includes a frequency divider circuit 530 that couples node NVoutref to node N9. Circuit 530 is composed of flip-flops connected together so that the output of one flip-flop is connected to the clock input of the next flip-flop. This enables the frequency division of the signal present at the clock input of the first flip-flop whenever there is a flip-flop in circuit 530. In the example shown, circuit 530 includes twelve flip-flops, and the frequency present at the input of the first flip-flop (on the left) of circuit 530 is divided by 2^12. Circuit 530 enables the period between each pulse of signal cal clk to be defined.

[0082] In the example shown, circuit 430 also includes circuit 526 configured to generate a time window. Circuit 526 includes a flip-flop 550 having its clock input coupled to node N9 and its data input connected to a high logic level. The output of flip-flop 550 is coupled to one or more (e.g., three) time shift units associated in series 540. The output of the last time shift unit is coupled to the reset input of flip-flop 550 via inverter 549. The output of flip-flop 550 is coupled to the reset inputs of flip-flops 546, 547, 548, and 551.

[0083] In the example, Figure 5 The flip-flop of circuit 430 is of D type.

[0084] In operation, circuit 526 defines the length of time of the window for observing the result of the presence of simultaneous and synchronous signals on NVoutref and NVoutlow and on NVoutref and NVouthigh. In other words, at each calibration period, circuit 526 defines the generation of pulse state high, state low, and cal clk within the duration t of the pulse, during which the pulse is also transmitted on signal cal clk.

[0085] In operation, circuit 526 defines the signals state high, state low, and reset of cal clk to zero after a time window defined by circuit 526 via inverter 549 .

[0086] The reset of the flip-flops of series 536 and 532 is provided by the result of branch 534. This allows a continuous frequency control, which will be performed once every four rising edges of signal Voutref due to inverter 522, but whose result will be verified at each calibration period, of duration t.

[0087] Figure 6 It shows that according to the embodiment Figure 4 More specifically, Figure 6 Picture shows Figure 4 One of the voltage comparators 421, 422 or 423.

[0088] In the example shown, one of the voltage comparators 421, 422, 423 is depicted. The other voltage comparators 421, 422, 423 are, for example, similar, with their size and architecture being as close to each other as possible.

[0089] exist Figure 6 , the illustrated voltage comparator includes a dual inverter circuit coupling a power supply node N8 (VDD) and a ground (GND). The dual inverter circuit includes two PMOS transistors 610, 612 and two NMOS transistors 614, 616 connected in series. The PMOS and NMOS transistors of the dual inverter include a common control node connected to an input node N2, N3 or N4 of the corresponding comparator.

[0090] In the example shown, the voltage comparator also includes a PMOS transistor 620, which has: a conduction node coupled to, preferably connected to, a power supply node N8; a control node coupled to, preferably connected to corresponding nodes NVouthigh, NVoutlow, NVoutref; and another conduction node coupled to, preferably connected to a conduction node common to transistors 610 and 612.

[0091] The illustrated voltage comparator also includes an NMOS transistor 618 having: a conduction node coupled to, preferably connected to ground; a control node coupled to, preferably connected to respective nodes NVouthigh, NVoutlow, NVoutref; and another conduction node coupled to, preferably connected to a conduction node common to transistors 614 and 616.

[0092] In the example shown, the voltage comparator also includes a PMOS transistor 622 and an NMOS transistor 624, which have a conduction node common to the two transistors 622, 624 coupled to, preferably connected to, the respective nodes NVouthigh, NVoutlow, NVoutref. Another conduction node of transistor 622 is coupled to, preferably connected to node N8, and another conduction node of transistor 624 is coupled to, preferably connected to ground. The control nodes of transistors 622, 624 are coupled together and coupled to a conduction node common to transistors 612 and 614.

[0093] In the example shown, the substrate nodes of transistors 610, 612, and 620 are coupled together and connected to VDD. The substrate nodes of transistors 614, 616, and 618 are coupled to ground.

[0094] In an example, the transistors of the voltage comparators 421, 422, 423 have sizes and architectures as similar as possible to each other. In particular, the transistors 610, 620; 612, 614; and 616, 618 preferably have sizes and architectures as similar as possible from one comparator to another.

[0095] Figure 7 It shows that according to the embodiment Figure 4 More specifically, Figure 7 An example of circuit 412 is illustrated.

[0096] In the example shown, the circuit 412 includes some (ten) resistors connected in series between a power supply node and ground, which power supply node may be a node N8, configured to be connected to a power supply rail of a voltage VDD. Node N2a corresponds to the junction between the fourth resistor 719 and the fifth resistor 718 connected in series. Node N2b corresponds to the junction between the fifth resistor 718 and the sixth resistor 717 connected in series. Node N3a corresponds to the junction between the eighth resistor 721 and the ninth resistor 722 connected in series. Node N4a corresponds to the junction between the ninth resistor 722 and the tenth resistor 723 connected in series. The obtained resistance ladder enables the formation of different voltage levels at nodes N2a, N2b, N3a, and N4a.

[0097] In the example shown, circuit 412 also includes a circuit including a PMOS transistor 725 and an NMOS transistor 726. Transistor 725 has a conduction node connected to power supply node N8, another conduction node connected to node N4a, a substrate node connected to node N8, and a control node connected to node N4a. Transistor 726 has a conduction node connected to node N4a, another conduction node connected to ground, a substrate node connected to ground, and a control node connected to node N4a.

[0098] By shorting the conduction nodes of transistors 726 and 725 corresponding to the drains of these transistors to their control nodes, this positions the voltage present on node N4a to be intermediate the thresholds Vhyst_h and Vhyst_1. Figure 6 This enables a duty cycle very close to 50% to be obtained at the output of comparator 423 if the size and architecture of the corresponding transistors 612 and 614 of the comparator are similar. This voltage at node N4a is applied to the resistor ladder and enables the voltage present on nodes N3a, N2a and N2b to be defined according to the positioning of nodes N3a, N2a and N2b on the resistor ladder. Nodes N3a, N2b and N2a can be placed at other points of the resistor ladder according to the voltage level to be used as a comparison reference.

[0099] Figure 8 Shows Figure 4 More specifically, Figure 8 The voltages Vhigh, Vlow and Vref relative to thresholds Vhyst_1 and Vhyst_h are illustrated as a function of time.

[0100] Prior to time t1 , signal Vref is centered at 0.6V, for example, and Vhyst_1 and Vhyst_h are located on either side of 0.6V.

[0101] At time t1, only the signal Vref generates a signal at the output of one of the voltage comparators. For example, if a voltage comparator such as Figure 7 4. If the circuit 412 is shown in FIG. 4, the signal has a duty cycle of 50%. Neither the signals Vhigh nor Vlow cross the two thresholds Vhyst_1 and Vhyst_h.

[0102] Between time t1 and the subsequent time t2, the amplitude of the signal Vxo from the oscillator increases until the signal Vlow crosses the threshold Vhyst_1. Then, the corresponding voltage comparator 422 generates a square wave signal Voutlow. Thus, the amplitude of the signal Vxo is greater than 2*(Vlow-Vref)+Vhyst_1. When the signal Voutlow has the same frequency as the signal Voutref, the amplitude of the signal Vxo is confirmed to exceed Vlow.

[0103] At time t3, Vhigh has crossed the thresholds Vhyst_h and Vhyst_l, which means that the amplitude Vxo becomes greater than 2*(Vhigh-Vref)+Vhyst_l. Then, if it is desired to adjust the amplitude of Vxo between 2*(Vlow-Vref)+Vhyst_l and 2*(Vhigh-Vref)+Vhyst_l, it becomes necessary to reduce, for example, the supply current of the oscillator.

[0104] Fig. 9 Shows Figure 4 More specifically, Fig. 9 The signals state high, state low, and pulses on cal clk are illustrated as a function of time.

[0105] The signal cal clk is a reference signal, whose pulses appear periodically at times t4, t5, t6, t7 and t8 with a period Tcal defined by the circuit 530. In the example, for an oscillator frequency of 54.24 MHz, Tcal is 75 μs.

[0106] In example with Figure 8 At time t4 corresponding to time t1, there is no pulse on the signal state low and state high.

[0107] In example with Figure 8 At time t5 corresponding to time t2 of Vxo, there is a pulse at signal state low. This means that the amplitude of Vxo is between 2*(Vlow-Vref)+Vhyst_1 and 2*(Vhigh-Vref)+Vhyst_1, and for example, the oscillator supply current does not have to be adjusted.

[0108] In example with Figure 8 At time t6 corresponding to time t3, there are pulses on the signal state low and state high. Therefore, the amplitude of Vxo is greater than 2*(Vhigh-Vref)+Vhyst_1. If it is desired to adjust the amplitude of Vxo between 2*(Vlow-Vref)+Vhyst_1 and 2*(Vhigh-Vref)+Vhyst_1, the oscillator supply current can be reduced by, for example, a factor of 2.

[0109] At time t7, there are still pulses on the signal state low and state high. Therefore, the amplitude of Vxo is still greater than 2*(Vhigh-Vref)+Vhyst_1. If it is desired to adjust the amplitude of Vxo between 2*(Vlow-Vref)+Vhyst_1 and 2*(Vhigh-Vref)+Vhyst_1, then at this time, for example, the power supply current of the oscillator can be reduced by 4 times relative to the current at time t5.

[0110] At time t8, there are still pulses on the signal state low and state high. Therefore, the amplitude of Vxo is still greater than 2*(Vhigh-Vref)+Vhyst_1. If it is desired to adjust the amplitude of Vxo between 2*(Vlow-Vref)+Vhyst_1 and 2*(Vhigh-Vref)+Vhyst_1, then at this time, for example, the supply current of the oscillator can be reduced by 8 times relative to the current at time t5. Repeat the same operation until the amplitude of Vxo returns to between 2*(Vlow-Vref)+Vhyst_1 and 2*(Vhigh-Vref)+Vhyst_1, that is, there are no further pulses on state high.

[0111] Modulating the strength of the oscillator supply current dichotomously enables the amplitude of Vxo to converge smoothly towards the desired voltage range. Other types of feedback are possible.

[0112] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, the number of flip-flops connected in series in the first branch 512, the second branch 514, and the third branch 516 of the circuit 430 is, for example, between zero and more than four. The more flip-flops there are in these branches, the greater the robustness against parasitic pulses.

[0113] Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, with regard to the generation of the voltages Vhigh, Vlow and Vref, a person skilled in the art can implement their knowledge to deliver a signal with an offset voltage based on the signal Vxo. Even if Figure 7 The embodiment enables generation of a signal Voutref having an almost just-right 50% duty cycle. It is also within the capabilities of a person skilled in the art to generate Vref in other ways such that it is not necessary to generate Vref to provide a signal Voutref having a 50% duty cycle at the output of the comparator 423.

[0114] Circuit 440 is not described in detail, but those skilled in the art will be able to implement their knowledge to form a circuit capable of verifying whether pulses are present simultaneously on cal clk, state low and state high, and thus modulating the parameters of the oscillator to modify its amplitude. Those skilled in the art will be able to implement their knowledge to perform feedback control of the oscillation amplitude acting on oscillator 404. In an example, those skilled in the art can implement oscillator 404 in a Colpitts topology using a negative resistor called Rneg that is proportional to the current. Therefore, current control causes the negative resistance to vary. However, the negative resistance Rneg of a Colpitts-type component can also be varied by varying the capacitance value. Those skilled in the art can implement other types of components for control feedback of oscillators, such as voltage-controlled components.

Claims

1. An electronic circuit comprising: a first circuit configured to generate a plurality of second signals based on a first periodic analog signal, the plurality of second signals having voltage levels offset from one another; a second circuit configured to generate a third periodic digital signal based on respective crossings of at least one threshold by the second signal; as well as The third circuit is configured to determine the amplitude range of the first periodic analog signal according to the number of the third periodic digital signal. 2 . The electronic circuit of claim 1 , wherein the second circuit is configured to generate each third periodic digital signal in response to a corresponding one of the second signals crossing two thresholds. 3 . The electronic circuit according to claim 1 , wherein the electronic circuit comprises a fourth circuit configured to adjust the amplitude of the first periodic analog signal according to the determined amplitude range.

4. The electronic circuit according to claim 3, wherein the third circuit comprises three branches, wherein each branch comprises a plurality of flip-flops connected in series, and wherein each branch is configured to receive a corresponding one of the third periodic digital signals at a clock input of the flip-flops of the corresponding branch, respectively.

5. The electronic circuit of claim 4, wherein each branch comprises at least two D-type flip-flops in a series of flip-flops.

6. The electronic circuit of claim 5 , wherein the third circuit comprises a first logic block configured to perform an AND function based on an output of the series of flip-flops of a first one of the branches and based on an output of the series of flip-flops of a second one of the branches.

7. The electronic circuit of claim 6, wherein the third circuit comprises a second logic block configured to perform an AND function based on the output of the series of flip-flops of the second branch and based on the output of the series of flip-flops of a third one of the branches. 8 . The electronic circuit of claim 7 , wherein the third circuit is configured to generate a first pulse on a first path in response to the outputs of the first branch and the second branch having a high logic state.

9. The electronic circuit of claim 8, wherein the third circuit is configured to generate a second pulse on a second path in response to the output of the second branch and the output of the third branch having a high logic state.

10. The electronic circuit of claim 6, wherein the third circuit is configured to generate pulses on the first path and the second path in response to the signal at the output of the second branch having a high logic state.

11. The electronic circuit of claim 10, wherein the fourth circuit is configured to generate a control signal that modifies an amplitude of the first periodic analog signal depending on the presence or absence of the pulses on the first path and the second path. 12 . The electronic circuit according to claim 2 , wherein each of the third periodic digital signals is generated by a corresponding voltage comparator having the two thresholds as trigger thresholds.

13. An electronic circuit as claimed in claim 12, wherein each voltage comparator is of the Schmitt trigger type.

14. The electronic circuit of claim 12 , wherein each voltage comparator has an input node coupled to a first node via a respective capacitive element, the first node being configured to receive the first periodic analog signal, and wherein each input node of each comparator is configured to receive one of the second signals, respectively.

15. The electronic circuit of claim 14 , wherein the first circuit comprises a resistor connected in series between a power supply node and ground, the power supply node being configured to receive a power supply voltage, and each of the second signals being generated based on a voltage present at a different node corresponding to a junction of two adjacent resistors in the series of resistors.

16. The electronic circuit of claim 15 , wherein the first circuit comprises a p-channel metal oxide semiconductor (PMOS) transistor and an n-channel metal oxide semiconductor (NMOS) transistor, each having a conduction node connected to a reference node, control nodes of the PMOS transistor and the NMOS transistor being connected to the reference node, another conduction node of the PMOS transistor being connected to the power supply node, and another conduction node of the NMOS transistor being connected to the ground.

17. The electronic circuit of claim 16, wherein the reference node is coupled to the ground via one of the series connected resistors.

18. The electronic circuit of claim 17, wherein each comparator comprises a dual inverter circuit coupling the power supply node and the ground; The dual inverter circuit includes two PMOS transistors and two NMOS transistors connected in series; and A control node common to the PMOS transistor and the NMOS transistor of the dual inverter circuit is coupled to the reference node.

19. The electronic circuit of claim 1, wherein the first periodic analog signal is derived from a crystal oscillator.

20. A near field communication (NFC) microcontroller, comprising: processor; as well as an electronic circuit, communicatively coupled to the processor, comprising: a first circuit configured to generate a plurality of second signals based on a first periodic analog signal, the plurality of second signals having voltage levels offset from one another; a second circuit configured to generate a third periodic digital signal in response to respective crossings of at least one threshold by the second signal; and The third circuit is configured to determine the amplitude range of the first periodic analog signal according to the number of the third periodic digital signal.

21. A method of operating an electronic circuit, the method comprising: generating, with a first circuit of the electronic circuit, a plurality of second signals based on the first periodic analog signal, the plurality of second signals having voltage levels that are offset from one another; generating, with a second circuit of the electronic circuit, a third periodic digital signal in response to a corresponding crossing of at least one threshold by the second signal; as well as The third circuit of the electronic circuit is used to determine the amplitude range of the first periodic analog signal according to the quantity of the third periodic digital signal.

22. The method of claim 21, further comprising generating, by the second circuit, each third periodic digital signal in response to a corresponding one of the second signals crossing two thresholds.

23. The method of claim 21, further comprising adjusting, by a fourth circuit of the electronic circuit, an amplitude of the first periodic analog signal according to the determined amplitude range.

24. The method of claim 21, wherein the third circuit comprises three branches, each branch comprising a plurality of flip-flops in a series of flip-flops, and the method further comprises: A respective one of the third periodic digital signals is received by each branch at a clock input of a flip-flop of the respective branch.

25. The method of claim 24, wherein each branch comprises at least two D-type flip-flops connected in series, and the method further comprises: An AND function is performed by a first logic block of the third circuit based on outputs of the series of flip-flops of a first one of the branches and based on outputs of the series of flip-flops of a second one of the branches.

26. The method of claim 22, further comprising generating a respective one of the third periodic digital signals by a respective voltage comparator having the two thresholds as trigger thresholds.

27. The method of claim 21, further comprising receiving the first periodic analog signal from a crystal oscillator.

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