Multi-phase clock generation circuit and multi-phase clock calibration circuit

Abstract

According to an embodiment of the present disclosure, a multi-phase clock generation circuit and a multi-phase clock calibration circuit are provided. The multi-phase clock generation circuit includes a multi-phase clock generation circuit; a multi-phase clock error detection circuit, including a first set of DC component extraction modules, a phase difference detection circuit, a second set of DC component extraction modules, a multiplexing module, and a comparison module, wherein the multi-phase clock signals are input to the comparison module via the first set of DC component extraction modules and the multiplexing module, and the multi-phase clock signals are input to the comparison module via the phase difference detection circuit, the second DC component extraction module, and the multiplexing module, and the comparison module outputs a detected error; a digital control circuit that assigns a selection module number to each sub-module in the multiplexing module; a multi-phase clock adjustment circuit that includes a duty cycle adjustment circuit and a phase adjustment circuit. The embodiments of the present disclosure can effectively reduce the calibration process of the chip, simplify the chip design, and reduce costs.

Description

Technical Field

[0001] The present disclosure relates to a clock generation circuit, and in particular to a multi-phase clock generation circuit and a multi-phase clock calibration circuit. Background Art

[0002] As data centers continue to demand high-speed communications, serial interface communication speed requirements are also increasing. However, traditional analog receivers are struggling to meet these high-speed communication requirements. In recent years, new receivers based on high-speed time-interleaved analog-to-digital converters (TIADCs) have gradually become mainstream.

[0003] High-speed time-interleaved analog-to-digital converters (ADCs) achieve efficient data conversion by using multiple clocks to sample the same analog signal in parallel. However, phase errors between these multi-phase clocks can significantly impact the signal-to-noise-distortion ratio (SNR). This error degrades ADC performance, further impacting the receiver's bit error rate (BER), becoming a significant factor limiting the reliability of high-speed communications.

[0004] Prior art already utilizes a delay-locked loop (DLL) to generate an eight-phase clock. However, precise delay calibration is required during the DLL's locking process; otherwise, the locking delay can easily become an integer multiple of the clock period, rather than the clock period itself. After DLL calibration, further calibration of the clock's duty cycle and phase deviation is required to ensure clock signal stability and accuracy. However, this approach complicates the overall chip structure and makes the calibration process lengthy. Summary of the Invention

[0005] In order to solve the problems existing in the prior art, embodiments of the present disclosure provide a multi-phase clock generation circuit and a multi-phase clock calibration circuit.

[0006] According to a first aspect, embodiments of the present disclosure provide a multi-phase clock generation circuit, which includes a multi-phase clock generation circuit that generates a multi-phase clock signal through a plurality of serially connected registers; a multi-phase clock error detection circuit, which includes a first set of DC component extraction modules, a phase difference detection circuit, a second set of DC component extraction modules, a multiplexing module, and a comparison module, wherein the multi-phase clock signal is input to the comparison module via the first set of DC component extraction modules and the multiplexing module or via the multiplexing module and the first set of DC component extraction modules, the multi-phase clock signal is input to the comparison module via the phase difference detection circuit, the second DC component extraction module, and the multiplexing module or via the phase difference detection circuit, the multiplexing module, and the second DC component extraction module, and the comparison module outputs a detected error; a digital control circuit that assigns a selection module number to each sub-module in the multiplexing module and associates the number with each detected error; a multi-phase clock adjustment circuit, which includes a duty cycle adjustment circuit and a phase adjustment circuit, and the multi-phase clock adjustment circuit adjusts the duty cycle or phase of one or more clock signals according to the output of the digital control circuit.

[0007] In embodiments of the present disclosure, the positions of the multiplexing module and the DC component extraction module can be interchanged. The multiplexing module can be placed after the DC component extraction module to select and output a detected value of a clock signal detection, such as a duty cycle or a phase difference value, or can be placed before the DC component extraction module, and the result is the same for the comparison module. Each sub-module in the multiplexing module inputs a set of duty cycle detection values or a set of phase difference detection values to the comparison module. The multi-phase clock adjustment circuit finely adjusts the duty cycle and phase, and the adjustment range can be at the picosecond level.

[0008] The multi-phase clock generation circuit provided in the embodiments of the present disclosure has a simple structure, does not need to be implemented using a delay-locked loop, avoids complex calibration processes, and simplifies chip design.

[0009] Optionally, the multi-phase clock signal is input to the comparison module via the first set of DC component extraction modules and the multiplexing module or via the multiplexing module and the first set of DC component extraction modules, for detecting the duty cycle error between each pair of clock signals with opposite phases in the multi-phase clock signal. The duty cycle information can be extracted by measuring the DC component of the signal, and the DC component extraction module can be implemented using a low-pass filter, thereby making the duty cycle detection circuit have a simple structure.

[0010] Optionally, the phase difference detection circuit detects the phase difference of at least two groups of clock signals, and the second DC component extraction module extracts the DC component of the phase difference of the two groups of clock signals.

[0011] Optionally, the phase difference detection circuit includes an exclusive - OR logic circuit. The phase difference detection circuit performs exclusive - OR operations on the following four groups of clock signals: the clock signals with phases of 0 degrees and 90 degrees, the clock signals with phases of 0 degrees and 270 degrees, the clock signals with phases of 180 degrees and 270 degrees, and the clock signals with phases of 90 degrees and 180 degrees, to obtain corresponding first to fourth phase difference signals. The second DC component extraction module extracts the DC component from the signal obtained by superimposing the first and third phase difference signals, and extracts the DC component from the signal obtained by superimposing the second and fourth phase difference signals. The phase difference detection circuit only needs to use a logic circuit and a DC component extraction module, with a simple structure, which simplifies the design. Performing phase difference detection on the four groups of clocks and then superimposing the processed results can keep the loads of each clock signal balanced and avoid affecting the clock signals during the detection process.

[0012] Optionally, the multi - phase clock generation circuit according to the first aspect of the present disclosure further includes a multi - phase clock duty - cycle adjustment circuit, which includes a logic circuit and a delay circuit. It receives the output of the multi - phase clock generation circuit, and uses the logic circuit to perform a logic operation on each clock signal and another clock signal in the multi - phase clock signals delayed by the delay circuit as a group of signals, to obtain multi - phase clock signals with a predetermined duty - cycle, where the delay value of the delay circuit is determined according to the predetermined duty - cycle. When the duty - cycle of the clock signal output by the multi - phase clock generation circuit has a large gap from the required duty - cycle, the duty - cycle can be adjusted by the duty - cycle adjustment circuit. The above - mentioned duty - cycle adjustment method realizes the adjustment of the duty - cycle by performing a logic operation on the clock signal and the other - phase clock after delay.

[0013] Optionally, the phase adjustment circuit includes at least one group of connected inverters and variable capacitors. Each phase adjustment circuit is used to adjust the phase of a clock signal. When the digital control circuit determines that it is necessary to adjust the phase of one or more clock signals according to the selection module number and the detection error, it sends a control signal to the phase adjustment circuit corresponding to the one or more clock signals to adjust the capacitance value of the corresponding variable capacitor. This circuit has a simple structure and can obtain a relatively high - precision adjustment result without a complex adjustment process.

[0014] Optionally, the duty - cycle adjustment circuit includes a variable number of connected PMOSs and a variable number of connected NMOSs. Each duty - cycle adjustment circuit is used to adjust the duty - cycle of a clock signal. When the digital control circuit determines that it is necessary to adjust the duty - cycle of one or more clock signals according to the selection module number and the detection error, it sends a control signal to the duty - cycle adjustment circuit of the one or more clock signals to adjust the number of connected PMOSs or the number of connected NMOSs in the corresponding duty - cycle adjustment circuit. Here, the PMOS and NMOS can be connected in the structure of an inverter, and the number of PMOS transistors and NMOS transistors is adjusted to change the phase characteristics of the output signal.

[0015] Optionally, the multi-phase clock generation circuit includes 8 cascaded shift registers. The four-phase clock signal is respectively input to the clock terminals of the first to fourth shift registers and the fifth to eighth shift registers to obtain an eight-phase clock signal. The multi-phase clock generation circuit can also be used to generate clock signals such as four-phase and sixteen-phase. Two or more inverters can be connected between the shift registers to enhance the driving ability.

[0016] Optionally, the multiplexing module includes one or more levels of transmission gate circuits, the comparison module is a comparator, and the multi-phase clock error detection circuit further includes an amplifier connected to the output of the comparator and a latch connected to the output of the amplifier.

[0017] According to a second aspect of the present disclosure, there is provided a multi-phase clock calibration circuit, which includes a multi-phase clock error detection circuit, which includes a first set of DC component extraction modules, a phase difference detection circuit, a second set of DC component extraction modules, a multiplexing module, and a comparison module. Among them, the multi-phase clock signal is input to the comparison module via the first set of DC component extraction modules and the multiplexing module or is input to the comparison module via the multiplexing module and the first set of DC component extraction modules. The multi-phase clock signal is input to the comparison module via the phase difference detection circuit, the second DC component extraction module, and the multiplexing module or is input to the comparison module via the phase difference detection circuit, the multiplexing module, and the second DC component extraction module. The comparison module outputs a detection error digital control circuit, which assigns a selection module number to each sub-module in the multiplexing module and corresponds the number to each detection error; a multi-phase clock adjustment circuit, whose input terminal is the multi-phase clock signal, and each group of clock signals with opposite phases is connected to a duty cycle adjustment circuit and a phase adjustment circuit. The multi-phase clock adjustment circuit adjusts the duty cycle or phase of one or more clock signals according to the output of the digital control circuit.

[0018] The multi-phase clock calibration circuit according to the embodiment of the present disclosure is not only applicable to the analog-to-digital conversion module in a receiver for high-speed communication, but can also be used in other application scenarios that require precise control of phase errors.

[0019] Optionally, the multi-phase clock signal is input to the comparison module via the first set of DC component extraction modules and the multiplexing module or is input to the comparison module via the multiplexing module and the first set of DC component extraction modules, for detecting the duty cycle error between each group of clock signals with opposite phases in the multi-phase clock signal.

[0020] Optionally, the phase difference detection circuit detects the phase difference of at least two groups of clock signals, and the second DC component extraction module extracts the DC component of the phase difference of the two groups of clock signals.

[0021] Optionally, the phase difference detection circuit includes an exclusive - OR logic circuit. The phase difference detection circuit performs exclusive - OR operations on the following four groups of clock signals: the clock signals with phases of 0 degrees and 90 degrees, the clock signals with phases of 0 degrees and 270 degrees, the clock signals with phases of 180 degrees and 270 degrees, and the clock signals with phases of 90 degrees and 180 degrees, to obtain corresponding first to fourth phase difference signals. The second DC component extraction module extracts the DC component from the signal obtained by superimposing the first and third phase difference signals, and extracts the DC component from the signal obtained by superimposing the second and fourth phase difference signals.

[0022] Optionally, the phase adjustment circuit includes at least one set of connected inverters and variable capacitors. Each phase adjustment circuit is used to adjust the phase of a clock signal. When the digital control circuit determines that it is necessary to adjust the phase of one or more clock signals according to the selection module number and the detection error, a control signal is sent to the phase adjustment circuits corresponding to the one or more clock signals to adjust the capacitance value of the corresponding variable capacitor.

[0023] Optionally, the duty - cycle adjustment circuit includes a variable number of connected PMOSs and a variable number of connected NMOSs. Each duty - cycle adjustment circuit is used to adjust the duty cycle of a clock signal. When the digital control circuit determines that it is necessary to adjust the duty cycle of one or more clock signals according to the selection module number and the detection error, a control signal is sent to the duty - cycle adjustment circuits of the one or more clock signals to adjust the number of connected PMOSs or the number of connected NMOSs in the corresponding duty - cycle adjustment circuit.

[0024] Optionally, the phase difference detection circuit includes an exclusive - OR logic circuit. The phase difference detection circuit performs exclusive - OR operations on the following four groups of clock signals: the clock signals with phases of 0 degrees and 45 degrees, the clock signals with phases of 45 degrees and 90 degrees, the clock signals with phases of 180 degrees and 225 degrees, and the clock signals with phases of 225 degrees and 270 degrees, to obtain corresponding fifth to eighth phase difference signals. The second DC component extraction module extracts the DC component from the signal obtained by superimposing the fifth and eighth phase difference signals, and extracts the DC component from the signal obtained by superimposing the sixth and seventh phase difference signals.

[0025] Implementing any device of the present disclosure does not necessarily require achieving all of the above - mentioned advantages simultaneously. Other features and advantages of the present disclosure will be described in subsequent embodiments of the specification, and, in part, will become apparent from the embodiments of the specification, or will be understood by implementing the present disclosure. The objectives and advantages of the embodiments of the present disclosure can be realized and obtained through the structures pointed out in the specification, claims, and drawings. Description of the Drawings

[0026] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0027] Figure 1 is a multi-phase clock generation circuit according to an embodiment of the present disclosure;

[0028] Figure 2 is a schematic structural diagram of a clock generation circuit for generating an eight-phase clock from a four-phase clock according to an embodiment of the present disclosure;

[0029] Figure 3 is Figure 2 a timing diagram of multiple shift registers in the clock generation circuit of;

[0030] Figure 4 is a schematic structural diagram of an eight-phase clock duty cycle adjustment circuit according to an embodiment of the present disclosure;

[0031] Figure 5 is Figure 4 a timing diagram of some input and output signals of the eight-phase clock duty cycle adjustment circuit shown in;

[0032] Figure 6 is a schematic structural diagram of an eight-phase clock error detection circuit according to an embodiment of the present disclosure;

[0033] Figure 7 is a partial schematic structural diagram of a multi-phase clock adjustment circuit according to an embodiment of the present disclosure;

[0034] Figure 8 is Figure 7 a circuit example of a partial structure of the clock adjustment circuit in; Specific Embodiments

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. Various different embodiments can be combined with each other to form other embodiments not shown in the following description. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0036] Unless otherwise defined, technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar terms used in the specification and claims of this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "an" do not necessarily denote a quantity limitation. Terms such as "comprising" or "including" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left" and "right" are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0037] Figure 1 Shown is a multi-phase clock generation circuit according to an embodiment of the present disclosure. The circuit includes a multi-phase clock generation circuit 11, a multi-phase clock duty cycle adjustment circuit 12, a multi-phase clock adjustment circuit 13, and a multi-phase clock error detection circuit 14.

[0038] The multi-phase clock generation circuit 11 can be used to generate an initial multi-phase clock signal. For example, a clock signal with half the number of input phases can be used to generate a clock signal of the target phase via a plurality of cascaded registers. The cascaded connection of the plurality of registers enables the output terminal (Q terminal) of the previous register to be connected to the data terminal (D terminal) of the subsequent register between adjacent registers. The number of cascaded registers corresponds to the number of phases of the multi-phase clock to be generated. For example, an 8-phase clock signal can be obtained by inputting a 4-phase clock signal, and a 16-phase clock signal can be obtained by inputting an 8-phase clock signal.

[0039] The multi-phase clock duty cycle adjustment circuit 12 can adjust the duty cycles of the clock signals of multiple phases as needed, and it can utilize delay units to obtain the required duty cycles. The delay time of the delay unit can be determined according to the required duty cycle. When the output duty cycle of the multi-phase clock generation circuit 11 meets the requirements, the multi-phase clock duty cycle adjustment circuit 12 can be omitted. The multi-phase clock adjustment circuit 13 adjusts the phases and duty cycles of the corresponding clock signals according to the clock signal phase difference detected by the multi-phase clock error detection circuit 14 and the duty cycle comparison result, to obtain a calibrated multi-phase clock signal. Figures 2 - 5 Taking an eight-phase clock generation circuit as an example, the circuit structures of the multi-phase clock generation circuit 11, the multi-phase clock duty cycle adjustment circuit 12, the multi-phase clock adjustment circuit 13, and the multi-phase clock error detection circuit 14 are shown. Figures 2 - 5The circuit structure shown is exemplary and is not intended to limit the scope of the present disclosure.

[0040] As Figure 2 shown, this embodiment of the present disclosure generates an eight-phase clock based on a four-phase clock. The input four-phase clock signals are ick_d0_dp, ick_d0_dn, ick_d90_dp, and ick_d90_dn, which respectively represent the clock signal of the 0th phase, the inverted clock signal of the 0th phase (i.e., the 180-degree clock signal), the clock signal of the 90-degree phase, and the inverted clock signal of the 90-degree phase (i.e., the 270-degree clock signal). When identifying the clock signal, the phase greater than or equal to 0 and less than 180 degrees is identified as the P-channel phase, and the phase greater than or equal to 180 degrees and less than 360 degrees is identified as the N-channel phase.

[0041] The circuit includes eight cascaded shift registers, and the number of shift registers corresponds to the number of phases of the clock signal to be generated. The four-phase clock signals are sequentially input to the first to fourth shift registers and the fifth to eighth shift registers. The data terminal of the first shift register can input the 2-divided clock signal of one phase clock signal of the four-phase clock signal. This signal can be obtained through a frequency division circuit. The circuit can generate other numbers of phase clock signals such as four-phase clock or sixteen-phase clock by increasing or decreasing the number of registers.

[0042] More specifically, the input clock signal ick_d0_dp is frequency-divided (here it is divided by two), and is input to the first shift register via an inverter. Among the eight cascaded shift registers, the output terminal and the data terminal between adjacent shift registers are connected via two inverters. Thus, by using ick_d0_dp, ick_d90_dn, ick_d0_dn, ick_d90_dp, ick_d0_dp, ick_d90_dn, ick_d0_dn, ick_d90_dp input to the clock terminals (CLK) of the eight shift registers, an eight-phase clock signal, namely wck_d0_dn, wck_d135_dn, wck_d90_dp, wck_d45_dn, wck_d0_dp, wck_d135_dp, wck_d90_dn, and wck_d45_dp, can be generated.

[0043] Figure 3 shows Figure 2Timing schematic diagrams of the data terminal signals of the first to eighth shift registers and the output clock signals. The frequency of the eight-phase clock signal is half of the four-phase clock frequency, and its duty cycle is the same as that of the four-phase clock frequency. The data terminal signals of the first to eighth shift registers are wck_shift_0, wck_shift_1, wck_shift_2, wck_shift_3, wck_shift_4, wck_shift_5, wck_shift_6, and wck_shift_7 respectively. Although the clock signals input to the first to fourth and fifth to eighth shift registers are the same, the output clock signals are opposite due to the opposite signals at the data terminals, thus forming a complete eight-phase clock signal.

[0044] The hardware structure for generating the eight-phase clock signal using the above structure is simple, without complex frequency division logic, and the generated phase deviation is small.

[0045] In the above embodiment, the two-stage inverter is an optional part, which can be used to enhance the driving ability, or other electrical components can be selected to replace the two-stage inverter. The register can also be implemented with various devices, such as latches, flip-flops, register arrays, etc. Any circuit that can implement the above functions of the register is included in the scope of the register described in the above embodiment.

[0046] Figure 4 It is a schematic structural diagram of an eight-phase clock duty cycle adjustment circuit according to an embodiment of the present disclosure. This duty cycle adjustment circuit does not require a phase interpolator and a delay locked loop, and only needs to use delay units and logical operations to achieve duty cycle adjustment.

[0047] For a clock signal, performing a logical operation on it with another signal having the same frequency can generate a new clock signal with an adjusted duty cycle. This another signal is a signal selected from a multi-phase clock signal and can be subjected to a delay process. According to the desired duty cycle, the delay size and logical operation are determined.

[0048] In this embodiment, the logical operation can be a NAND operation. The function of the inverter in this circuit is similar to Figure 1 For each signal in the multi-phase clock signal, a clock signal with a fixed phase difference from it is selected according to the duty cycle to be generated, and it is delayed by a predetermined time. A new set of multi-phase clock signals with a changed duty cycle can be obtained by performing a NAND operation on each pair of signals in each group. The phase difference and delay of each pair of signals in each group are the same.

[0049] Figure 4In the example, for each clock signal, another clock signal with a 90-degree phase difference from it is selected. By performing a NAND operation on each clock signal and another clock signal delayed by a certain time, a clock signal with an adjusted duty cycle is output. For example, after passing through a delay unit, wck_d90_dn performs a NAND operation with wck_d0_dp, and after passing through two inverters, ock_d0_dp with an adjusted duty cycle is output; after passing through a delay unit, wck_d135_dn performs a NAND operation with wck_d45_dp, and after passing through two inverters, ock_d45_dp with an adjusted duty cycle is output. The duty cycles of the clock signals with other phases are adjusted similarly. The delay times of delay units 1 to 8 are the same, and the duty cycles of the output eight-phase clock signals are the same. Figure 5 shows a schematic diagram of the timing diagram of some clock signals generated by the Figure 4 circuit before and after duty cycle adjustment.

[0050] In one example, after inversion, the duty cycles of the output eight-phase clock signals ock_d0_dp, ock_d45_dp, ock_d90_dp, ock_d135_dp, ock_d0_dn, ock_d45_dn, ock_d90_dn, and ock_d135_dn are not higher than 25%, resulting in non-overlapping clock signals.

[0051] To meet the requirements of the analog-to-digital converter sampling for the clock signal, the embodiments of the present disclosure design an eight-phase clock signal with a specific duty cycle. To ensure that the data sampled in each phase does not repeat with other phases, the input data will be divided into multiple groups during use, and the clocks within each group do not overlap. Figure 4 If the duty cycle of the shown circuit is not greater than 25%, it can ensure that at least four clocks in two groups do not overlap. When the duty cycle is adjusted below 12.5%, eight non-overlapping clocks can be obtained. The circuit can be modified according to the number of phase clock signals to be applicable to other multi-phase clock signals.

[0052] Due to factors such as mismatch between devices and parasitic traces, the generated multi-phase clocks will have phase errors. Therefore, a circuit for detecting and calibrating phase errors is required.

[0053] Figure 6 shows an eight-phase clock error detection circuit. Figure 6In the illustrated embodiment, the detection circuit at least includes a duty cycle detection circuit 601, a phase difference detection circuit 602, a second DC component extraction module 603, a multiplexing module 604, and a comparison module 605. It may also include an amplification module 606 and a latching module 607. The output of the duty cycle detection circuit 601 and the output of the phase difference detection circuit 602 are connected to one path of the comparison module through the multiplexing module 604 via the output of the second DC component extraction module 603 to output the comparison result. Optionally, the duty cycle detection circuit 601 and the phase difference detection circuit 602 may also be respectively connected to separate comparison modules via the multiplexing module to obtain two error signals for the duty cycle and the phase difference. The above circuit structures of each part can be adjusted according to the number of phases, so as to be applicable to other multi-phase clocks.

[0054] The duty cycle detection circuit 601 includes a first DC component extraction module for extracting the DC component of the eight-phase clock signal, where the DC component is extracted for each clock signal respectively. Every two signals with opposite phases in the eight-phase clock signal are divided into a group, and the two DC component extraction modules of each group are connected to one selection module in the multiplexing module. The selection module is connected or disconnected from its corresponding group of DC component extraction modules according to the received control signal, so that only the detection result extracted by one group is output to the comparison module 605 at each predetermined time interval. The comparison module 605 compares the DC components of the two signals with opposite phases in each group. The comparison result can be amplified by the amplification module 606 and output to the digital control circuit (not shown) via the latching module 607. The comparison module 605, the amplification module 606, and the latching module 607 can be implemented by a comparator, an amplifier, and a latch respectively, or other circuit structures can be adopted according to needs to implement the corresponding functions.

[0055] The first and second DC component extraction modules may include one or more DC component extraction modules, and the number of modules is related to the number of clock signals to be processed. The first and second DC component extraction modules can be implemented by a low-pass filter, which has a simple circuit implementation and low cost. Converting the duty cycle information into DC information can also be achieved by other circuits. After obtaining the DC components of the two clock signals with opposite phases, compare them to obtain the comparison result of the duty cycle. The first and second DC component extraction modules can be placed before the multiplexing module or after the multiplexing module. If the DC component extraction modules are placed after the multiplexing module, the outputs of the DC component extraction modules will be connected to the comparison module.

[0056] In Figure 6 In the illustrated embodiment, when the multiplexing module is placed before the DC component extraction modules, first select a group of signals to be extracted with the DC component, and then extract the DC component through the corresponding DC component extraction module.

[0057] exist Figure 6 In the multi-channel selection module, each selection module can be turned on and off according to control signals from the digital control circuit. When turned off, it prevents the connected upstream circuit from affecting the subsequent comparison module. During each detection and comparison period, only one corresponding selection module is turned on, allowing the comparison module to compare a set of measurement signals and output the comparison results. The digital control circuit can number each selection module to determine which set of detection results is output by the error signal err. The selection module can include one or more stages of transmission gate circuits.

[0058] For example, the duty cycle information of ock_d0_dp and ock_d0_dn is converted into a DC signal by the DC component extraction module and output to the comparison module 605 through the selection module. If the duty cycle of ock_d0_dp is slightly greater than the duty cycle of ock_d0_dn, the comparison module, the amplification module and the latch module can output "1" to correspond to the above situation, and output the result to the digital control circuit to feedback adjust ock_d0_dp and / or ock_d0_dn so that the duty cycles of the two are the same. This adjustment method will refer to Figure 7 Provide explanation.

[0059] Phase difference detection circuit 602 divides the eight-phase clock signal into multiple groups to detect phase errors. From the results of each group of phase errors, the clock signal with the lagging phase can be found. Figure 7 Specifically, Figure 6 The first group of signals includes ock_d0_dp, ock_d90_dp, ock_d0_dn, and ock_d90_dn, and their corresponding phases are 0 degrees, 90 degrees, 180 degrees, and 270 degrees. An exclusive OR logic circuit generates signals corresponding to the four phase differences between ock_d0_dp and ock_d90_dp, ock_d0_dn and ock_d90_dn, ock_d0_dn and ock_d90_dp, and ock_d0_dp and ock_d90_dn. In this example, if the XOR result of ock_d0_dp and ock_d90_dp, ock_d0_dn, and ock_d90_dn is greater than the XOR result of ock_d0_dn and ock_d90_dp, ock_d0_dp, and ock_d90_dn, after passing through the second DC component extraction module, it indicates that ock_d90_dp and ock_d90_dn are out of phase. The detected DC error information, after passing through the multi-channel selection module and comparison module, is fed back to the multi-channel clock adjustment circuit for calibration.

[0060] The second group of signals includes ock_d0_dp, ock_d45_dp, ock_d90_dp, ock_d0_dn, ock_d45_dn, and ock_d90_dn, which detect the phase errors between ock_d0_dp, ock_d45_dp, and ock_d90_dp, and the phase errors between ock_d0_dn, ock_d45_dn, and ock_d90_dn. Similarly, by comparing the extracted DC components, the clock signal with a lagging phase is found, and then it is adjusted. Specifically, the phase differences between ock_d0_dp and ock_d45_dp, ock_d45_dp and ock_d90_dp, ock_d0_dn and ock_d45_dn, and ock_d45_dn and ock_d90_dn are obtained through an exclusive-OR logic circuit. After superposition, they enter the second DC component extraction module, and through the comparison of the two groups of signals, the information on whether the phases of ock_d45_dp and ock_d45_dn are lagging or leading can be obtained, and thus how to adjust them is determined.

[0061] Similar to the second group of signals, the third group of signals (not shown) may include ock_d0_dp, ock_d90_dp, ock_d135_dp, ock_d0_dn, ock_d90_dn, and ock_d135_dn, which detect the phase differences between ock_d90_dn, ock_d135_dn, and ock_d0_dp, and between ock_d90_dp, ock_d135_dp, and ock_d0_dn. Specifically, the phase differences between ock_d90_dp and ock_d135_dp, ock_d135_dp and ock_d0_dn, ock_d90_dn and ock_d135_dn, and ock_d135_dn and ock_d0_dp are obtained through an exclusive-OR logic circuit, and the information on whether the phases of ock_d135_dp and ock_d135_dn are lagging or leading is determined, and thus how to adjust them is determined.

[0062] The above examples are the methods for detecting the phase errors of eight-phase clock signals. For four-phase clock signals, the circuit for detecting the first group of signals can be used to measure the phase errors of four-phase clock signals. For sixteen-phase clock signals, four groups of signals can be similarly added on the basis of the above circuit to measure the phase errors of the clock signals of the remaining eight phases.

[0063] The above circuit realizes the conversion of high gain multiple from phase error to DC error, and can accurately detect phase errors at the femtosecond level.

[0064] Figure 7The figure shows a partial structural schematic diagram of a multi-phase clock adjustment circuit according to an embodiment of the present disclosure. The circuit includes a decoding control circuit 701, a phase adjustment circuit 702, and a duty cycle adjustment circuit 703. Figure 7 Only the phase adjustment circuit 702 and the duty cycle adjustment circuit 703 for a set of clock signals with opposite phases are shown. The multi-phase clock adjustment circuit includes a phase adjustment circuit and a duty cycle adjustment circuit for each set of clock signals with opposite phases, and the structures for the remaining phases are the same as those shown in the figure, so the remaining parts are omitted here. In Figure 7 this, the clock signals with opposite phases are input into their respective phase adjustment circuits and duty cycle adjustment circuits, and they can be adjusted independently. Therefore, this circuit can be used as an independent phase adjustment circuit and duty cycle adjustment circuit for each clock signal. The decoding control circuit can be a part of the digital control circuit, which receives the error signal err and the number of the selection module corresponding to the error signal. The decoding control circuit 701 determines whether the error signal err is a duty cycle error or a phase error according to the received number, and determines the clock signal to be adjusted corresponding to the error signal. Figure 7 Only the phase adjustment circuit 702 and the duty cycle adjustment circuit 703 for ock_d0_dp and ock_d0_dn are shown. Both the phase adjustment circuit 702 and the duty cycle adjustment circuit 703 can include sub-circuits for adjusting ock_d0_dp and ock_d0_dn respectively. For example, the phase or duty cycle of ock_d0_dp can be adjusted separately. The decoding control circuit 701 can send control signals to the sub-circuits respectively. For each set of clock signals with opposite phases, a phase adjustment circuit and a duty cycle adjustment circuit are provided, and they receive the signals sent by the decoding control circuit 701. Since the circuit structures are the same, only ock_d0_dp and ock_d0_dn are taken as examples for illustration here.

[0065] For example, if it is determined according to the received number of the selection module that the error signal err is a phase error, and it is determined that this error signal indicates that ock_d90_dp and ock_d90_dn lag behind ock_d0_dp and ock_d0_dn, then the phase adjustment circuit is used to adjust the phases of ock_d0_dp and ock_d0_dn and / or ock_d90_dp and ock_d90_dn, that is, to adjust the phases of ock_d0_dp and ock_d0_dn backward and / or to adjust the phases of ock_d90_dp and ock_d90_dn forward.

[0066] For an example circuit of the phase adjustment circuit 702, reference can be made to Figure 8The circuit may include one or more stages of inverters and their adjustable load capacitors. By adjusting the capacitance value of the load capacitor, the phase of the corresponding clock signal can be adjusted. Specifically, the clock signal of each phase is connected to one end of the adjustable capacitor through an inverter, and the other end of the adjustable capacitor is grounded. Each clock signal can be input to a circuit of one stage of inverter and its adjustable load capacitor, or input to a circuit of multiple stages of inverters and their adjustable load capacitors, so that the adjustment accuracy is higher. According to the phase change range caused by PVT, the specific implementation method can be selected to make the adjustment range cover the phase change range. The adjustment of the capacitance value can be achieved by adjusting the capacitance value of the load capacitor or the number of load capacitors. The adjustable load capacitor can be adjusted according to the control signal output by the decoding control circuit. In the example described above, if it is detected that ock_d90_dp and ock_d90_dn lag behind ock_d0_dp and ock_d0_dn, it is possible to choose to reduce the load capacitors of the two paths of ock_d90_dp and ock_d90_dn, while increasing the load capacitors of ock_d0_dp and ock_d0_dn, or only increasing the load capacitors of ock_d0_dp and ock_d0_dn, or only reducing the load capacitors of ock_d90_dp and ock_d90_dn.

[0067] The duty cycle adjustment circuit 703 may be composed of multiple parallel PMOSs and multiple parallel CMOSs. By adjusting the number of parallel PMOSs or parallel NMOSs, the duration of the high level or low level can be changed, thereby adjusting the duty cycle. For example, PMOSs and NMOSs can form a multi-stage inverter circuit for the duty cycle adjustment circuit 703.

[0068] For example, if it is determined according to the number of the selection module that the error signal corresponds to the duty cycle error between ock_d0_dp and ock_d0_dn, the duty cycle adjustment circuit 703 can be used to adjust ock_d0_dp and / or ock_d0_dn according to the meaning represented by the error value (for example, "1" means that the duty cycle of ock_d0_dp is greater than the duty cycle of ock_d0_dn). By adjusting the number of PMOSs and NMOSs, the phase error and / or duty cycle error between the same group of clocks P and N can be calibrated. The duty cycle adjustment circuit can also be implemented in other circuit forms, not limited to the above method of adjusting the number of PMOSs and NMOSs.

[0069] The output signals of the clock adjustment circuit, such as ock_d0p, ock_d0n, etc., will return to Figure 6 the input end of the eight-phase clock error detection circuit shown, thereby realizing a high-precision clock signal.

[0070] Figure 6 and Figure 7The circuit shown can be used as a clock calibration circuit to adjust the phase and duty cycle errors that occur in a multi-phase clock generator.

[0071] Compared with the technical solution using a delay-locked loop, the embodiments of the present disclosure can effectively reduce the calibration process of the chip, simplify the chip design, and reduce costs. In addition, the embodiments of the present disclosure only use simple logic circuits, can generate multi-phase clocks, and detect and calibrate the phase errors between them. The calibration circuit can automatically calibrate to the optimal phase according to the changes in PVT (Process, Voltage, Temperature), improving the reliability of the chip under different working conditions and reducing the chip mass production test cost.

[0072] The clock calibration circuit proposed by the present disclosure is not limited to the usage scenario of a time-interleaved analog-to-digital converter, and can also be extended to other scenarios that use multi-phase clocks and require precise control of phase errors, such as the digital-to-analog conversion type output driver at the transmitting end of a high-speed serial interface circuit.

[0073] The above are only exemplary embodiments of the present disclosure and are not used to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A multi-phase clock generation circuit, characterized in that Comprising: A multi-phase clock generation circuit that generates a multi-phase clock signal through a plurality of serially connected registers; A multi-phase clock error detection circuit, which includes a first set of DC component extraction modules, a phase difference detection circuit, a second set of DC component extraction modules, a multiplexing module, and a comparison module. The multi-phase clock signal is input to the comparison module via the first set of DC component extraction modules and the multiplexing module or via the multiplexing module and the first set of DC component extraction modules. The multi-phase clock signal is input to the comparison module via the phase difference detection circuit, the second DC component extraction module, and the multiplexing module or via the phase difference detection circuit, the multiplexing module, and the second DC component extraction module. The comparison module outputs a detected error, wherein the multi-phase clock generation circuit does not include a phase-locked loop; A digital control circuit that assigns a selection module number to each sub-module in the multiplexing module and associates the number with each detected error; A multi-phase clock adjustment circuit, which includes a duty cycle adjustment circuit and a phase adjustment circuit. The multi-phase clock adjustment circuit adjusts the duty cycle or phase of one or more clock signals according to the output of the digital control circuit.

2. The multi-phase clock generation circuit according to claim 1, wherein The multi-phase clock signal is input to the comparison module via the first set of DC component extraction modules and the multiplexing module or via the multiplexing module and the first set of DC component extraction modules to detect the duty cycle error between each pair of clock signals with opposite phases in the multi-phase clock signal.

3. The multi-phase clock generation circuit according to claim 1, wherein The phase difference detection circuit detects the phase difference between at least two sets of clock signals, and the second DC component extraction module extracts the DC component of the phase difference between the two sets of clock signals.

4. The multi-phase clock generation circuit according to claim 3, characterized in that the phase difference The detection circuit includes an exclusive-OR logic circuit. The phase difference detection circuit performs an exclusive-OR operation on the following four sets of clock signals: the clock signals with phases of 0 degrees and 90 degrees, the clock signals with phases of 0 degrees and 270 degrees, the clock signals with phases of 180 degrees and 270 degrees, and the clock signals with phases of 90 degrees and 180 degrees to obtain the corresponding first to fourth phase difference signals. The second DC component extraction module extracts the DC component of the signal obtained by superimposing the first and third phase difference signals and extracts the DC component of the signal obtained by superimposing the second and fourth phase difference signals.

5. The multi-phase clock generation circuit according to claim 1, wherein Also included is a multi-phase clock duty cycle adjustment circuit, which includes a logic circuit and a delay circuit. It receives the output of the multi-phase clock generation circuit and uses the logic circuit to perform a logic operation on each clock signal and another clock signal in the multi-phase clock signal delayed by the delay circuit as a set of signals to obtain a multi-phase clock signal with a predetermined duty cycle, wherein the delay magnitude of the delay circuit is determined according to the predetermined duty cycle.

6. The multi-phase clock generation circuit according to claim 1, wherein The phase adjustment circuit includes at least one set of connected inverters and variable capacitors. Each phase adjustment circuit is used to adjust the phase of a clock signal. When the digital control circuit determines that it is necessary to adjust the phase of one or more clock signals according to the selection module number and the detected error, a control signal is sent to the phase adjustment circuits corresponding to the one or more clock signals to adjust the capacitance value of the corresponding variable capacitors.

7. The multi-phase clock generation circuit according to claim 1, wherein The duty cycle adjustment circuit includes PMOSs with variable connection numbers and NMOSs with variable connection numbers. Each duty cycle adjustment circuit is used to adjust the duty cycle of a clock signal. When the digital control circuit determines that it is necessary to adjust the duty cycles of one or more clock signals according to the selection module number and the detection error, a control signal is sent to the duty cycle adjustment circuits of the one or more clock signals to adjust the number of connected PMOSs or the number of connected NMOSs in the corresponding duty cycle adjustment circuits.

8. The multi-phase clock generation circuit according to claim 1, wherein The multi-phase clock generation circuit includes 8 cascaded shift registers. The four-phase clock signal is respectively input to the clock terminals of the first to fourth shift registers and the fifth to eighth shift registers to obtain an eight-phase clock signal.

9. The multi-phase clock generation circuit according to claim 1, wherein The multiplexing module includes one or more stages of transmission gate circuits. The comparison module is a comparator. The multi-phase clock error detection circuit further includes an amplifier connected to the output of the comparator and a latch connected to the output of the amplifier.

10. A multi-phase clock calibration circuit, characterized in that Comprising A multi-phase clock error detection circuit, which includes a first set of DC component extraction modules, a phase difference detection circuit, a second set of DC component extraction modules, a multiplexing module, and a comparison module. Among them, the multi-phase clock signal is input to the comparison module via the first set of DC component extraction modules and the multiplexing module or is input to the comparison module via the multiplexing module and the first set of DC component extraction modules. The multi-phase clock signal is input to the comparison module via the phase difference detection circuit, the second DC component extraction module, and the multiplexing module or is input to the comparison module via the phase difference detection circuit, the multiplexing module, and the second DC component extraction module. The comparison module outputs a detection error, where the multi-phase clock calibration circuit does not include a phase-locked loop; A digital control circuit, which assigns a selection module number to each sub-module in the multiplexing module and corresponds the number to each detection error; A multi-phase clock adjustment circuit, whose input terminal is a multi-phase clock signal. Each group of clock signals with opposite phases is connected to a duty cycle adjustment circuit and a phase adjustment circuit. The multi-phase clock adjustment circuit adjusts the duty cycle or phase of one or more clock signals according to the output of the digital control circuit.

11. The multi-phase clock calibration circuit according to claim 10, wherein The multi-phase clock signal is input to the comparison module via the first set of DC component extraction modules and the multiplexing module or is input to the comparison module via the multiplexing module and the first set of DC component extraction modules, for detecting the duty cycle error between each group of clock signals with opposite phases in the multi-phase clock signal.

12. The multi-phase clock calibration circuit according to claim 10, wherein The phase difference detection circuit detects the phase difference of at least two groups of clock signals, and the second DC component extraction module extracts the DC component of the phase difference of the two groups of clock signals.

13. The multi-phase clock calibration circuit according to claim 12, wherein the phase difference The detection circuit includes an exclusive-OR logic circuit. The phase difference detection circuit performs exclusive-OR operations on the following four groups of clock signals: the clock signals with phases of 0 degrees and 90 degrees, the clock signals with phases of 0 degrees and 270 degrees, the clock signals with phases of 180 degrees and 270 degrees, and the clock signals with phases of 90 degrees and 180 degrees, to obtain corresponding first to fourth phase difference signals. The second DC component extraction module extracts the DC component from the signal obtained by superimposing the first and third phase difference signals, and extracts the DC component from the signal obtained by superimposing the second and fourth phase difference signals.

14. The multi-phase clock calibration circuit according to claim 10, wherein The phase adjustment circuit includes at least one set of connected inverters and variable capacitors. Each phase adjustment circuit is used to adjust the phase of a clock signal. When the digital control circuit determines that it is necessary to adjust the phase of one or more clock signals according to the selection module number and the detection error, it sends a control signal to the phase adjustment circuit corresponding to the one or more clock signals to adjust the capacitance value of the corresponding variable capacitor.

15. The multi-phase clock calibration circuit according to claim 10, wherein The duty cycle adjustment circuit includes a variable number of connected PMOSs and a variable number of connected NMOSs. Each duty cycle adjustment circuit is used to adjust the duty cycle of a clock signal. When the digital control circuit determines that it is necessary to adjust the duty cycle of one or more clock signals according to the selection module number and the detection error, it sends a control signal to the duty cycle adjustment circuit of the one or more clock signals to adjust the number of connected PMOSs or the number of connected NMOSs in the corresponding duty cycle adjustment circuit.

16. The multi-phase clock calibration circuit according to claim 13, wherein the phase difference The detection circuit includes an exclusive-OR logic circuit. The phase difference detection circuit performs exclusive-OR operations on the following four groups of clock signals: the clock signals with phases of 0 degrees and 45 degrees, the clock signals with phases of 45 degrees and 90 degrees, the clock signals with phases of 180 degrees and 225 degrees, and the clock signals with phases of 225 degrees and 270 degrees, to obtain corresponding fifth to eighth phase difference signals. The second DC component extraction module extracts the DC component from the signal obtained by superimposing the fifth and eighth phase difference signals, and extracts the DC component from the signal obtained by superimposing the sixth and seventh phase difference signals.

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