NMOS type high-end ideal diode based on differential amplifier

Abstract

The invention relates to the technical field of diodes, in particular to an NMOS type high-end ideal diode based on a differential amplifier. A circuit is composed of an NMOS main tube, a differential amplification circuit, a voltage comparator, a bias power supply and the like. The differential amplification circuit can be one of an NPN (negative-positive-negative) type, an NMOS (N-channel metal oxide semiconductor) type, a PNP (positive-negative-positive-negative) type and a PMOS (P-channel metal oxide semiconductor) type, the differential amplification circuit is used for comparing voltage of a drain electrode and a source electrode of an NMOS main tube, an output signal is loaded to the voltage comparator again to be amplified, and the voltage comparator outputs a signal to control on and off of the NMOS main tube. Four high-end ideal diode circuits are designed by complementing advantages and complementing disadvantages, and software simulation verification shows that the designed circuit can realize an anti-backflow function, can meet the use occasion with a wide current range and protect an input power supply pre-stage circuit, and is simple in circuit, very low in cost and high in practicability.

Description

Technical Field

[0001] The invention relates to the technical field of power diodes, and in particular to an NMOS type high-end ideal diode based on a differential amplifier. Background Art

[0002] Diodes are used more and more because of their unidirectional conduction characteristics and backflow prevention function. In particular, Schottky diodes in series have a small voltage drop on the power supply, which is welcomed by more and more designers. Since the voltage drop of Schottky diodes is greater than that of MOS tubes, for some voltage-sensitive circuits, MOS tubes with low impedance characteristics are more preferred to improve product reliability.

[0003] At present, the Oring circuit is used in many occasions to ensure that each single power supply is independent of each other and does not have backflow. It is most commonly used in current sharing circuits to meet different power requirements. Therefore, a low-loss high-end ideal diode and an ultra-low-loss ideal diode are needed to further reduce the voltage drop and have the function of preventing backflow and protecting the front stage, so as to minimize the loss and extend the battery working time.

[0004] The main technical solutions for high-end ideal diodes implemented by existing technologies are as follows.

[0005] PMOS main tube + PMOS auxiliary tube (pair of tubes) technical solution: existing technology patent (an ultra-low loss ideal diode, patent number: CN201821304820.X);

[0006] NMOS main tube + NMOS auxiliary tube (pair of tubes) technical solution: It adopts NMOS main tube to realize high-end ideal diode. The circuit consists of one NMOS main tube, two NMOS auxiliary tubes, bias power supply VBIAS, etc. The load RL is located between the positive pole of power supply VCC and NMOS main tube.

[0007] MOS tube + voltage comparator (operational amplifier) ​​technical solution: The voltage comparator collects the voltage difference between the source and drain of the MOS tube, and after comparison, the output signal controls the conduction and cutoff of the MOS tube.

[0008] The differential amplifier circuit evolved from the amplifier circuit with a stable static operating point. It has different effects on different input signals. It has a strong inhibitory effect on common-mode signals and amplifies differential-mode signals. The amplification capacity of the circuit is related to the output mode. It is widely used in audio amplifiers, voltage comparators, data communication interfaces and other circuits.

[0009] Offset voltage, also known as input offset voltage (VIO), reflects the symmetry of the circuit, and its value is generally ±1 to 10mV. Overdrive voltage (VOD) is the differential voltage generated between the positive and negative inputs of the voltage comparator on the offset voltage (VIO), and the absolute value of the voltage difference between the dual input ports of the voltage comparator. To achieve accurate comparison, the overdrive voltage (VOD) should be higher than the offset voltage (VIO).

[0010] The input offset voltage (VIO) of TI's voltage comparator chip LM393B is VIO = ±0.37mV (typical value), |VIO| ≤ 2.5mV; the input offset voltage (VIO) of the voltage comparator chip LMC7211AIM5 is VIO = 3mV (typical value), |VIO| ≤ 8mV. When selecting a voltage comparator, you should choose a comparator chip with a lower offset voltage.

[0011] Since the voltage comparator works in the nonlinear region: in the actual application circuit, the voltage comparator circuit is often connected in the hysteresis voltage comparator mode, which enhances the anti-interference ability of the circuit. If the circuit has hysteresis characteristics, it is generally required that the hysteresis voltage is greater than the offset voltage, that is, ΔV=|VT1-VT2|≥VIO=2mV, which means that the drain-source channel conduction current ID>VIO / RD(ON)S through the MOS tube.

[0012] When the NMOS tube is turned on, the drain-source channel resistance RDS(ON) is relatively small. Assuming RDS(ON)=10mΩ, ID>VIO / RDS(ON)=2mV / 10mΩ=0.2A, it means that the current must be greater than 0.2A for the voltage comparator to work normally. Obviously, the NMOS tube is suitable for working occasions with large current.

[0013] The drain-source channel resistance RDS(ON) of the PMOS tube is relatively large. Assuming RDS(ON) = 100mΩ, ID>VIO / RDS(ON) = 2mV / 100mΩ = 0.02A, it means that the voltage comparator can work normally when the current is greater than 0.02A. Obviously, the PMOS tube is suitable for working occasions with small current.

[0014] So for the occasions where the working current is less than 0.2A, the first solution is to choose a PMOS tube model with RDS(ON)>100mΩ, satisfying RDS(ON)×ID>VIO, that is, RDS(ON)>VIO / ID; the second solution is to connect a current detection resistor R in series at the drain or source of the original POS tube to satisfy (R+RDS(ON))×ID>VIO, that is, R>VIO / ID-RDS(ON).

[0015] Whether it is an NMOS tube or a PMOS tube, there is a certain on-resistance when it is turned on. For example, the on-resistance of a power NMOS tube is about tens of milliohms, which is lower than the on-resistance of a PMOS tube under the same conditions. Once it is turned on, there is current, which will produce an on-voltage drop (the product of the on-current and the on-resistance). The on-voltage drop is the voltage difference between the drain and the source of the MOS tube. This voltage difference is loaded to the dual input ports of the differential amplifier circuit, and the differential amplifier circuit is used to amplify the signal (that is, the difference between the two signals). The differential signals output by the two output terminals are loaded again to the voltage comparator (the non-inverting terminal and the inverting terminal) to control the on and off of the tube and realize the function of an ideal diode.

[0016] It can be seen from the above technical scheme that by combining the characteristics of the differential amplifier circuit (dual input ports, dual output ports) and the hysteresis voltage comparator, the advantages are complemented by taking advantage of each other's strengths to design a new high-end ideal diode device based on differential amplifier technology to meet the needs of wide current range applications. Summary of the invention

[0017] The technical problem to be solved by the present invention is to provide an NMOS type high-end ideal diode based on a differential amplifier based on the above technical content.

[0018] In order to solve the above technical problems, the technical solution provided by the present invention is: an NMOS type high-end ideal diode based on a differential amplifier, the circuit comprising an NMOS main tube V1, a differential amplifier circuit, a voltage comparator U1 and a bias power supply VBIAS;

[0019] The dual input ports of the differential amplifier circuit are respectively connected to the drain and source of the NMOS supervisor V1 and compare the voltages. The dual input ends of the voltage comparator U1 receive the output information of the differential amplifier circuit, and the output end is connected to the gate of the NMOS supervisor V1 to control the conduction or cutoff of the NMOS supervisor V1.

[0020] Preferably, the differential amplifier circuit includes a transistor pair and a peripheral circuit;

[0021] The transistor pair includes any one of an NPN pair, an NMOS pair, a PNP pair, and a PMOS pair.

[0022] Preferably, the transistor pair is NPN auxiliary transistors V2 and V3, and the peripheral circuit includes resistors R1 to R5, wherein resistor R2 = R3, and resistor R4 = R5;

[0023] The bases of the NPN auxiliary tubes V2 and V3 are connected to the source and drain of the NMOS main tube V1 through resistors R4 and R5 respectively as dual input ports of the differential amplifier circuit;

[0024] The collectors of the NPN auxiliary tubes V2 and V3 are connected to the inverting end and the non-inverting end of the voltage comparator respectively as the dual output ports of the differential amplifier circuit. The collectors of the NPN auxiliary tubes V2 and V3 are also connected to the bias power supply VBIAS through resistors R2 and R3 respectively, and the emitters are connected to each other and grounded through resistor R1.

[0025] Preferably, the transistor pair is NMOS auxiliary transistors V2 and V3, and the peripheral circuit includes resistors R1 to R5, wherein resistor R2 = R3, and resistor R4 = R5;

[0026] The gates of the NMOS auxiliary tubes V2 and V3 are connected to the source and drain of the NMOS main tube V1 through resistors R4 and R5 respectively as dual input ports of the differential amplifier circuit;

[0027] The drains of the NMOS auxiliary tubes V2 and V3 are connected to the inverting end and the non-inverting end of the voltage comparator respectively as the dual output ports of the differential amplifier circuit. The drains of the NMOS auxiliary tubes V2 and V3 are also connected to the bias power supply VBIAS through resistors R2 and R3 respectively, and the sources are connected to each other and grounded through resistor R1.

[0028] Preferably, the transistor pair is a PNP auxiliary tube V2, V3, and the peripheral circuit includes resistors R1 to R5, wherein resistor R2 = R3, and resistor R4 = R5;

[0029] The bases of the PNP auxiliary tubes V2 and V3 are connected to the source and drain of the NMOS main tube V1 through resistors R4 and R5 respectively as dual input ports of the differential amplifier circuit;

[0030] The collectors of the PNP auxiliary tubes V2 and V3 are connected to the inverting terminal and the non-inverting terminal of the voltage comparator respectively as the dual output ports of the differential amplifier circuit, and are also grounded through the resistors R2 and R3;

[0031] The emitters of the PNP auxiliary tubes V2 and V3 are connected to the bias power supply VBIAS through the resistor R1.

[0032] Preferably, the transistor pair is a PMOS auxiliary transistor V2, V3, and the peripheral circuit includes resistors R1 to R5, wherein resistor R2 = R3, and resistor R4 = R5;

[0033] The gates of the PMOS auxiliary tubes V2 and V3 are connected to the source and drain of the NMOS main tube V1 through resistors R4 and R5 respectively as dual input ports of the differential amplifier circuit;

[0034] The drains of the PMOS auxiliary tubes V2 and V3 are connected to the inverting terminal and the non-inverting terminal of the voltage comparator respectively as the dual output ports of the differential amplifier circuit, and are also grounded through the resistors R2 and R3;

[0035] The sources of the PMOS auxiliary tubes V2 and V3 are connected to the bias power supply VBIAS through the resistor R1.

[0036] Compared with the prior art, the advantages of the present invention are: combining the differential amplifier circuit (dual input ports, dual output ports) and the hysteresis voltage comparator characteristics, due to the dual amplification of the differential amplifier and the voltage comparator, it is suitable for use in a wide current range. The circuit has a backflow prevention function, which can protect the previous stage circuit; it has low loss and small static current loss; the circuit is simple, the cost is very low, and the practicability is strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of an NMOS-type (main tube) high-side ideal diode implemented for an NPN pair differential amplifier;

[0038] Figure 2 Schematic diagram of an NMOS type (main tube) high-side ideal diode implemented for an NMOS pair differential amplifier;

[0039] Figure 3 Schematic diagram of an NMOS type (main tube) high-side ideal diode implemented for a PNP pair differential amplifier;

[0040] Figure 4 Schematic diagram of an NMOS type (main tube) high-side ideal diode implemented for a PMOS pair differential amplifier;

[0041] Figure 5 yes Figure 1 Forward conduction simulation;

[0042] Figure 6 yes Figure 1 Reverse cutoff simulation;

[0043] Figure 7 yes Figure 2 Forward conduction simulation;

[0044] Figure 8 yes Figure 2 Reverse cutoff simulation;

[0045] Fig. 9 yes Figure 3 Forward conduction simulation;

[0046] Fig.10 yes Figure 3 Reverse cutoff simulation;

[0047] Fig.11 yes Figure 4 Forward conduction simulation;

[0048] Fig.12 yes Figure 4 Reverse cutoff simulation. DETAILED DESCRIPTION

[0049] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0050] Implementation Method 1

[0051] An NMOS type high-side ideal diode based on a differential amplifier, the circuit is as follows Figure 1 As shown, it includes NMOS main tube V1, differential amplifier, voltage comparator U1, bias power supply VBIAS, etc. The differential amplifier is composed of NPN pair tubes V2 and V3, resistors R1 to R5, etc., which is a common emitter circuit, where R2 = R3, R4 = R5. The two bases of the NPN pair tubes V2 and V3 serve as the dual input ports of the differential amplifier, respectively detecting the source and drain voltages of the NMOS main tube V1. After the amplification of the pair tubes V2 and V3 of the differential amplifier, the two collector potentials of the V2 tube and the V3 tube serve as dual output ports, respectively outputting differential signals U- and U+, U- and U+, respectively connected to the inverting terminal and the non-inverting terminal of the voltage comparator U1, and the output signal V1G of the voltage comparator U1 controls the conduction and cutoff of the NMOS main tube V1.

[0052] The differential amplifier can overcome the problem of temperature drift. Under the action of differential mode signal, the current change of R1 is 0, that is, the resistor R1 has no feedback effect on the differential mode signal, which is equivalent to a short circuit. Therefore, the amplification ability of the differential mode signal is greatly improved, while simplifying the circuit and making the power supply and signal source "shared ground". The differential amplifier is also called a differential amplifier. The so-called "differential" means that the output voltage will change (change amount) only when there is a difference (change amount) in the potential between the dual input ports.

[0053] Differential amplifiers generally require ideal parameter symmetry, R2 = R3, R4 = R5, and the input characteristic curves and output characteristic curves of the NPN pair of tubes V2 and V3 completely overlap. Due to the dispersion of transistor characteristics, the parameters of any component cannot be ideally symmetrical, that is, the zero drift cannot be completely suppressed. However, in integrated circuits, since adjacent components have good symmetry and the parameters are basically equal, the ideal parameter symmetry can generally be achieved approximately. Therefore, the NPN pair of tubes V2 and V3 are preferably packaged together with the NPN pair of tubes chips to ensure that the parameters of the two tubes are basically equal.

[0054] The specific working principle is as follows.

[0055] When the DC power supply VCC=VCC1 is powered on (forward conduction), the current output by VCC first passes through the body diode of NMOS tube V1 (Vout=VCC-V F , V F =The diode conduction voltage drop), when the output current gradually increases, the internal power supply VCC is higher than the external voltage Vout (VCC>Vout), the voltage VA>VC, and the NPN tube V2 is more completely turned on than the NPN tube V3 (the drain-source channel conduction impedance of the V2 tube is V2R CE Compared with the drain-source channel conduction impedance V3R of V3 tube CE The conduction degree depends on the base voltage), which means that the voltage U+>U-, the differential signal U-, U+ output by the differential amplifier is transmitted to the voltage comparator U1, and the voltage comparator U1 outputs a high level, that is, V1G≈VBIAS. When V1 GS =V1G-VCC>V TN (V TN The drain-source channel of the NMOS tube V1 is turned on, and the VCC current flows through the drain-source low-impedance channel of the NMOS tube V1 to the load RL (no longer through the body diode high-impedance channel of the NMOS tube V1). The drain-source channel of the NMOS tube V1 has a small conduction impedance, that is, the conduction loss is smaller than that of the diode, which reduces power loss and improves power utilization efficiency.

[0056] When the external voltage Vout=VCC2 is greater than the internal power supply VCC (Vout>VCC), the voltage VC>VA, and the NPN tube V3 is more completely turned on than the NPN tube V2 (the drain-source channel conduction impedance of the V3 tube is V3R CE Compared with the drain-source channel conduction impedance V2R of V2 tube CE The conduction degree depends on the base voltage), that is, the voltage U->U+, the differential signal U-, U+ output by the differential amplifier is transmitted to the voltage comparator U1, and the voltage comparator U1 outputs a low level, that is, V1G≈0V. When V1 GS =V1G-VCC≈-VCC<V TN , the drain-source channel of the NMOS tube V1 is cut off, the power supply VCC is isolated from the external voltage Vout, and the current of the external power supply (other power supplies connected in parallel with the voltage Vout) cannot flow back into the power supply VCC, thereby achieving the purpose of protecting the power supply VCC1.

[0057] Furthermore, the voltage comparator has a voltage comparator with a hysteresis loop transmission characteristic (also known as a Schmitt trigger). The threshold voltage of this voltage comparator changes with the change of the output voltage, and the anti-interference ability is improved. The hysteresis voltage comparator has a hysteresis characteristic, that is, inertia, and thus has a certain anti-interference ability. The stronger the anti-interference ability, the worse the sensitivity. The hysteresis voltage comparator circuit has two threshold voltages. The input voltage VCC causes the output voltage Vout to jump in the process of gradually increasing the threshold voltage VT1, and the input voltage VCC causes the output voltage Vout to jump in the process of gradually decreasing the threshold voltage VT2. VT1≠VT2, and the circuit has a hysteresis characteristic. The similarity with the single-limit voltage comparator is that when the input voltage changes in a single direction, the output voltage Vout only jumps once.

[0058] Furthermore, the NMOS tube V1 can use NMOS tubes with different conduction currents. For high-power power control, the NMOS tube can select the conduction resistance R between the drain and the source. DS(ON) A power tube device with a current of several milliohms and a large current passing through it has a small conduction voltage drop when passing a large current, that is, it has a very low forward voltage and can be approximated as an ideal diode.

[0059] Implementation Method 2

[0060] Circuit such as Figure 2 As shown, the circuit structure is basically the same as that of Implementation Method 1, except that: Implementation Method 1 uses an NPN pair of tubes for the differential amplifier circuit, and Implementation Method 2 uses an NMOS pair of tubes to replace the NPN pair of tubes V2 and V3, wherein R2=R3, R4=R5, and the resistance values ​​of R2 and R4 are in the order of megohms, belonging to a common source circuit. The specific working principle is basically the same as that of Implementation Method 1, see Implementation Method 1 for details, and no further description is given.

[0061] Implementation Method 3

[0062] An NMOS type high-side ideal diode based on a differential amplifier, the circuit is as follows Figure 3 As shown, it includes NMOS main body V1, differential amplifier, voltage comparator U1, bias power supply VBIAS, etc. The differential amplifier is composed of PNP pair tubes V2 and V3, resistors R1~R5, etc., which belongs to a common emitter circuit, wherein R2=R3, R4=R5. The two bases of the PNP pair tubes V2 and V3 are used as dual input ports to detect the source and drain voltages of the NMOS main body V1 respectively. After the amplification of the PNP pair tubes V2 and V3 of the differential amplifier, the two collectors of the V2 tube and the V3 tube are used as dual output ports to output differential signals U- and U+ respectively. U- and U+ are connected to the inverting terminal and the non-inverting terminal of the voltage comparator U1 respectively. The output signal V1G of the voltage comparator U1 controls the conduction and cutoff of the NMOS main body V1. The specific working principle is as follows.

[0063] When the DC power supply VCC=VCC1 is powered on (forward conduction), the current output by VCC first passes through the body diode of NMOS tube V1 (Vout=VCC-V F , V F =The diode conduction voltage drop), when the output current gradually increases, the internal power supply VCC is higher than the external voltage Vout (VCC>Vout), that is, the voltage VA>VC, the PNP tube V3 is more thoroughly turned on than the PNP tube V2 (the drain-source channel conduction impedance of the V3 tube is V3R CE Compared with the drain-source channel conduction impedance V2R of V2 tube CE The conduction degree depends on the difference between the bias power supply VBIAS and the base voltage), which means that the voltage U+>U-. The differential signals U- and U+ output by the differential amplifier are transmitted to the voltage comparator U1. The voltage comparator U1 outputs a high level, that is, V1G≈VBIAS. When V1 GS =V1G-VCC>V TN , the drain-source channel of the NMOS tube V1 is turned on, and the VCC current passes through the drain-source low-impedance channel of the NMOS tube V1 to the load RL (no longer passes through the body diode high-impedance channel of the NMOS tube V1). The drain-source channel of the NMOS tube V1 has a small conduction impedance, that is, the conduction loss is less than that of the diode, which reduces power loss and improves power utilization efficiency.

[0064] When the external voltage Vout = VCC2 is greater than the internal power supply VCC (Vout>VCC), the voltage VC>VA, and the PNP tube V2 is more completely turned on than the PNP tube V3 (the drain-source channel conduction impedance of the V2 tube is V2R CE Lower, V3R CE >V2R CE The conduction degree depends on the difference between the bias power supply VBIAS and the base voltage), that is, the voltage U->U+. The differential signals U- and U+ output by the differential amplifier are transmitted to the voltage comparator U1. The voltage comparator U1 outputs a low level, that is, V1G≈0V. When V1 GS =V1G-VCC≈-VCC<V TN , the drain-source channel of the NMOS tube V1 is cut off, the power supply VCC is isolated from the external voltage Vout, and the current of the external power supply (other power supplies connected in parallel with the voltage Vout) cannot flow back into the power supply VCC, thereby achieving the purpose of protecting the power supply VCC1.

[0065] Implementation Method 4

[0066] Circuit such as Figure 4As shown, the circuit structure is basically the same as that of the third embodiment, except that the third embodiment uses a PNP pair of transistors, while the fourth embodiment uses a PMOS pair of transistors to replace the PNP pair of transistors, which is a common source circuit, wherein R2 = R3, R4 = R5, and the resistance values ​​of R2 and R4 are in the order of megohms. The specific working principle is basically the same as that of the third embodiment, see the third embodiment for details, and will not be repeated here.

[0067] according to Figure 1 to Figure 4 The circuit schematic is simulated and tested using the National Instruments simulation software Multisim (version V14.0). The voltage comparator is LMC7211AIM5, a rail-to-rail op amp, and the output stage uses push-pull amplification to achieve an approximate full swing. The PMOS tube is NVTFS5124PLTAG from ON Semiconductor, with a minimum on-threshold voltage V TP(MIN) =-1.5V, maximum value V TP(MAX) =-2.5V, typical value V not given TP , the on-state current can reach -6A, and the on-state impedance R DS(ON) =0.26Ω(V GS =-10V), R DS(ON) =0.38Ω(V GS =-4.5V). The NMOS tube is made by NXP, model 2N7002E, and the minimum on-state voltage is V TN(MIN) =1V, maximum value V TN(MAX) =2.8V, typical value V is not given TN , conduction current I D 10A / 30V, on-resistance R DS(ON) ≤0.03Ω(V GS =10V), R DS(ON) ≤0.05Ω(V GS =4.5V); the NPN tube is from Generic Company, model 2N2222A; the PNP tube is from Generic Company, model 2N2905; the load resistance RL=10Ω, the specific simulation test is as follows.

[0068] Implementation Method 1 Simulation

[0069] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = 10kΩ, R4 = R5 = 100kΩ, VBIAS = 20V, VCC = VCC1 = 12V (switch J1 is closed), such as Figure 5As shown, when forward conducting, the output voltage Vout of the NMOS main tube V1 is ≈12.0V; the base current of the NPN auxiliary tube V2 is 4.66μA (detection point PR6), and the base voltage VA=11.5V (PR2, measured by the multimeter is 11.533V), so it can be considered that the NPN auxiliary tube V2 is turned on; the base current of the NPN auxiliary tube V3 is 4.42μA (PR8), and the base voltage VC=11.5V (PR1, measured by the multimeter is 11.531V), so it can be considered that the NPN auxiliary tube V3 is turned on, and the NPN tube V2 is turned on more thoroughly than the NPN tube V3; U+=14.7V (PR10), U-=14.5V (PR9), that is, U+>U-, the voltage comparator U1 outputs a high level, that is, V1G=VBIAS=20.0V (PR4), V1 GS =V1G-VCC≈20V-12V=8V>V TN , the drain-source channel of NMOS V1 is turned on, and the on-state voltage drop is about 26.16mV (measured by a multimeter), which is lower than the on-state voltage drop of the diode V F =0.6V, the positive output current of the power supply is 1.20A, corresponding to the drain-source channel on-resistance R DS(ON) =26.16mV / 1.20A=21.8mΩ.

[0070] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 12.1V, Vout > VCC, voltage VC = 11.6V (test point PR1, multimeter measured voltage 11.593V), VA = 11.6V (test point PR2, multimeter measured voltage 11.586V), U- = 15.0V, U+ = 14.1V, that is, voltage U->U+, NPN tube V3 is more thoroughly turned on than NPN tube V2, voltage comparator U1 outputs a low level, that is, V1G≈4.76mV, V1 GS =V1G-VCC≈-12V<V TN , the drain-source channel of NMOS tube V1 is cut off, such as Figure 6 As shown, the output current of the power supply VCC1 is 4.09μA, which is used to bias the V2 tube. The backflow current of the VCC2 output (node ​​VCC current: 4.09μA-4.13μA=-0.04μA=-40nA) to the power supply VCC1 can be ignored. It can be considered that VCC1 is isolated from the external voltage Vout, thereby achieving the purpose of protecting the power supply VCC1.

[0071] For different current usage scenarios, the resistance value of the load resistor RL is changed, and the simulation test results are shown in Table 1.

[0072] Table 1 Load current simulation test

[0073]

[0074] According to the load current simulation test in Table 1, it can be seen that R1=R2=R3=R4=R5=10kΩ, and this set of parameters has a better magnification: load RL=12kΩ, load current is 1mA, and the conduction voltage drop V1 of NMOS V1 SD =21.933μV (corresponding on-resistance R DS(ON) =21.933mΩ), which is in line with the data sheet parameters. After the differential amplifier amplifies the output U+ and U-, the difference is 1.198mV. The differential amplifier amplification factor is Au = 1.198mV / 21.933μV = 54.62. The other two sets of parameters are amplified by less than 10 times. The typical offset voltage of the voltage comparator chip LMC7211AIM5 is VIO = 3mV. If there is no differential amplifier, the drain-source conduction current I of the NMOS V1 that allows the LMC7211AIM5 to work properly is D =VIO / R DS(ON) =3mV / 21.933mΩ=0.1367A=136.7mA; if a differential amplifier is used, the corresponding on-state current I D =0.1367A / 54.62=2.5mA. Theoretically, the on-current is greater than 2.5mA, which can reach the offset voltage of LMC7211AIM5. The combined use of the differential amplifier and the voltage comparator reduces the response time as the driving voltage increases.

[0075] Implementation Method 2 Simulation

[0076] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = 10kΩ, R4 = R5 = 100kΩ, VBIAS = 20V, VCC = VCC1 = 12V (switch J1 is closed), such as Figure 7 As shown, when forward conducting, the output voltage Vout of the NMOS supervisor V1 is ≈12.0V; the voltage VA≈VC≈12.0V (measured by the multimeter: VA=11.999V, VC=11.973V), U+=15.6V, U-=14.5V, that is, U+>U-, the voltage comparator U1 outputs a high level, that is, V1G=VBIAS=20.0V(PR4), V1 GS =V1G-VCC≈20V-12V=8V>V TN , the drain-source channel of NMOS V1 is turned on, and the on-state voltage drop is about 26.159mV (measured by a multimeter), which is lower than the on-state voltage drop of the diode V F =0.6V, the positive output current of the power supply is 1.20A, corresponding to the drain-source channel on-resistance R DS(ON) =26.159mV / 1.20A=21.8mΩ.

[0077] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 12.1V, Vout > VCC, voltage VA = 12.0V, VC = 12.1V, U+ = 13.2V, U- = 16.9V, that is, U- > U+, voltage comparator U1 outputs a low level, that is, V1G = 4.76mV (PR4), V1 GS =V1G-VCC≈-12V<V TN , the drain-source channel of NMOS V1 is cut off, such as Figure 8 As shown, the output current of the power supply VCC1 is 0A, and the backflow current (node ​​VCC current: 0A-1.38nA=-1.38nA) output by VCC2 to the power supply VCC1 can be ignored. It can be considered that VCC1 is isolated from the external voltage Vout, thereby achieving the purpose of protecting the power supply VCC1.

[0078] Implementation Method 3 Simulation

[0079] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = 10kΩ, R4 = R5 = 100kΩ, VBIAS = 20V, VCC = VCC1 = 12V (switch J1 is closed), such as Fig. 9 As shown, when forward conducting, the output voltage Vout of the NMOS supervisor V1 is ≈12.0V; the voltage VA≈VC=12.3V (measured by the multimeter: VA=12.293V, VC=12.29V), U+=3.66V, U-=3.39V, that is, U+>U-, and the voltage comparator U1 outputs a high level, that is, V1G=VBIAS=20.0V(PR4), V1 GS =V1G-VCC≈20V-12V=8V>V TN , the drain-source channel of NMOS V1 is turned on, and the on-state voltage drop is about 26.159mV (measured by a multimeter), which is lower than the on-state voltage drop of the diode V F =0.6V, the positive output current of the power supply is 1.20A, corresponding to the drain-source channel on-resistance R DS(ON) =26.159mV / 1.20A=21.8mΩ.

[0080] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 12.1V, Vout > VCC, voltage VA = 12.3V, VC = 12.4V, U+ = 2.98V, U- = 4.01V, that is, U- > U+, voltage comparator U1 outputs a low level, that is, V1G = 4.76mV (PR4), V1 GS =V1G-VCC≈-12V<V TN , the drain-source channel of NMOS V1 is cut off, such as Fig.10As shown, the bias power supply VBIAS outputs a bias current of 3.48μA to the power supply VCC1, and VCC2 outputs a reverse current (node ​​VCC current: 3.55μA-3.48μA=-0.07μA=-70nA) to the power supply VCC1, which can be ignored. It can be considered that VCC1 is isolated from the external voltage Vout, thereby achieving the purpose of protecting the power supply VCC1.

[0081] Implementation Method 4 Simulation

[0082] DC power supply forward conduction simulation test: Set R1 = R2 = R3 = 10kΩ, R4 = R5 = 100kΩ, VBIAS = 20V, VCC = VCC1 = 12V (switch J1 is closed), such as Fig.11 As shown, when forward conducting, the output voltage Vout of the NMOS supervisor V1 is ≈ 12.0V; the voltage VA ≈ VC = 12.0V (measured by the multimeter: VA = -99.992mV, VC = -2.42μV), U+ = 7.02V, U- = 1.05mV, that is, U+>U-, and the voltage comparator U1 outputs a high level, that is, V1G = VBIAS = 20.0V (PR4), V1 GS =V1G-VCC≈20V-12V=8V>V TN , the drain-source channel of NMOS V1 is turned on, and the on-state voltage drop is about 26.159mV, which is lower than the on-state voltage drop of the diode V F =0.6V, the positive output current of the power supply is 1.20A, corresponding to the drain-source channel on-resistance R DS(ON) =26.159mV / 1.20A=21.8mΩ.

[0083] DC power supply reverse cutoff simulation test: After switch J1 is closed, switch J2 is also closed, that is, Vout = VCC2 = 12.1V, Vout > VCC, voltage VA = 12.0V, VC = 12.1V, U+ = 1.05mV, U- = 6.99V, that is, U- > U+, voltage comparator U1 outputs a low level, that is, V1G = 4.76mV (PR4), V1 GS =V1G-VCC≈-12V<V TN , the drain-source channel of NMOS V1 is cut off, such as Fig.12 As shown, the output current of the power supply VCC1 is 0A, and the backflow current (node ​​VCC current: 0A-24pA=-24pA) output by VCC2 to the power supply VCC1 can be ignored. It can be considered that VCC1 is isolated from the external voltage Vout, thereby achieving the purpose of protecting the power supply VCC1.

[0084] The beneficial effects of the present invention are as follows: under the same conditions, the voltage drop of the main tube of the high-end ideal diode, which is a PMOS tube, is about 0.3V, which is suitable for occasions with small working current; while the voltage drop of the main tube, which is an NMOS tube, can be as low as tens of millivolts, which is suitable for occasions with large working current. Due to the dual amplification of the differential amplifier and the voltage comparator, it is suitable for use in occasions with a wide current range. The circuit has a backflow prevention function, which can protect the previous stage circuit; it has low loss and small static current loss; the circuit is simple, the cost is very low, and the practicability is strong.

[0085] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. An NMOS type high-end ideal diode based on a differential amplifier, characterized in that: The circuit includes an NMOS main circuit V1, a differential amplifier circuit, a voltage comparator U1 and a bias power supply VBIAS; The dual input ports of the differential amplifier circuit are respectively connected to the drain and source of the NMOS supervisor V1 and compare the voltages. The dual input ends of the voltage comparator U1 receive the output information of the differential amplifier circuit, and the output end is connected to the gate of the NMOS supervisor V1 to control the conduction or cutoff of the NMOS supervisor V1.

2. The NMOS type high-end ideal diode based on a differential amplifier according to claim 1, characterized in that: The differential amplifier circuit includes a transistor pair and a peripheral circuit; The transistor pair includes any one of an NPN pair, an NMOS pair, a PNP pair, and a PMOS pair.

3. The NMOS type high-end ideal diode based on a differential amplifier according to claim 2, characterized in that: The transistor pair is NPN auxiliary tubes V2 and V3, and the peripheral circuit includes resistors R1 to R5, wherein resistor R2 = R3, and resistor R4 = R5; The bases of the NPN auxiliary tubes V2 and V3 are connected to the source and drain of the NMOS main tube V1 through resistors R4 and R5 respectively as dual input ports of the differential amplifier circuit; The collectors of the NPN auxiliary tubes V2 and V3 are connected to the inverting end and the non-inverting end of the voltage comparator respectively as the dual output ports of the differential amplifier circuit. The collectors of the NPN auxiliary tubes V2 and V3 are also connected to the bias power supply VBIAS through resistors R2 and R3 respectively, and the emitters are connected to each other and grounded through resistor R1.

4. The NMOS type high-end ideal diode based on a differential amplifier according to claim 2, characterized in that: The transistor pair is NMOS auxiliary transistors V2 and V3, and the peripheral circuit includes resistors R1 to R5, wherein resistor R2 = R3 and resistor R4 = R5; The gates of the NMOS auxiliary tubes V2 and V3 are connected to the source and drain of the NMOS main tube V1 through resistors R4 and R5 respectively as dual input ports of the differential amplifier circuit; The drains of the NMOS auxiliary tubes V2 and V3 are connected to the inverting end and the non-inverting end of the voltage comparator respectively as the dual output ports of the differential amplifier circuit. The drains of the NMOS auxiliary tubes V2 and V3 are also connected to the bias power supply VBIAS through resistors R2 and R3 respectively, and the sources are connected to each other and grounded through resistor R1.

5. The NMOS type high-side ideal diode based on a differential amplifier according to claim 2, characterized in that: The transistor pair is a PNP auxiliary tube V2, V3, and the peripheral circuit includes resistors R1 to R5, wherein resistor R2 = R3, and resistor R4 = R5; The bases of the PNP auxiliary tubes V2 and V3 are connected to the source and drain of the NMOS main tube V1 through resistors R4 and R5 respectively as dual input ports of the differential amplifier circuit; The collectors of the PNP auxiliary tubes V2 and V3 are connected to the inverting terminal and the non-inverting terminal of the voltage comparator respectively as the dual output ports of the differential amplifier circuit, and are also grounded through the resistors R2 and R3; The emitters of the PNP auxiliary tubes V2 and V3 are connected to the bias power supply VBIAS through the resistor R1.

6. The NMOS type high-side ideal diode based on a differential amplifier according to claim 2, characterized in that: The transistor pair is a PMOS auxiliary transistor V2, V3, and the peripheral circuit includes resistors R1 to R5, wherein resistor R2 = R3, and resistor R4 = R5; The gates of the PMOS auxiliary tubes V2 and V3 are connected to the source and drain of the NMOS main tube V1 through resistors R4 and R5 respectively as dual input ports of the differential amplifier circuit; The drains of the PMOS auxiliary tubes V2 and V3 are connected to the inverting terminal and the non-inverting terminal of the voltage comparator respectively as the dual output ports of the differential amplifier circuit, and are also grounded through the resistors R2 and R3; The sources of the PMOS auxiliary tubes V2 and V3 are connected to the bias power supply VBIAS through the resistor R1.

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