28Gbps Serial Interface Signal Compensation Circuit Embedded in Anti-Irradiation FPGA

Abstract

The present invention provides a signal compensation circuit for a 28 Gbps serial interface embedded in an anti-radiation FPGA, mainly solving the problem of high bit error rate in data transmission of anti-radiation FPGA devices. The solution of the present invention is as follows: The main path signal circuit performs impedance matching and common-mode terminal voltage processing on the high-frequency attenuation signal according to the control signal of the first anti-radiation configuration circuit to obtain the main path output signal, and inputs the main path output signal into the first signal superposition circuit and the second signal superposition circuit respectively; The equalization signal circuit performs equalization processing on the high-frequency attenuation signal according to the control signal of the second anti-radiation configuration circuit to obtain the equalization signal, and inputs the equalization signal into the first signal superposition circuit; The first signal superposition circuit superimposes the main path output signal and the equalization signal according to the control signal of the anti-radiation auxiliary circuit to obtain the superimposed signal, thereby realizing the compensation processing of the data signal, avoiding problems such as compensation degree limitation, power supply voltage limitation, and power supply noise limitation, and further reducing the bit error.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a signal compensation circuit for a 28 Gbps serial interface embedded in an anti-radiation FPGA. Background Art

[0002] With the increasing requirements for the data transmission performance of anti-radiation FPGA devices in the field of modern satellite communication, the single-channel rate requirement of its embedded high-speed serial interface has reached the gigabit per second level. When the signal transmission reaches the gigabit rate, the signal integrity problem becomes more and more obvious. Since the frequency characteristic of the signal transmission link shows a low-pass characteristic, the high-frequency components of the signal will be greatly attenuated when passing from the system sending end through the transmission cable to the receiving end. In the time domain, it is manifested as signal distortion, slow rising and falling edges, and signal amplitude decrease. If the high-frequency components of the signal are not compensated, the clock data recovery circuit at the receiving end will generate error codes due to insufficient sampling and holding time when receiving the signal.

[0003] Therefore, in the prior art, pre-compensation processing is added at the sending end of the high-speed serial interface, including two methods: (1) increasing the amplitude of the high-frequency components of the signal, that is, increasing the signal amplitude at the rising and falling edges by a certain proportion; (2) decreasing the amplitude of the low-frequency components of the signal, that is, decreasing the signal amplitude outside the rising and falling edges by a certain proportion. When the high-frequency attenuation occurs during cable transmission, the amplitudes of the low-frequency and high-frequency components tend to be smooth at this time, and then the low-frequency and high-frequency components of the signal are amplified together at the receiving end. The above solutions only add pre-compensation processing methods at the sending end, but there are still the following problems: (1) Different materials and lengths of the transmission cable result in different signal attenuations, so it is difficult to determine the compensation degree; (2) If the method of increasing the amplitude is adopted, it will be limited by the power supply voltage; (3) If the method of decreasing the amplitude is adopted, it will be limited by the power supply noise. In addition, when the signal amplitude becomes low and then attenuates through the transmission cable, it will further increase the pressure for the receiving end to identify the signal; these problems will lead to an increase in the error rate. Summary of the Invention

[0004] In order to overcome the deficiencies of the prior art and reduce the error rate of data transmission of anti-radiation FPGA devices, the present invention provides a signal compensation circuit for a 28 Gbps serial interface embedded in an anti-radiation FPGA. The present invention can superimpose and amplify the signals processed by the main path signal circuit and the equalization signal circuit for the original high-frequency attenuated signal, thereby realizing the compensation processing of the data signal, avoiding the problems such as compensation degree limitation, power supply voltage limitation, and power supply noise limitation caused by only pre-compensating at the sending end in the prior art. Therefore, a better signal compensation effect can be achieved, and it has anti-radiation ability, avoiding single event effects, and ensuring the reliability of signal transmission.

[0005] The anti-radiation FPGA is embedded with a 28Gbps serial interface signal compensation circuit, which includes a data receiving end, a main path signal circuit, an equalization signal circuit, a first signal superposition circuit, a first anti-radiation configuration circuit, a second anti-radiation configuration circuit, and an anti-radiation auxiliary circuit; the data receiving end includes a first receiving output end RX1 and a second receiving output end RX2;

[0006] The first anti-radiation configuration circuit is used to strengthen storage and output the control signal of the equalization signal circuit; the second anti-radiation configuration circuit is used to strengthen storage and output the control signal of the main path signal circuit; the anti-radiation auxiliary circuit is used to strengthen storage and output the control signal of the signal superposition circuit; the output end of the first anti-radiation configuration circuit is the first control signal CS1; the output end of the second anti-radiation configuration circuit is the second control signal CS2; the anti-radiation auxiliary circuit includes a first control signal output end EN1, a second control signal output end EN2, a first reference current output end B1, and a second reference current output end B2;

[0007] The main path signal circuit performs impedance matching and common-mode terminal voltage processing on the high-frequency attenuation signal according to the control signal of the first anti-radiation configuration circuit to obtain a main path output signal, and inputs the main path output signal into the first signal superposition circuit;

[0008] The equalization signal circuit performs equalization processing on the high-frequency attenuation signal according to the control signal of the second anti-radiation configuration circuit to obtain an equalization signal, and inputs the equalization signal into the first signal superposition circuit;

[0009] The first signal superposition circuit superimposes the main path output signal and the equalization signal according to the control signal of the anti-radiation auxiliary circuit to obtain a superimposed signal; then connects the superimposed signal to the data recognition end and the edge recognition end respectively.

[0010] Further, the radiation-resistant FPGA embedded with a 28Gbps serial interface signal compensation circuit includes a second signal superposition circuit; the second signal superposition circuit superimposes the main path output signal and the equalization signal according to the control signal of the radiation-resistant auxiliary circuit to obtain a superimposed signal; the first signal superposition circuit has the same structure as the second signal superposition circuit; the input of the second signal superposition circuit 107 includes a ninth input terminal VI9, a tenth input terminal VI10, an eleventh input terminal VI11, a twelfth input terminal VI12, a second reference current input terminal I2, and a second superposition control signal input terminal S2; the ninth input terminal VI9 is connected to the first output terminal VO1; the tenth input terminal VI10 is connected to the second output terminal VO2; the eleventh input terminal VI11 is connected to the third output terminal VO3; the twelfth input terminal VI12 is connected to the fourth output terminal VO4; the second superposition control signal input terminal S2 is connected to the second control signal output terminal EN2; the second reference current input terminal I2 is connected to the second reference current output terminal B2; the second superposition control signal input terminal S2 is a 12-bit control signal, and the second superposition control signal input terminal S2 includes 12 input terminals and 12 output terminals, and the input terminals and output terminals correspond one by one; the output of the second signal superposition circuit 107 is a seventh output terminal VO7 and an eighth output terminal VO8; the fifth output terminal VO5, the sixth output terminal VO6, the seventh output terminal VO7, and the eighth output terminal VO8 are sequentially connected to the input terminal of the data delay processing circuit; the data delay processing circuit delays the superimposed signals output by the first signal superposition circuit and the second signal superposition circuit, and inputs the delayed superimposed signals into the data recognition terminal and the edge recognition terminal respectively; the input of the data delay processing circuit includes a thirteenth input terminal VI13, a fourteenth input terminal VI14, a fifteenth input terminal VI15, and a sixteenth input terminal VI16; the output of the data delay processing circuit is a ninth output terminal VO9 and a tenth output terminal VO10; the ninth output terminal VO9 is connected to the data recognition terminal; the tenth output terminal VO10 is connected to the edge recognition terminal.

[0011] Further, the input terminals of the main path signal circuit 104 include a third input terminal VI3, a fourth input terminal VI4, and a main path control input terminal SC; the main path control input terminal SC is a digital switch; the main path control input terminal SC includes seven input terminals and seven output terminals, and the input terminals and output terminals correspond one by one; the main path control input terminal SC is connected to the second control signal CS2; the output terminals of the main path signal circuit 104 include a third output terminal VO3 and a fourth output terminal VO4; the first receive output terminal RX1 is connected to the third input terminal VI3; the second receive output terminal RX2 is connected to the fourth input terminal VI4; the third output terminal VO3 is connected to the seventh input terminal VI7; the fourth output terminal VO4 is connected to the eighth input terminal VI8;

[0012] The main path signal circuit 104 includes a first impedance matching resistor array, a second impedance matching resistor array, a first coupling capacitor 204, a second coupling capacitor 205, and a common-mode voltage circuit;

[0013] The first coupling capacitor 204 includes a first capacitor C1 and a sixth terminal SC<5> of the main path control input terminal SC; the first capacitor C1 is connected in parallel with the sixth terminal SC<5> of the main path control input terminal SC;

[0014] The second coupling capacitor 205 includes a second capacitor C2 and a sixth terminal SC<6> of the main path control input terminal SC; the second capacitor C2 is connected in parallel with the sixth terminal SC<6> of the main path control input terminal SC;

[0015] The first impedance matching resistor array R1 includes five resistors connected in parallel; each resistor is connected in series with a pair of input and output terminals of the main path control input terminal SC; the five resistors are respectively connected in series with the first to fifth terminals of the main path control input terminal SC in sequence; the second impedance matching resistor array R2 is the same as the first impedance matching resistor array R1;

[0016] The third input terminal VI3 of the main path signal circuit 104 is connected to the input terminal of the first impedance matching resistor array; the third input terminal VI3 of the main path signal circuit 104 is connected to one end of the first coupling capacitor 204; the other end of the first coupling capacitor 204 is connected to the third output terminal VO3;

[0017] The fourth input terminal VI4 of the main path signal circuit 104 is connected to the input terminal of the second impedance matching resistor array; the fourth input terminal VI4 of the main path signal circuit 104 is connected to one end of the second coupling capacitor 205; the other end of the second coupling capacitor 205 is connected to the fourth output terminal VO4;

[0018] The output terminals of the first impedance matching resistor array and the second impedance matching resistor array are connected to the input terminal of the common-mode voltage circuit 203; the output terminal of the common-mode voltage circuit 203 is grounded;

[0019] Furthermore, the common-mode voltage circuit 203 is used to adjust the common-mode terminal voltage of the main path signal circuit signal;

[0020] The common-mode voltage circuit includes a first common-mode digital switch, a second common-mode digital switch, and a third common-mode digital switch; the input end of the common-mode voltage circuit is respectively connected to the input ends of the first common-mode digital switch, the second common-mode digital switch, and the third common-mode digital switch; the output end of the first common-mode digital switch is connected to a 1.2V voltage; the output end of the second common-mode digital switch is connected to a 0.8V voltage; the output end of the third common-mode digital switch is connected to the ground; in the DC coupling scenario, the common-mode voltage circuit outputs and selects a 1.2V voltage mode or a ground mode; in the AC coupling scenario, the common-mode voltage circuit outputs and selects to connect to a 0.8V voltage mode.

[0021] Furthermore, the input end of the equalization signal circuit 105 includes a first input end VI1, a second input end VI2, and an equalization control input end EC; the equalization control input end EC is a digital switch; the equalization control input end EC includes sixteen input ends and sixteen output ends, and the input ends and the output ends correspond one by one; the equalization control input end EC is connected to a first control signal CS1; the output end of the equalization signal circuit 105 includes a first output end VO1 and a second output end VO2;

[0022] The equalization signal circuit 105 includes a first resistor array 302, a second resistor array 303, a third resistor array 305, a fourth resistor array 306, a first input capacitor C3, and a second input capacitor C4; the first input terminal VI1 of the equalization signal circuit 105 is connected to the input terminal of the first input capacitor C3; the output terminal of the first input capacitor C3 is respectively connected to the input terminals of the first resistor array, the second resistor array, and the first output terminal VO1; the second input terminal VI2 of the equalization signal circuit 105 is connected to the input terminal of the second input capacitor C4; the output terminal of the second input capacitor C4 is respectively connected to the input terminals of the third resistor array, the fourth resistor array, and the second output terminal VO2 of the equalization signal circuit; the input terminal of the first resistor array 302 is connected to the input terminals of the seventh resistor R7 and the eighth resistor R8 connected in parallel; the output terminals of the seventh resistor R7 and the eighth resistor R8 connected in parallel are connected to the input terminal of the fifth resistor R5; the output terminal of the fifth resistor R5 is connected to the drain of the PMOS switch tube MP3; the third output terminal EC<2> of the equalization control input terminal EC is connected to the gate of the PMOS tube MP3; the output terminals of the seventh resistor R7 and the eighth resistor R8 connected in parallel are connected to the input terminal of the sixth resistor R6; the output terminal of the sixth resistor R6 is connected to the drain of the PMOS switch tube MP4; the fourth output terminal EC<3> of the equalization control input terminal EC is connected to the gate of the PMOS tube MP4; the source of the PMOS switch tube MP4 is connected to the source of the PMOS tube MP3; the sources of the PMOS switch tube MP4 and the PMOS tube MP3 are respectively connected to the drain of the PMOS switch tube MP2; the sources of the PMOS switch tube MP4 and the PMOS tube MP3 are respectively connected to the input terminal of the fourth resistor R4; the gate of the PMOS switch tube MP2 is connected to the second output terminal EC<1> of the equalization control input terminal EC; the output terminal of the fourth resistor R4 is connected to the source of the PMOS switch tube MP2; the output terminal of the fourth resistor R4 and the source of the PMOS switch tube MP2 are respectively connected to the drain of the PMOS switch tube MP1; the output terminal of the fourth resistor R4 and the source of the PMOS switch tube MP2 are respectively connected to the input terminal of the third resistor R3; the gate of the PMOS switch tube MP1 is connected to the first output terminal EC<0> of the equalization control input terminal EC; the output terminal of the third resistor R3 is connected to the source of the PMOS switch tube MP1; the source of the PMOS switch tube MP1 is connected to the analog power supply terminal AVDD;

[0023] The input end of the second resistor array 303 is connected to the input ends of the ninth resistor R9 and the tenth resistor R10 in parallel; the output ends of the ninth resistor R9 and the tenth resistor R10 in parallel are connected to the input end of the eleventh resistor R11; the output end of the eleventh resistor R11 is connected to the drain of the NMOS switch tube MN3; the output ends of the ninth resistor R9 and the tenth resistor R10 in parallel are connected to the input end of the twelfth resistor R12; the output end of the twelfth resistor R12 is connected to the drain of the NMOS switch tube MN4; the source of the NMOS switch tube MN3 is connected to the source of the NMOS switch tube MN4; the gate of the NMOS switch tube MN3 is connected to the fifth output end EC<4> of the equalization control input terminal EC; the gate of the NMOS switch tube MN4 is connected to the eighth output end EC<7> of the equalization control input terminal EC; the source of the NMOS switch tube MN3 and the source of the NMOS switch tube MN4 are connected to the drain of the NMOS switch tube MN2; the source of the NMOS switch tube MN3 and the source of the NMOS switch tube MN4 are connected to the input end of the thirteenth resistor R13; the source of the NMOS switch tube MN2 is connected to the output end of the thirteenth resistor R13; the gate of the NMOS switch tube MN2 is connected to the sixth output end EC<5> of the equalization control input terminal EC; the source of the NMOS switch tube MN2 and the output end of the thirteenth resistor R13 are respectively connected to the drain of the NMOS switch tube MN1; the source of the NMOS switch tube MN2 and the output end of the thirteenth resistor R13 are respectively connected to the input end of the fourteenth resistor R14; the source of the NMOS switch tube MN1 is connected to the output end of the fourteenth resistor R14 and is grounded at the same time; the gate of the NMOS switch tube MN1 is connected to the seventh output end EC<6> of the equalization control input terminal EC; the input end of the third resistor array 305 is connected to the input ends of the nineteenth resistor R19 and the twentieth resistor R20 in parallel; the output ends of the nineteenth resistor R19 and the twentieth resistor R20 in parallel are connected to the input end of the seventeenth resistor R17; the output end of the seventeenth resistor R17 is connected to the drain of the PMOS switch tube MP7; the eleventh output end EC<10> of the equalization control input terminal EC is connected to the gate of the PMOS tube MP7; the output ends of the nineteenth resistor R19 and the twentieth resistor R20 in parallel are connected to the input end of the eighteenth resistor R18; the output end of the eighteenth resistor R18 is connected to the drain of the PMOS switch tube MP8; the twelfth output end EC<11> of the equalization control input terminal EC is connected to the gate of the PMOS tube MP8; the source of the PMOS switch tube MP7 is connected to the source of the PMOS switch tube MP8; the source of the PMOS switch tube MP7 and the source of the PMOS switch tube MP8 are respectively connected to the drain of the PMOS switch tube MP6; the source of the PMOS switch tube MP7 and the source of the PMOS switch tube MP8 are respectively connected to the input end of the sixteenth resistor R16; the gate of the PMOS switch tube MP6 is connected to the tenth output end EC<9> of the equalization control input terminal EC;The output terminal of the sixteenth resistor R16 is connected to the source of the PMOS switch transistor MP6; the output terminal of the sixteenth resistor R16 and the source of the PMOS switch transistor MP6 are respectively connected to the drain of the PMOS switch transistor MP5; the output terminal of the sixteenth resistor R16 and the source of the PMOS switch transistor MP6 are respectively connected to the input terminal of the fifteenth resistor R15; the gate of the PMOS switch transistor MP5 is connected to the ninth output terminal EC<8> of the equalization control input terminal EC; the output terminal of the fifteenth resistor R15 is connected to the source of the PMOS switch transistor MP5; the source of the PMOS switch transistor MP5 is connected to the analog power supply terminal AVDD; the input terminal of the fourth resistor array 306 is connected to the input terminals of the parallel-connected twenty-first resistor R21 and twenty-second resistor R22; the output terminals of the parallel-connected twenty-first resistor R21 and twenty-second resistor R22 are connected to the input terminal of the twenty-third resistor R23; the output terminal of the twenty-third resistor R23 is connected to the drain of the NMOS switch transistor MN7; the output terminals of the parallel-connected twenty-first resistor R21 and twenty-second resistor R22 are respectively connected to the input terminals of the twenty-fourth resistor R24; the output terminal of the twenty-fourth resistor R24 is connected to the drain of the NMOS switch transistor MN8; the source of the NMOS switch transistor MN7 is connected to the source of the NMOS switch transistor MN8; the gate of the NMOS switch transistor MN7 is connected to the thirteenth output terminal EC<12> of the equalization control input terminal EC; the gate of the NMOS switch transistor MN8 is connected to the sixteenth output terminal EC<15> of the equalization control input terminal EC; the source of the NMOS switch transistor MN7 and the source of the NMOS switch transistor MN8 are connected to the drain of the NMOS switch transistor MN6; the source of the NMOS switch transistor MN7 and the source of the NMOS switch transistor MN8 are connected to the input terminal of the twenty-fifth resistor R25; the source of the NMOS switch transistor MN6 is connected to the output terminal of the twenty-fifth resistor R25; the gate of the NMOS switch transistor MN6 is connected to the fourteenth output terminal EC<13> of the equalization control input terminal EC; the source of the NMOS switch transistor MN6 and the output terminal of the twenty-fifth resistor R25 are respectively connected to the drain of the NMOS switch transistor MN5; the source of the NMOS switch transistor MN6 and the output terminal of the twenty-fifth resistor R25 are respectively connected to the input terminal of the twenty-sixth resistor R26; the source of the NMOS switch transistor MN5 is connected to the output terminal of the twenty-sixth resistor R26 and is grounded at the same time; the gate of the NMOS switch transistor MN5 is connected to the fifteenth output terminal EC<14> of the equalization control input terminal EC.;

[0024] Further, the input end of the first signal superposition circuit includes a fifth input end VI5, a sixth input end VI6, a seventh input end VI7, an eighth input end VI8, a first reference current input end I1, and a first superposition control signal input end S1; the first superposition control signal input end S1 is connected to the first control signal output end EN1; the first reference current input end I1 is connected to the first reference current output end B1; the first superposition control signal input end S1 is a 12-bit control signal, and the first superposition control signal input end S1 includes 12 input ends and 12 output ends, and the input ends and the output ends correspond one by one; the output end of the first signal superposition circuit 106 includes a fifth output end VO5 and a sixth output end VO6; the fifth output end VO5 is connected to the data identification end; the sixth output end VO6 is connected to the edge identification end;

[0025] The first signal superposition circuit 106 includes an enable control circuit 401, a first input pair of transistors 404, a second input pair of transistors 405, a first current source array 402, a second current source array 403, a first load resistor array 406, and a second load resistor array 407;

[0026] The first input pair of transistors 404 includes an NMOS transistor MN11 and an NMOS transistor MN12; the fifth input end VI5 of the first signal superposition circuit 106 is connected to the gate of the NMOS transistor MN11; the sixth input end VI6 of the first signal superposition circuit 106 is connected to the gate of the NMOS transistor MN12; the source of the NMOS transistor MN11 and the source of the NMOS transistor MN12 are connected; the drain of the NMOS transistor MN11 is connected to the input end of the first load resistor array 406; the drain of the NMOS transistor MN12 is connected to the input end of the second load resistor array 407;

[0027] The second input pair of transistors 405 includes an NMOS transistor MN13 and an NMOS transistor MN14; the seventh input end VI7 of the first signal superposition circuit 106 is connected to the gate of the NMOS transistor MN13; the eighth input end VI8 of the first signal superposition circuit 106 is connected to the gate of the NMOS transistor MN14; the source of the NMOS transistor MN13 and the source of the NMOS transistor MN14 are connected; the drain of the NMOS transistor MN13 is connected to the input end of the first load resistor array 406; the drain of the NMOS transistor MN14 is connected to the input end of the second load resistor array 407;

[0028] The first load resistor array 406 includes a twenty-eighth resistor R28, a PMOS switch transistor MP9, a PMOS switch transistor MP10, and a twenty-seventh resistor R27; the input end of the first load resistor array 406 is simultaneously connected to the input end of the twenty-eighth resistor R28, the input end of the twenty-seventh resistor R27, and the fifth output end VO5; the output end of the twenty-eighth resistor R28 is connected to the drain of the PMOS switch transistor MP10; the source of the PMOS switch transistor MP10 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch transistor MP10 is connected to the second output terminal S1<1> of the first superimposed control signal input terminal S1; the output end of the twenty-seventh resistor R27 is connected to the drain of the PMOS switch transistor MP9; the source of the PMOS switch transistor MP9 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch transistor MP9 is connected to the first output terminal S1<0> of the first superimposed control signal input terminal S1;

[0029] The second load resistor array 407 includes a twenty-ninth resistor R29, a PMOS switch transistor MP11, a PMOS switch transistor MP12, and a thirtieth resistor R30; the input end of the second load resistor array 407 is simultaneously connected to the input end of the twenty-ninth resistor R29, the input end of the thirtieth resistor R30, and the sixth output end VO6; the output end of the twenty-ninth resistor R29 is connected to the drain of the PMOS switch transistor MP11; the source of the PMOS switch transistor MP11 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch transistor MP11 is connected to the second output terminal S1<1> of the first superimposed control signal input terminal S1; the output end of the thirtieth resistor R30 is connected to the drain of the PMOS switch transistor MP12; the source of the PMOS switch transistor MP12 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch transistor MP12 is connected to the first output terminal S1<0> of the first superimposed control signal input terminal S1;

[0030] The first current source array includes four NMOS transistors; the sources of the four NMOS transistors are grounded respectively; the gate of each NMOS transistor is connected in series with an output terminal of the first superimposed control signal input terminal S1; the gates of the four NMOS transistors are connected in series with the fifth to eighth output terminals of the first superimposed control signal input terminal S1 in sequence; the drains of the four NMOS transistors are connected in parallel and then connected to the source of the NMOS transistor MN11 and the source of the NMOS transistor MN12 respectively;

[0031] The second current source array includes four NMOS transistors; the sources of the four NMOS transistors are grounded respectively; the gate of each NMOS transistor is connected in series with an output terminal of the first superimposed control signal input terminal S1; the gates of the four NMOS transistors are sequentially connected in series with the ninth to twelfth output terminals of the first superimposed control signal input terminal S1; the drains of the four NMOS transistors are connected in parallel and then connected to the source of the NMOS transistor MN13 and the source of the NMOS transistor MN14 respectively;

[0032] The enabling control circuit includes an NMOS transistor MN9, an NMOS transistor MN10, and a PMOS switch transistor MP13; the first reference current input terminal I1 is connected to the drain of the NMOS transistor MN9 and the source of the PMOS switch transistor MP13 respectively; the source of the NMOS transistor MN9 is connected to the drain of the PMOS switch transistor MP13; the gate of the NMOS transistor MN9 is connected to the fourth input / output terminal S1<3> of the first superimposed control signal input terminal S1; the gate of the PMOS switch transistor MP13 is connected to the third input / output terminal S1<2> of the first superimposed control signal input terminal S1; the source of the NMOS transistor MN9 is connected to the drain of the NMOS transistor MN10; the source of the NMOS transistor MN10 is grounded; the gate of the NMOS transistor MN10 is connected to the third input / output terminal S1<2> of the first superimposed control signal input terminal S1; the source of the NMOS transistor MN9 is connected to the gates of the four NMOS transistors of the first current source array respectively; the source of the NMOS transistor MN9 is connected to the gates of the four NMOS transistors of the second current source array respectively.

[0033] The beneficial effects of the present invention are as follows: The signal compensation circuit proposed by the present invention can superimpose and amplify the signals processed by the main path signal circuit and the equalization signal circuit on the received end for the original high-frequency attenuated signals, so as to realize the compensation processing of data signals, avoiding problems such as compensation degree limitation, power supply voltage limitation, and power supply noise limitation caused by only pre-compensating at the sending end in the prior art. Therefore, better signal compensation effects can be achieved and the error code can be reduced. When the superimposed signals output by the signal superimposing circuit proposed by the present invention are divided into two or more transmission paths, the compensated signals are respectively subjected to delay processing and then transmitted to the data recognition end and the edge recognition end for clock and data recovery processing, which helps to achieve better signal fidelity and reduce the error code. Description of the Drawings

[0034] Figure 1 is a schematic diagram of a 28 Gbps serial interface signal compensation circuit embedded in an anti-radiation FPGA provided by an embodiment of the present invention;

[0035] Figure 2 is a schematic diagram of another 28 Gbps serial interface signal compensation circuit embedded in an anti-radiation FPGA provided by an embodiment of the present invention;

[0036] Figure 3 It is a schematic diagram of the main path signal circuit provided by an embodiment of the present invention;

[0037] Figure 4 It is a schematic diagram of the equalization signal circuit provided by an embodiment of the present invention;

[0038] Figure 5 It is a schematic diagram of the signal superposition circuit provided by an embodiment of the present invention;

[0039] In the figure, 101 - receiving end data path; 102 - first anti-radiation configuration circuit; 103 - second anti-radiation configuration circuit; 104 - main path signal circuit; 105 - equalization signal circuit; 106 - first signal superposition circuit; 107 - second signal superposition circuit; 108 - anti-radiation auxiliary circuit; 109 - data delay processing circuit;

[0040] 203 - common mode voltage circuit; 204 - first coupling capacitor; 205 - second coupling capacitor;

[0041] 302 - first resistor array; 303 - second resistor array; 305 - third resistor array; 306 - fourth resistor array;

[0042] 401 - enable control circuit; 402 - first current source array; 403 - second current source array; 404 - first input pair transistor; 405 - second input pair transistor; 406 - first load resistor array; 407 - second radiation resistance array;

[0043] RX1 - first receiving output terminal; RX2 - second receiving output terminal;

[0044] VI1 - first input terminal; VI2 - second input terminal; VI3 - third input terminal; VI4 - fourth input terminal; VI5 - fifth input terminal; VI6 - sixth input terminal; VI7 - seventh input terminal; VI8 - eighth input terminal; VI9 - ninth input terminal; VI10 - tenth input terminal; VI11 - eleventh input terminal; VI12 - twelfth input terminal; VI13 - thirteenth input terminal; VI14 - fourteenth input terminal; VI15 - fifteenth input terminal; VI16 - sixteenth input terminal;

[0045] VO1 - first output terminal; VO2 - second output terminal; VO3 - third output terminal; VO4 - fourth output terminal; VO5 - fifth output terminal; VO6 - sixth output terminal; VO7 - seventh output terminal; VO8 - eighth output terminal; VO9 - ninth output terminal; VO10 - tenth output terminal;

[0046] CS1 - First control signal; CS2 - Second control signal; EC - Equalization control input terminal; SC - Main path control input terminal; S1 - First superimposed control signal input terminal; S2 - Second superimposed control signal input terminal; I1 - First reference current input terminal; I2 - Second reference current input terminal; EN1 - First control signal output terminal; EN2 - Second control signal output terminal EN; B1 - First reference current output terminal; B2 - Second reference current output terminal;

[0047] C1 - First capacitor; C2 - Second capacitor; C3 - First input capacitor; C4 - Second input capacitor;

[0048] R1 - First impedance matching resistor array; R2 - Second impedance matching resistor array;

[0049] R3 - Third resistor; R4 - Fourth resistor; R5 - Fifth resistor; R6 - Sixth resistor; R7 - Seventh resistor; R8 - Eighth resistor; R9 - Ninth resistor; R10 - Tenth resistor; R11 - Eleventh resistor; R12 - Twelfth resistor; R13 - Thirteenth resistor; R14 - Fourteenth resistor; R15 - Fifteenth resistor; R16 - Sixteenth resistor; R17 - Seventeenth resistor; R18 - Eighteenth resistor; R19 - Nineteenth resistor; R20 - Twentieth resistor; R21 - Twenty - first resistor; R22 - Twenty - second resistor; R23 - Twenty - third resistor; R24 - Twenty - fourth resistor; R25 - Twenty - fifth resistor; R26 - Twenty - sixth resistor; R27 - Twenty - seventh resistor; R28 - Twenty - eighth resistor; R29 - Twenty - ninth resistor; R30 - Thirtieth resistor. Detailed implementation manner

[0050] The radiation - resistant FPGA embedded with a 28Gbps serial interface signal compensation circuit includes a data receiving end, a main path signal circuit, an equalization signal circuit, a first signal superimposing circuit, a second signal superimposing circuit, a first radiation - resistant configuration circuit, a second radiation - resistant configuration circuit, and a radiation - resistant auxiliary circuit;

[0051] The data receiving end includes a first receiving output end RX1 and a second receiving output end RX2; the input end of the equalization signal circuit 105 includes a first input end VI1, a second input end VI2 and an equalization control input end EC; the equalization control input end EC is a digital switch; the equalization control input end EC includes sixteen input ends and sixteen output ends, and the input ends and the output ends correspond one by one; the output end of the equalization signal circuit 105 includes a first output end VO1 and a second output end VO2; the input end of the main path signal circuit 104 includes a third input end VI3, a fourth input end VI4 and a main path control input end SC; the main path control input end SC is a digital switch; the main path control input end SC includes seven input ends and seven output ends, and the input ends and the output ends correspond one by one; the output end of the main path signal circuit 104 includes a third output end VO3 and a fourth output end VO4; both the first anti-radiation configuration circuit and the second anti-radiation configuration circuit include a digital buffer unit and a radiation-hardened storage unit, and have the ability to resist the influence of single-event effects; the output end of the first anti-radiation configuration circuit is a first control signal CS1; the output end of the second anti-radiation configuration circuit is a second control signal CS2; the anti-radiation auxiliary circuit includes a first control signal output end EN1, a second control signal output end EN2, a first reference current output end B1 and a second reference current output end B2; the anti-radiation auxiliary circuit is used to provide a reference current for the current source array in the signal superposition circuit, and harden the storage and output the control signals of the main path signal circuit / equalization signal circuit / signal superposition circuit; the input end of the first signal superposition circuit 106 includes a fifth input end VI5, a sixth input end VI6, a seventh input end VI7, an eighth input end VI8, a first reference current input end I1 and a first superposition control signal input end S1; the first superposition control signal input end S1 is a 12-bit control signal, and the first superposition control signal input end S1 includes twelve input ends and twelve output ends, and the input ends and the output ends correspond one by one; the output end of the first signal superposition circuit 106 includes a fifth output end VO5 and a sixth output end VO6; the first signal superposition circuit 106 has the same structure as the second signal superposition circuit 107; the input of the second signal superposition circuit 107 includes a ninth input end VI9, a tenth input end VI10, an eleventh input end VI11, a twelfth input end VI12, a second reference current input end I2 and a second superposition control signal input end S2; the second superposition control signal input end S2 is a 12-bit control signal, and the second superposition control signal input end S2 includes twelve input ends and twelve output ends, and the input ends and the output ends correspond one by one; the output of the second signal superposition circuit 107 is a seventh output end VO7 and an eighth output end VO8; the first receiving output end RX1 is respectively connected to the third input end VI3 of the main path signal circuit 104 and the first input end VI1 of the equalization signal circuit 105;The second receiving output terminal RX2 is respectively connected to the fourth input terminal VI4 of the main path signal circuit 104 and the second input terminal VI2 of the equalization signal circuit 105; the first control signal CS1 is connected to the equalization control input terminal EC of the equalization signal circuit 105; the second control signal CS2 is connected to the main path control input terminal SC of the main path signal circuit 104; the output terminal VO1 of the equalization signal circuit 105 is respectively connected to the fifth input terminal VI5 of the first signal superposition circuit 106 and the ninth input terminal VI9 of the second signal superposition circuit 107; the output terminal VO2 of the equalization signal circuit 105 is respectively connected to the sixth input terminal VI6 of the first signal superposition circuit 106 and the tenth input terminal VI10 of the second signal superposition circuit 107; the output terminal VO3 of the main path signal circuit 104 is respectively connected to the seventh input terminal VI7 of the first signal superposition circuit 106 and the eleventh input terminal VI11 of the second signal superposition circuit 107; the output terminal VO4 of the main path signal circuit 104 is respectively connected to the eighth input terminal VI8 of the first signal superposition circuit 106 and the twelfth input terminal VI12 of the second signal superposition circuit 107; the first control signal output terminal EN1 of the anti-radiation auxiliary circuit is connected to the first superposition control signal input terminal S1 of the first signal superposition circuit 106; the first reference current output terminal B1 of the anti-radiation auxiliary circuit is connected to the first reference current input terminal I1 of the first signal superposition circuit 106; the second control signal output terminal EN2 of the anti-radiation auxiliary circuit is connected to the second superposition control signal input terminal S2 of the second signal superposition circuit 107; the second reference current output terminal B2 of the anti-radiation auxiliary circuit is connected to the second reference current input terminal I2 of the second signal superposition circuit 107; the output terminal B1 is connected to the first reference current input terminal I1 of the first signal superposition circuit 106, and the output terminal of 106 includes a fifth output terminal VO5 and a sixth output terminal VO6 which are respectively connected to the data recognition terminal; the output of the second signal superposition circuit 107 is a seventh output terminal VO7 and an eighth output terminal VO8 which are respectively connected to the edge recognition terminal.;

[0052] When the transmission path of the superimposed signal includes at least two paths, a data delay processing circuit is added; the data delay processing circuit is used to perform delay processing on the superimposed signal, and input the delayed superimposed signal into the data identification terminal and the edge identification terminal of the clock data recovery circuit respectively; the inputs of the data delay processing circuit include a thirteenth input terminal VI13, a fourteenth input terminal VI14, a fifteenth input terminal VI15 and a sixteenth input terminal VI16; the outputs of the data delay processing circuit include a ninth output terminal VO9 and a tenth output terminal VO10; a fifth output terminal VO5 of the first signal superimposing circuit 106 is connected to the thirteenth input terminal VI13; a sixth output terminal VO6 of the first signal superimposing circuit 106 is connected to VI14; a seventh output terminal VO7 of the second signal superimposing circuit 106 is connected to VI15; an eighth output terminal VO8 of the second signal superimposing circuit 106 is connected to VI16; the ninth output terminal VO9 of the data delay processing circuit is connected to the data identification terminal; and a tenth output terminal VO10 of the data delay processing circuit is connected to the edge identification terminal.

[0053] The data receiving end receives the high-frequency attenuation signal, and transmits the signal to the equalization signal circuit and the main path signal circuit through a first receiving output terminal RX1 and a second receiving output terminal RX2 respectively;

[0054] The equalization signal circuit 105 includes a first resistor array 302, a second resistor array 303, a third resistor array 305, a fourth resistor array 306, a first input capacitor C3, and a second input capacitor C4; a first input terminal VI1 of the equalization signal circuit 105 is connected to an input terminal of the first input capacitor C3; an output terminal of the first input capacitor C3 is respectively connected to an input terminal of the first resistor array, an input terminal of the second resistor array, and a first output terminal VO1; a second input terminal VI2 of the equalization signal circuit 105 is connected to an input terminal of the second input capacitor C4; an output terminal of the second input capacitor C4 is respectively connected to an input terminal of the third resistor array, an input terminal of the fourth resistor array, and a second output terminal VO2 of the equalization signal circuit; an input terminal of the first resistor array 302 is connected to an input terminal of a parallel combination of a seventh resistor R7 and an eighth resistor R8; an output terminal of the parallel combination of the seventh resistor R7 and the eighth resistor R8 is connected to an input terminal of a fifth resistor R5; an output terminal of the fifth resistor R5 is connected to a drain of a PMOS switch tube MP3; a third output terminal EC<2> of an equalization control input terminal EC is connected to a gate of the PMOS tube MP3; an output terminal of the parallel combination of the seventh resistor R7 and the eighth resistor R8 is connected to an input terminal of a sixth resistor R6; an output terminal of the sixth resistor R6 is connected to a drain of a PMOS switch tube MP4; a fourth output terminal EC<3> of the equalization control input terminal EC is connected to a gate of the PMOS tube MP4; a source of the PMOS switch tube MP4 is connected to a source of the PMOS tube MP3; a source of the PMOS switch tube MP4 and a source of the PMOS tube MP3 are respectively connected to a drain of a PMOS switch tube MP2; a source of the PMOS switch tube MP4 and a source of the PMOS tube MP3 are respectively connected to an input terminal of a fourth resistor R4; a gate of the PMOS switch tube MP2 is connected to a second output terminal EC<1> of the equalization control input terminal EC; an output terminal of the fourth resistor R4 is connected to a source of the PMOS switch tube MP2; an output terminal of the fourth resistor R4 and a source of the PMOS switch tube MP2 are respectively connected to a drain of a PMOS switch tube MP1; an output terminal of the fourth resistor R4 and a source of the PMOS switch tube MP2 are respectively connected to an input terminal of a third resistor R3; a gate of the PMOS switch tube MP1 is connected to a first output terminal EC<0> of the equalization control input terminal EC; an output terminal of the third resistor R3 is connected to a source of the PMOS switch tube MP1; a source of the PMOS switch tube MP1 is connected to an analog power supply terminal AVDD;

[0055] The input terminal of the second resistor array 303 is connected to the input terminals of the parallel-connected ninth resistor R9 and tenth resistor R10; the output terminals of the parallel-connected ninth resistor R9 and tenth resistor R10 are connected to the input terminal of the eleventh resistor R11; the output terminal of the eleventh resistor R11 is connected to the drain of the NMOS switch MN3; the output terminals of the parallel-connected ninth resistor R9 and tenth resistor R10 are connected to the input terminal of the twelfth resistor R12; the output terminal of the twelfth resistor R12 is connected to the drain of the NMOS switch MN4; the source of the NMOS switch MN3 is connected to the source of the NMOS switch MN4; the gate of the NMOS switch MN3 is connected to the fifth output terminal EC<4> of the equalization control input terminal EC; the gate of the NMOS switch MN4 is connected to the eighth output terminal EC<7> of the equalization control input terminal EC; the source of the NMOS switch MN3 and the source of the NMOS switch MN4 are connected to the drain of the NMOS switch MN2; the source of the NMOS switch MN3 and the source of the NMOS switch MN4 are connected to the input terminal of the thirteenth resistor R13; the source of the NMOS switch MN2 is connected to the output terminal of the thirteenth resistor R13; the gate of the NMOS switch MN2 is connected to the sixth output terminal EC<5> of the equalization control input terminal EC; the source of the NMOS switch MN2 and the output terminal of the thirteenth resistor R13 are respectively connected to the drain of the NMOS switch MN1; the source of the NMOS switch MN2 and the output terminal of the thirteenth resistor R13 are respectively connected to the input terminal of the fourteenth resistor R14; the source of the NMOS switch MN1 is connected to the output terminal of the fourteenth resistor R14 and is grounded at the same time; the gate of the NMOS switch MN1 is connected to the seventh output terminal EC<6> of the equalization control input terminal EC; the input terminal of the third resistor array 305 is connected to the input terminals of the parallel-connected nineteenth resistor R19 and twentieth resistor R20; the output terminals of the parallel-connected nineteenth resistor R19 and twentieth resistor R20 are connected to the input terminal of the seventeenth resistor R17; the output terminal of the seventeenth resistor R17 is connected to the drain of the PMOS switch MP7; the eleventh output terminal EC<10> of the equalization control input terminal EC is connected to the gate of the PMOS transistor MP7; the output terminals of the parallel-connected nineteenth resistor R19 and twentieth resistor R20 are connected to the input terminal of the eighteenth resistor R18; the output terminal of the eighteenth resistor R18 is connected to the drain of the PMOS switch MP8; the twelfth output terminal EC<11> of the equalization control input terminal EC is connected to the gate of the PMOS transistor MP8; the source of the PMOS switch MP7 is connected to the source of the PMOS switch MP8; the source of the PMOS switch MP7 and the source of the PMOS switch MP8 are respectively connected to the drain of the PMOS switch MP6; the source of the PMOS switch MP7 and the source of the PMOS switch MP8 are respectively connected to the input terminal of the sixteenth resistor R16; the gate of the PMOS switch MP6 is connected to the tenth output terminal EC<9> of the equalization control input terminal EC;The output terminal of the sixteenth resistor R16 is connected to the source of the PMOS switch tube MP6; the output terminal of the sixteenth resistor R16 and the source of the PMOS switch tube MP6 are respectively connected to the drain of the PMOS switch tube MP5; the output terminal of the sixteenth resistor R16 and the source of the PMOS switch tube MP6 are respectively connected to the input terminal of the fifteenth resistor R15; the gate of the PMOS switch tube MP5 is connected to the ninth output terminal EC<8> of the equalization control input terminal EC; the output terminal of the fifteenth resistor R15 is connected to the source of the PMOS switch tube MP5; the source of the PMOS switch tube MP5 is connected to the analog power supply terminal AVDD; the input terminal of the fourth resistor array 306 is connected to the input terminals of the parallel-connected twenty-first resistor R21 and twenty-second resistor R22; the output terminals of the parallel-connected twenty-first resistor R21 and twenty-second resistor R22 are connected to the input terminal of the twenty-third resistor R23; the output terminal of the twenty-third resistor R23 is connected to the drain of the NMOS switch tube MN7; the output terminals of the parallel-connected twenty-first resistor R21 and twenty-second resistor R22 are respectively connected to the input terminals of the twenty-fourth resistor R24; the output terminal of the twenty-fourth resistor R24 is connected to the drain of the NMOS switch tube MN8; the source of the NMOS switch tube MN7 is connected to the source of the NMOS switch tube MN8; the gate of the NMOS switch tube MN7 is connected to the thirteenth output terminal EC<12> of the equalization control input terminal EC; the gate of the NMOS switch tube MN8 is connected to the sixteenth output terminal EC<15> of the equalization control input terminal EC; the source of the NMOS switch tube MN7 and the source of the NMOS switch tube MN8 are connected to the drain of the NMOS switch tube MN6; the source of the NMOS switch tube MN7 and the source of the NMOS switch tube MN8 are connected to the input terminal of the twenty-fifth resistor R25; the source of the NMOS switch tube MN6 is connected to the output terminal of the twenty-fifth resistor R25; the gate of the NMOS switch tube MN6 is connected to the fourteenth output terminal EC<13> of the equalization control input terminal EC; the source of the NMOS switch tube MN6 and the output terminal of the twenty-fifth resistor R25 are respectively connected to the drain of the NMOS switch tube MN5; the source of the NMOS switch tube MN6 and the output terminal of the twenty-fifth resistor R25 are respectively connected to the input terminal of the twenty-sixth resistor R26; the source of the NMOS switch tube MN5 is connected to the output terminal of the twenty-sixth resistor R26 and is grounded at the same time; the gate of the NMOS switch tube MN5 is connected to the fifteenth output terminal EC<14> of the equalization control input terminal EC;

[0056] The input terminals of the main path signal circuit 104 include a third input terminal VI3, a fourth input terminal VI4, and a main path control input terminal SC; the main path control input terminal SC is a digital switch; the main path control input terminal SC includes seven input terminals and seven output terminals, and the input terminals and output terminals correspond one by one; the output terminals of the main path signal circuit 104 include a third output terminal VO3 and a fourth output terminal VO4;

[0057] The main path signal circuit 104 includes a first impedance matching resistor array, a second impedance matching resistor array, a first coupling capacitor 204, a second coupling capacitor 205, and a common mode voltage circuit;

[0058] The first coupling capacitor 204 includes a first capacitor C1 and a sixth terminal SC<5> of the main path control input terminal SC; the first capacitor C1 is connected in parallel with the sixth terminal SC<5> of the main path control input terminal SC;

[0059] The second coupling capacitor 205 includes a second capacitor C2 and a sixth terminal SC<6> of the main path control input terminal SC; the second capacitor C2 is connected in parallel with the sixth terminal SC<6> of the main path control input terminal SC;

[0060] The first impedance matching resistor array R1 includes five resistors connected in parallel; each resistor is connected in series with a pair of input and output terminals of the main path control input terminal SC; the five resistors are respectively connected in series with the first to fifth terminals of the main path control input terminal SC in sequence; the second impedance matching resistor array R2 is the same as the first impedance matching resistor array R1;

[0061] The third input terminal VI3 of the main path signal circuit 104 is connected to the input terminal of the first impedance matching resistor array; the third input terminal VI3 of the main path signal circuit 104 is connected to one end of the first coupling capacitor 204; the other end of the first coupling capacitor 204 is connected to the third output terminal VO3;

[0062] The fourth input terminal VI4 of the main path signal circuit 104 is connected to the input terminal of the second impedance matching resistor array; the fourth input terminal VI4 of the main path signal circuit 104 is connected to one end of the second coupling capacitor 205; the other end of the second coupling capacitor 205 is connected to the fourth output terminal VO4;

[0063] The output terminals of the first impedance matching resistor array and the second impedance matching resistor array are connected to the input terminal of the common mode voltage circuit 203; the output terminal of the common mode voltage circuit 203 is grounded;

[0064] The first impedance matching resistor array and the second impedance matching resistor array are used to receive data signals from the receiving end data path 101, and are also used to adjust the output impedance of the main path signal circuit 104 to achieve impedance matching with the transmission line impedance, so as to reduce the signal reflection problem caused by impedance discontinuity;

[0065] The common-mode voltage circuit 203 is used to regulate the common-mode terminal voltage of the main path signal circuit; the common-mode voltage circuit includes a first common-mode digital switch, a second common-mode digital switch, and a third common-mode digital switch; the input end of the common-mode voltage circuit is respectively connected to the input ends of the first common-mode digital switch, the second common-mode digital switch, and the third common-mode digital switch; the output end of the first common-mode digital switch is connected to a 1.2V voltage; the output end of the second common-mode digital switch is connected to a 0.8V voltage; the output end of the third common-mode digital switch is connected to ground; in the DC coupling scenario, the common-mode voltage circuit outputs and selects the 1.2V voltage mode or the ground mode; in the AC coupling scenario, the common-mode voltage circuit outputs and selects to connect to the 0.8V voltage mode.

[0066] The first signal superposition circuit 106 and the second signal superposition circuit 107 have the same structure;

[0067] The first signal superposition circuit 106 includes an enable control circuit 401, a first input pair of transistors 404, a second input pair of transistors 405, a first current source array 402, a second current source array 403, a first load resistor array 406, and a second load resistor array 407;

[0068] The first input pair of transistors 404 includes an NMOS transistor MN11 and an NMOS transistor MN12; the fifth input terminal VI5 of the first signal superposition circuit 106 is connected to the gate of MN11; the sixth input terminal VI6 of the first signal superposition circuit 106 is connected to the gate of MN12; the source of the NMOS transistor MN11 and the source of the NMOS transistor MN12 are connected; the drain of MN11 is connected to the input end of the first load resistor array 406; the drain of MN12 is connected to the input end of the second load resistor array 407;

[0069] The first input pair of transistors 405 includes an NMOS transistor MN13 and an NMOS transistor MN14; the seventh input terminal VI7 of the first signal superposition circuit 106 is connected to the gate of MN13; the eighth input terminal VI8 of the first signal superposition circuit 106 is connected to the gate of MN14; the source of the NMOS transistor MN13 and the source of the NMOS transistor MN14 are connected; the drain of MN13 is connected to the input end of the first load resistor array 406; the drain of MN14 is connected to the input end of the second load resistor array 407;

[0070] The first load resistor array 406 includes a twenty-eighth resistor R28, a PMOS switch tube MP9, a PMOS switch tube MP10, and a twenty-seventh resistor R27; the input end of the first load resistor array 406 is simultaneously connected to the input end of the twenty-eighth resistor R28, the input end of the twenty-seventh resistor R27, and the fifth output end VO5; the output end of the twenty-eighth resistor R28 is connected to the drain of the PMOS switch tube MP10; the source of the PMOS switch tube MP10 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch tube MP10 is connected to the second output end S1<1> of the first superimposed control signal input terminal S1; the output end of the twenty-seventh resistor R27 is connected to the drain of the PMOS switch tube MP9; the source of the PMOS switch tube MP9 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch tube MP9 is connected to the first output end S1<0> of the first superimposed control signal input terminal S1;

[0071] The second load resistor array 407 includes a twenty-ninth resistor R29, a PMOS switch tube MP11, a PMOS switch tube MP12, and a thirtieth resistor R30; the input end of the second load resistor array 407 is simultaneously connected to the input end of the twenty-ninth resistor R29, the input end of the thirtieth resistor R30, and the sixth output end VO6; the output end of the twenty-ninth resistor R29 is connected to the drain of the PMOS switch tube MP11; the source of the PMOS switch tube MP11 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch tube MP11 is connected to the second output end S1<1> of the first superimposed control signal input terminal S1; the output end of the thirtieth resistor R30 is connected to the drain of the PMOS switch tube MP12; the source of the PMOS switch tube MP12 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch tube MP12 is connected to the first output end S1<0> of the first superimposed control signal input terminal S1;

[0072] The first current source array includes four NMOS transistors; the sources of the four NMOS transistors are grounded respectively; the gate of each NMOS transistor is connected in series with an output end of the first superimposed control signal input terminal S1; the gates of the four NMOS transistors are connected in series with the fifth to eighth output ends of the first superimposed control signal input terminal S1 in sequence; the drains of the four NMOS transistors are connected in parallel and then connected to the source of the NMOS transistor MN11 and the source of the NMOS transistor MN12 respectively;

[0073] The second current source array includes four NMOS transistors; the sources of the four NMOS transistors are grounded respectively; the gate of each NMOS transistor is connected in series with an output terminal of the first superimposed control signal input terminal S1; the gates of the four NMOS transistors are sequentially connected in series with the ninth to twelfth output terminals of the first superimposed control signal input terminal S1; the drains of the four NMOS transistors are connected in parallel and then connected to the source of the NMOS transistor MN13 and the source of the NMOS transistor MN14 respectively;

[0074] The enabling control circuit includes an NMOS transistor MN9, an NMOS transistor MN10 and a PMOS switch transistor MP13; the first reference current input terminal I1 is connected to the drain of the NMOS transistor MN9 and the source of the PMOS switch transistor MP13 respectively; the source of the NMOS transistor MN9 is connected to the drain of the PMOS switch transistor MP13; the gate of the NMOS transistor MN9 is connected to the fourth input / output terminal S1<3> of the first superimposed control signal input terminal S1; the gate of the PMOS switch transistor MP13 is connected to the third input / output terminal S1<2> of the first superimposed control signal input terminal S1; the source of the NMOS transistor MN9 is connected to the drain of the NMOS transistor MN10; the source of the NMOS transistor MN10 is grounded; the gate of the NMOS transistor MN10 is connected to the third input / output terminal S1<2> of the first superimposed control signal input terminal S1; the source of the NMOS transistor MN9 is connected to the gates of the four NMOS transistors of the first current source array respectively; the source of the NMOS transistor MN9 is connected to the gates of the four NMOS transistors of the second current source array respectively;

[0075] The present invention will be further described below in conjunction with the drawings and embodiments.

[0076] The present invention provides a radiation-resistant FPGA embedded 28Gbps serial interface signal compensation circuit, which can superimpose and amplify the signals processed by the main path signal circuit and the equalization signal circuit of the original high-frequency attenuation signal, so as to realize the compensation processing of data signals, avoiding problems such as compensation degree limitation, power supply voltage limitation and power supply noise limitation brought by only pre-compensating at the sending end in the prior art. Therefore, a better signal compensation effect can be achieved, and it has radiation-resistant ability, avoiding single-event effects and ensuring the reliability of signal transmission. Among them, the single-event effect refers to the phenomenon that a single high-energy charged particle in space hits the sensitive part of a microelectronic device. Due to ionization, the device generates extra charges or causes atomic displacement of the material, its logical state changes, and its function is interfered with or fails.

[0077] As Figure 1As shown, the above anti-radiation FPGA incorporates a 28 Gbps serial interface signal compensation circuit, including a main path signal circuit, an equalization signal circuit, a signal superposition circuit, and an anti-radiation circuit; the main path signal circuit and the equalization signal circuit are respectively used to receive high-frequency attenuated signals, and the high-frequency attenuated signals come from the receiving end of the serial interface; the main path signal circuit is also used to perform impedance matching and common-mode terminal voltage processing on the high-frequency attenuated signal according to the control signal of the main path signal circuit to obtain the main path output signal, and input the main path output signal into the signal superposition circuit; the equalization signal circuit is also used to perform equalization processing on the high-frequency attenuated signal according to the control signal of the equalization signal circuit to obtain the equalization signal, and input the equalization signal into the signal superposition circuit; the signal superposition circuit is used to superimpose the main path output signal and the equalization signal according to the control signal of the signal superposition circuit to obtain the superimposed signal; the anti-radiation circuit is used to strengthen the storage and output the control signals of the main path signal circuit / equalization signal circuit / signal superposition circuit.

[0078] For example, as Figure 2 shown, in some alternative embodiments, the receiving end data path 101 is a data signal path for receiving data from the system sending end and the transmission cable, and this data is a data signal after high-frequency attenuation. The first receiving output end RX1 of the receiving end data path 101 is respectively connected to the first input end VI3 of the main path signal circuit 104 and the first input end VI1 of the equalization signal circuit 105; the second receiving output end RX2 of the receiving end data path 101 is respectively connected to the second input end VI4 of the main path signal circuit 104 and the second input end VI2 of the equalization signal circuit 105; the receiving end data path 101 transmits the high-frequency attenuated signal to the equalization signal circuit 105 for equalization processing, and the receiving end data path 101 transmits the high-frequency attenuated signal to the main path signal circuit 104 for impedance matching and common-mode terminal voltage processing.

[0079] Based on the same inventive concept, the anti-radiation FPGA incorporated serial interface signal compensation circuit provided by the embodiments of the present invention, the signal compensation set at the receiving end is not limited to a 28 Gbps transmission rate, and can also be used in signal transmissions with other transmission rates. Preferably, the signal compensation scheme provided by the embodiments of the present invention is applicable to the signal transmission of the FPGA incorporated 28 Gbps serial interface.

[0080] As Figure 2As shown, in some alternative embodiments, the anti-radiation circuit includes a first anti-radiation configuration circuit 102, a second anti-radiation configuration circuit 103, and an anti-radiation auxiliary circuit 108. The control signal output terminal CS1 of the first anti-radiation configuration circuit 102 is connected to the control signal input terminal EC of the equalization signal circuit 105 for providing a control signal to the equalization signal circuit 105. The control signal output terminal CS2 of the second anti-radiation configuration circuit 103 is connected to the control signal input terminal SC of the main path signal circuit 104 for providing a control signal to the main path signal circuit 104. The control signal output terminal CS1 of the first anti-radiation configuration circuit 102 is a digital switch signal and includes 16 output terminals; the control signal output terminal CS2 of the second anti-radiation configuration circuit 103 is a digital switch signal and includes 5 output terminals. The output terminals EN1 and EN2 of the anti-radiation auxiliary circuit 108 are both digital switch signals and each includes 12 output terminals.

[0081] In the above embodiments, the anti-radiation circuit as shown in the anti-radiation auxiliary circuit 108 includes a voltage-current biasing circuit and an anti-radiation hardened storage circuit; the voltage-current biasing circuit is used to provide a reference current for the current source array in the signal superposition circuit; the anti-radiation hardened storage circuit is used to harden and store and output the control signals of the main path signal circuit / equalization signal circuit / signal superposition circuit.

[0082] In the above embodiments, the anti-radiation circuit as shown in the first anti-radiation configuration circuit 102 or the second anti-radiation configuration circuit 103 is composed of digital logic circuits, specifically including digital buffer units, radiation hardened storage units, etc., and has the ability to resist the influence of single-event effects, that is, has anti-radiation ability, and is used to provide control signals for the main path signal circuit 104 or the equalization signal circuit 105.

[0083] In some specific embodiments, when the transmission path of the superimposed signal includes at least two paths, the anti-radiation FPGA also includes an embedded 28Gbps serial interface signal compensation circuit: a data delay processing circuit and a clock data recovery circuit; the data delay processing circuit is used to perform delay processing on the superimposed signal and input the delayed superimposed signal into the data identification terminal and the edge identification terminal of the clock data recovery circuit respectively; the clock data recovery circuit is used to perform data recovery and clock recovery on the delayed superimposed signal.

[0084] For example, as Figure 2As shown, in some alternative embodiments, the signal superposition circuit includes a first signal superposition circuit 106 and a second signal superposition circuit 107. At this time, when the transmission path of the superimposed signal includes four paths, namely: the first output terminal VO5 of the first signal superposition circuit 106 to the first input terminal VI13 of the data delay processing circuit 109, the second output terminal VO6 of the first signal superposition circuit 106 to the second input terminal VI14 of the data delay processing circuit 109, the first output terminal VO7 of the second signal superposition circuit 107 to the third input terminal VI15 of the data delay processing circuit 109, and the second output terminal VO8 of the second signal superposition circuit 107 to the fourth input terminal VI16 of the data delay processing circuit 109.

[0085] In some specific embodiments, the signal connection of the radiation-hardened FPGA embedded with a 28 Gbps serial interface signal compensation circuit is as follows: The main path signal circuit includes two signal input terminals, two signal output terminals, and one control signal input terminal; the equalization signal circuit includes two signal input terminals, two signal output terminals, and one control signal input terminal; the signal superposition circuit includes a first signal superposition circuit and a second signal superposition circuit with the same structure. The first signal superposition circuit includes four signal input terminals, two signal output terminals, one control signal input terminal, and one reference current input terminal; the radiation-hardened circuit includes a first radiation-hardened configuration circuit, a second radiation-hardened configuration circuit, and a radiation-hardened auxiliary circuit. The control signal output terminal of the first radiation-hardened configuration circuit is connected to the control signal input terminal of the equalization signal circuit, and the control signal output terminal of the second radiation-hardened configuration circuit is connected to the control signal input terminal of the main path signal circuit. The radiation-hardened auxiliary circuit includes two control signal output terminals and two reference current output terminals. One control signal output terminal of the radiation-hardened auxiliary circuit is connected to the control signal input terminal of the first signal superposition circuit, and one reference current output terminal of the radiation-hardened auxiliary circuit is connected to the reference current input terminal of the first signal superposition circuit. The other control signal output terminal of the radiation-hardened auxiliary circuit is connected to the control signal input terminal of the second signal superposition circuit, and the other reference current output terminal of the radiation-hardened auxiliary circuit is connected to the reference current input terminal of the second signal superposition circuit; the two signal output terminals of the main path signal circuit are respectively connected to the two signal input terminals of the first signal superposition circuit and the second signal superposition circuit, and the two signal output terminals of the equalization signal circuit are respectively connected to the other two signal input terminals of the first signal superposition circuit and the second signal superposition circuit; the radiation-hardened FPGA embedded with a 28 Gbps serial interface signal compensation circuit further includes a data delay processing circuit, and the data delay processing circuit includes four signal input terminals, which are respectively connected to the signal output terminals of the first signal superposition circuit and the second signal superposition circuit.

[0086] Taking Figure 2 the connection shown as an example, the signal connection in the above embodiments includes:

[0087] The first output terminal VO3 of the main path signal circuit 104 is respectively connected to the third input terminal VI7 of the first signal superposition circuit 106 and the third input terminal VI11 of the second signal superposition circuit 107. The second output terminal VO4 of the main path signal circuit 104 is respectively connected to the fourth input terminal VI8 of the first signal superposition circuit 106 and the fourth input terminal VI12 of the second signal superposition circuit 107, for transmitting the high-frequency attenuation signal after impedance matching and setting the common-mode terminal voltage to the first signal superposition circuit 106 and the second signal superposition circuit 107 for superposition processing. The first output terminal VO1 of the equalization signal circuit 105 is respectively connected to the first input terminal VI5 of the first signal superposition circuit 106 and the first input terminal VI9 of the second signal superposition circuit 107. The second output terminal VO2 of the equalization signal circuit 105 is respectively connected to the second input terminal VI6 of the first signal superposition circuit 106 and the second input terminal VI10 of the second signal superposition circuit 107, for transmitting the equalized signal after equalization processing to the first signal superposition circuit 106 and the second signal superposition circuit 107 for superposition processing.

[0088] Figure 2 Among them, the first output terminal VO5 of the first signal superposition circuit 106 is connected to the first input terminal VI13 of the data delay processing circuit 109, and its second output terminal VO6 is connected to the second input terminal VI14 of the data delay processing circuit 109. The first signal superposition circuit 106 superimposes and processes the high-frequency attenuation signal processed by the main path signal circuit 104 and the equalization signal processed by the equalization signal circuit 105 to achieve a signal compensation effect, and outputs the compensated signal to the data identification terminal of the clock data recovery circuit after delay processing. The first output terminal VO7 of the second signal superposition circuit 107 is connected to the third input terminal VI15 of the data delay processing circuit 109, and its second output terminal VO8 is connected to the fourth input terminal VI16 of the data delay processing circuit 109. The second signal superposition circuit 106 superimposes and processes the high-frequency attenuation signal processed by the main path signal circuit 104 and the equalization signal processed by the equalization signal circuit 105 to achieve a signal compensation effect, and outputs the compensated signal to the edge identification terminal of the clock data recovery circuit after delay processing.

[0089] Figure 2In the figure, the control signal output terminal EN1 and the reference current output terminal B1 of the anti-radiation auxiliary circuit 108 are respectively connected to the control signal input terminal S1 and the reference current input terminal I1 of the first signal superposition circuit 106, and the control signal output terminal EN2 and the reference current output terminal B2 of the anti-radiation auxiliary circuit 108 are respectively connected to the control signal input terminal S2 and the reference current input terminal I2 of the second signal superposition circuit 107, for providing control signals and bias voltages to the first signal superposition circuit 106 and the second signal superposition circuit 107 respectively. The first signal output terminal VO9 and the second signal output terminal VO10 of the data delay processing circuit 109 are respectively connected to the data identification terminal and the edge identification terminal of the receiving end clock data recovery circuit CDR (Clock and Data Recovery) for data recovery and clock recovery.

[0090] In some specific embodiments, the main path signal circuit includes an impedance matching resistor array, a common mode voltage circuit, and an output signal control code switch; the impedance matching resistor array includes switches with multiple control codes and a variable resistor array, for receiving high-frequency attenuation signals and adjusting the output impedance of the main path signal circuit to match the transmission line impedance; the common mode voltage circuit is respectively connected to the variable resistor array and the ground terminal for adjusting the common mode terminal voltage of the signal of the main path signal circuit; the output signal control code switch is respectively connected to the impedance matching resistor array and the signal output terminal of the main path signal circuit; the switches with multiple control codes and the output signal control code switch are for receiving the control signals of the main path signal circuit output by the anti-radiation circuit.

[0091] For example, as Figure 3 shown, the main path signal circuit 104 includes a first impedance matching resistor array, a second impedance matching resistor array, a common mode voltage circuit 203, a first coupling capacitor 204, and a second coupling capacitor 205. Among them, the first impedance matching resistor array and the second impedance matching resistor array are variable resistors respectively composed of switches controlled by five-bit control codes and resistor arrays R1 and R2, for receiving data signals from the receiving end data path 101, and also for adjusting the output impedance of the main path signal circuit 104 to achieve impedance matching with the transmission line impedance, so as to reduce the signal reflection problem caused by impedance discontinuity.

[0092] In some specific embodiments, the common mode voltage circuit includes a power supply connection mode, a ground connection mode, and a two-thirds power supply connection mode. Different common mode voltages are for different application scenarios. Specifically, in the DC coupling scenario, the common mode voltage circuit selects the power supply connection mode or the ground connection mode; in the AC coupling scenario, the common mode voltage circuit selects the two-thirds power supply connection mode.

[0093] For example, as Figure 3As shown, the common-mode voltage circuit 203 is used to regulate the common-mode terminal voltage of the main path signal circuit, and has three selection modes: connected to the power supply, grounded, and two-thirds of the power supply value. One of the three modes can be selected according to the system application requirements.

[0094] In the common-mode voltage circuit 203, the coupling capacitors can be used in two ways. One is to use the coupling capacitors on the external board; the other is to use the internal coupling capacitors when no coupling capacitors are soldered externally. When choosing to use the internal coupling capacitors, in some specific embodiments, the above-mentioned main path signal circuit further includes coupling capacitors, and each coupling capacitor is respectively connected in parallel across the output signal control code switch. As Figure 3 shown, the first coupling capacitor 204 is composed of a switch controlled by the control code SC<5> and a capacitor C1, and the second coupling capacitor 205 is composed of a switch controlled by the control code SC<6> and a capacitor C2, and is used to select the internal / external capacitance coupling method to transmit the signal from the receive-end data path 101. Figure 3 Among them, SC<6:0> represents that the input terminal SC is a 7-bit control signal, including 7 input terminals and 7 output terminals. The input terminals and output terminals correspond one by one. Among them, SC<0> represents the first bit of the SC signal, and SC<6> represents the seventh bit of the control signal SC.

[0095] In some specific embodiments, the equalization signal circuit includes a high-pass filter circuit; the high-pass filter circuit includes an input capacitor, a PMOS switch transistor resistance array, and an NMOS switch transistor resistance array; the input capacitor is used to receive the high-frequency attenuation signal and transmit the signal to the PMOS switch transistor resistance array and the NMOS switch transistor resistance array; the PMOS switch transistor resistance array includes a plurality of PMOS switch transistors and resistors, and the PMOS switch transistor resistance array is respectively connected to the analog power supply terminal and the signal output terminal of the high-pass filter circuit; the NMOS switch transistor resistance array includes a plurality of NMOS switch transistors and resistors, and the NMOS switch transistor resistance array is respectively connected to the ground terminal and the signal output terminal of the high-pass filter circuit; the PMOS switch transistors of the PMOS switch transistor resistance array and the NMOS switch transistors of the NMOS switch transistor resistance array are used to receive the control signal of the equalization signal circuit output by the anti-radiation circuit to turn on or off the high-pass filter circuit.

[0096] In some specific embodiments, the equalization signal circuit further includes a redundant high-pass filter circuit; the redundant high-pass filter circuit has the same structure as the high-pass filter circuit.

[0097] For example, as Figure 4As shown, the equalization signal circuit 105 includes a first input capacitor, a second input capacitor, a first resistor array 302, a second resistor array 303, a third resistor array 305, and a fourth resistor array 306. Among them, the first input capacitor and the first resistor array 302, the second resistor array 303 respectively form a high-pass filter circuit; the second input capacitor and the third resistor array 305, the fourth resistor array 306 respectively form a redundant high-pass filter circuit. The first resistor array 302 and the third resistor array 305 are respectively connected to the analog power supply terminal (AVDD), and the first resistor array 302 is also connected to the signal output terminal VO1 of the high-pass filter circuit, and the third resistor array 305 is also connected to the signal output terminal VO2 of the redundant high-pass filter circuit. The second resistor array 303 and the fourth resistor array 306 are respectively connected to the ground terminal, and the second resistor array 303 is also connected to the signal output terminal VO1 of the high-pass filter circuit, and the fourth resistor array 306 is also connected to the signal output terminal VO2 of the redundant high-pass filter circuit.

[0098] Figure 4 Among them, the first input capacitor C3 is connected between the first input terminal VI1 of the equalization signal circuit 105 and the first output terminal VO1 of the equalization signal circuit 105, and the second input capacitor C4 is connected between the second input terminal VI2 of the equalization signal circuit 105 and the second output terminal VO2 of the equalization signal circuit 105.

[0099] Figure 4 Among them, the first resistor array 302 is composed of PMOS switching transistors MP1, MP2, MP3, MP4 and resistors R3, R4, R5, R6, R7, R8; the second resistor array 303 is composed of NMOS switching transistors MN1, MN2, MN3, MN4 and resistors R9, R10, R11, R12, R13, R14; the third resistor array 305 is composed of PMOS switching transistors MP5, MP6, MP7, MP8 and resistors R15, R16, R17, R18, R19, R20; the fourth resistor array 306 is composed of NMOS switching transistors MN5, MN6, MN7, MN8 and resistors R21, R22, R23, R24, R25, R26. Taking the first resistor array 302 as an example, the internal connection of the resistor array is described. One end of the parallel connection of resistors R7 and R8 is connected to the first output terminal VO1 of the equalization signal circuit 105, and the other end of the parallel connection of resistors R7 and R8 is connected to one end of resistors R5 and R6. The other end of resistor R5 is connected to the drain of MP3, and the other end of resistor R6 is connected to the drain of MP4. The sources of MP3 and MP4 are connected to each other. The drain of MP2 is connected to the source of MP3, and resistor R4 is connected in parallel between the source and drain of MP2. The drain of MP1 is connected to the source of MP2, and resistor R3 is connected in parallel between the source and drain of MP1. The source of MP1 is connected to the analog power supply terminal (AVDD).

[0100] Figure 4Among them, EC<15:0> indicates that the input end EC is a 16-bit control signal, including 16 input ends and 16 output ends, and the input ends and output ends correspond one by one. The 1st to 4th bits EC<0>, EC<1>, EC<2>, EC<3> of the signal EC are respectively connected to the gate input ends of the PMOS switch tubes MP1, MP2, MP3, MP4 of the first resistor array 302. The 5th to 8th bits EC<4>, EC<5>, EC<6>, EC<7> of the signal EC are respectively connected to the gate input ends of the NMOS switch tubes MN3, MN2, MN1, MN4 of the second resistor array 303. The 9th to 12th bits EC<8>, EC<9>, EC<10>, EC<11> of the signal EC are respectively connected to the gate input ends of the PMOS switch tubes MP5, MP6, MP7, MP8 of the third resistor array 305. The 13th to 16th bits EC<12>, EC<13>, EC<14>, EC<15> of the signal EC are respectively connected to the gate input ends of the NMOS switch tubes MN7, MN6, MN5, MN8 of the fourth resistor array 306.

[0101] In some specific embodiments, the equalization signal circuit includes a first working mode, a second working mode, and a third working mode. In the first working mode, both the high-pass filter circuit and the redundant high-pass filter circuit are in the off state. After passing through the input capacitor, the high-frequency attenuation signal is output to the signal superposition circuit without passing through the PMOS switch tube resistor array and the NMOS switch tube resistor array. In the second working mode, the PMOS switch tube resistor array is in the on state, and the NMOS switch tube resistor array is in the off state. By controlling the PMOS switch tubes, the resistance value of the PMOS switch tube resistor array is changed to control the high-frequency bandwidth of the high-pass filter circuit, and high-frequency signal amplitude non-loss processing and low-frequency signal amplitude reduction processing are performed to obtain an equalization signal. In the third working mode, the NMOS switch tube resistor array is in the on state, and the PMOS switch tube resistor array is in the off state. By controlling the NMOS switch tubes, the resistance value of the NMOS switch tube resistor array is changed to control the high-frequency bandwidth of the redundant high-pass filter circuit, and high-frequency signal amplitude non-loss processing and low-frequency signal amplitude reduction processing are performed to obtain an equalization signal.

[0102] For example, as Figure 4 shown in the equalization signal circuit, the PMOS switch tubes and the NMOS switch tubes are used to turn on and off the path resistors. When working normally, there are three selection modes:

[0103] The first working mode is that the first, second, third, and fourth input resistor arrays are all in the off state. At this time, a high-pass filter circuit is not formed, the signal does not enter the compensation state, and the input signal directly passes through capacitors C3 and C4 and is then output to the first signal superposition circuit 106 and the second signal superposition circuit 107 of the subsequent stage.

[0104] The second working mode is that the first and third resistor arrays are in the on state, and the second and fourth resistor arrays are in the off state. At this time, a high-pass filter circuit is formed, and the signal enters the signal equalization state. By changing the resistance values of the first resistor array 302 and the third resistor array 305 through the PMOS transistor switch, the high-frequency bandwidth of the high-pass filter is further changed to achieve different degrees of equalization effects. In the signal equalization state, after the high-frequency signal amplitude is not lost and the low-frequency signal amplitude is reduced, the equalized signal is then output to the input ends of the first signal superposition circuit 106 and the second signal superposition circuit 107.

[0105] The third working mode is that the first and third resistor arrays are in the off state, and the second and fourth resistor arrays are in the on state. At this time, a high-pass filter circuit is formed, and the signal enters the signal equalization state. By changing the resistance values of the second resistor array 303 and the fourth resistor array 306 through the NMOS transistor switch, the high-frequency bandwidth of the high-pass filter is further changed to achieve different degrees of equalization effects. In the signal equalization state, after the high-frequency signal amplitude is not lost and the low-frequency signal amplitude is reduced, the equalized signal is then output to the input ends of the first signal superposition circuit 106 and the second signal superposition circuit 107.

[0106] In some specific embodiments, the signal superposition circuit includes an enable control circuit, an input pair of transistors, a current source array, and a load resistor array; wherein, the enable control circuit, the current source array, and the load resistor array are used to receive the control signals of the signal superposition circuit output by the anti-radiation circuit; the enable control circuit includes a PMOS switch transistor and an NMOS switch transistor, and is used to control the bias voltage output by the anti-radiation circuit to be transmitted to the current source array to control the on / off of the current source array; the input pair of transistors includes a pair of NMOS switch transistors and is used to receive the main path output signal and the equalization signal; the current source array is an NMOS switch transistor current source array, and according to the control signals of the signal superposition circuit output by the anti-radiation circuit, by adjusting the current of the current source array, the amplitude and gain multiple of the superposed signal are controlled; the load resistor array includes a PMOS switch transistor and a resistor, and is used to control the amplitude and common-mode terminal voltage of the superposed signal by adjusting the output resistance. The common-mode terminal voltage control performed by the load resistor array can be adapted to the common mode of the previous stage to achieve better signal transmission. The common-mode terminal voltage will affect the response speed of the subsequent stage circuit, and a more appropriate common-mode value will make the response speed of the subsequent stage circuit faster.

[0107] For example, asFigure 5 The signal superposition circuit shown, the first signal superposition circuit 106 respectively includes an enable control circuit 401, a first input pair of transistors 404, a second input pair of transistors 405, a first current source array 402, a second current source array 403, a first load resistor array 406, and a second load resistor array 407. The first signal superposition circuit 106 includes signal input terminals VIN5, VIN6, VIN7, and VIN8 (corresponding to Figure 2 VI5, VI6, VI7, and VI8 in it), signal output terminals VO5 and VO6, a reference current input terminal I1, and a control signal input terminal S1<11:0>, where S1<11:0> indicates that the input terminal S1 is a 12-bit control signal, including 12 input terminals and 12 output terminals, and the input terminals and output terminals correspond one by one. The enable control circuit 401 is composed of a PMOS switch transistor MP13 and NMOS switch transistors MN9 and MN10. The source of MN10 is grounded, the source of MP13 is connected to the drain of MN9, the drain of MP13 is connected to the source of MN9, the reference current input terminal I1 of the first signal superposition circuit 106 is connected to the source of MP13 and the drain of MN9, the gate of MN9 is connected to the 4th output terminal S1<3> of S1, and the gates of MN10 and MP13 are connected to the 3rd output terminal S1<2> of S1. The enable control circuit 401 is used to control the bias voltage output by the anti-radiation auxiliary circuit 108 to be transmitted to the first current source array 402 and the second current source array 403, and is also used to turn off the first and second current source arrays in the non-working state and enter the low-power mode. Among them, the bias voltage provides a reference current for the current source array in the signal superposition circuit.

[0108] Figure 5 In it, the first input pair of transistors 404 is composed of NMOS transistors MN11 and MN12. The sources of MN11 and MN12 are connected to each other. The drains of MN11 and MN12 are respectively connected to the first load resistor array 406 and the second load resistor array 407. The gates of MN11 and MN12 are respectively connected to the signal input terminals VIN5 and VIN6 of the first signal superposition circuit 106, and are used to receive the output signals of the equalization signal circuit 105. The second input pair of transistors 405 is composed of NMOS transistors MN13 and MN14. The sources of MN13 and MN14 are connected to each other. The drains of MN13 and MN14 are respectively connected to the first load resistor array 406 and the second load resistor array 407. The gates of MN13 and MN14 are respectively connected to the signal input terminals VIN7 and VIN8 of the first signal superposition circuit 106, and are used to receive the output signals of the main path signal circuit 104.

[0109] Figure 5Among them, the first current source array 402 and the second current source array 403 are respectively composed of NMOS transistor current source arrays MN15 and MN16. Their current magnitudes are respectively adjusted by the 5th to 8th output terminals S1<7:4> and the 9th to 12th output terminals S1<11:8> of the control signal S1. By changing the current magnitude, the amplitude and gain multiple of the output signal of the first signal superposition circuit 106 are adjusted. The sources of the NMOS transistor current source arrays MN15 and MN16 are grounded. The first load resistor array 406 is composed of PMOS switch transistors MP9, MP10 and resistors R27, R28. The second load resistor array 407 is respectively composed of PMOS switch transistors MP11, MP12 and resistors R29, R30, and is used to adjust the output resistance value, thereby changing the amplitude and common-mode terminal voltage of the output signal of the first signal superposition circuit 106. The gates of MP9 and MP12 are connected to the 1st output terminal S1<0> of S1. The gates of MP10 and MP11 are connected to the 2nd output terminal S1<1> of S1. The sources of MP9, MP10, MP11, and MP12 are connected to the analog power supply terminal (AVDD). One end of resistor R27 is connected to the drain of PMOS switch transistor MP9, and the other end is connected to the signal output terminal VO5. One end of resistor R28 is connected to the drain of PMOS switch transistor MP10, and the other end is respectively connected to the drain of NMOS transistor MN11, the drain of NMOS transistor MN13, and the signal output terminal VO5. One end of resistor R30 is connected to the drain of PMOS switch transistor MP12, and the other end is connected to the signal output terminal VO6. One end of resistor R29 is connected to the drain of PMOS switch transistor MP11, and the other end is respectively connected to the drain of NMOS transistor MN12, the drain of NMOS transistor MN14, and the signal output terminal VO6.

[0110] The first signal superposition circuit 106 and the second signal superposition circuit 107 perform superposition and amplification processing on the high-frequency attenuation signal of the main path signal circuit 104 and the low-frequency attenuation signal of the equalization signal circuit 105 received, so as to realize the compensation processing of the data signal. The structure of the second signal superposition circuit 107 is the same as that of the first signal superposition circuit 106.

[0111] The signal compensation circuit proposed by the present invention can superpose and amplify the signal after the original high-frequency attenuation signal is processed by the main path signal circuit and the equalization signal circuit at the receiving end, thereby realizing the compensation processing of the data signal, avoiding problems such as compensation degree limitation, power supply voltage limitation, and power supply noise limitation caused by only pre-compensating at the sending end in the prior art. Therefore, a better signal compensation effect can be achieved, and the error code can be reduced.

[0112] In some embodiments of the present invention, when the superimposed signal output by the signal superimposing circuit proposed by the present invention is divided into two or more transmission paths, the compensated signals are respectively passed to the data identification terminal and the edge identification terminal of the clock data recovery circuit after delay processing, so as to perform clock and data recovery processing, which helps to achieve better signal fidelity and reduce bit errors.

Claims

1. The anti-radiation FPGA is embedded with a 28Gbps serial interface signal compensation circuit, which is characterized in that: It includes a data receiving end, a main path signal circuit, an equalization signal circuit, a first signal superposition circuit, a first anti-radiation configuration circuit, a second anti-radiation configuration circuit, and an anti-radiation auxiliary circuit; the data receiving end includes a first receiving output end (RX1) and a second receiving output end (RX2); The first anti-radiation configuration circuit is used to strengthen storage and output the control signal of the equalization signal circuit; the second anti-radiation configuration circuit is used to strengthen storage and output the control signal of the main path signal circuit; the anti-radiation auxiliary circuit is used to strengthen storage and output the control signal of the first signal superposition circuit; the output end of the first anti-radiation configuration circuit is the first control signal (CS1); the output end of the second anti-radiation configuration circuit is the second control signal (CS2); the anti-radiation auxiliary circuit includes a first control signal output end (EN1), a second control signal output end (EN2), a first reference current output end (B1), and a second reference current output end (B2); The main path signal circuit performs impedance matching and common-mode terminal voltage processing on the high-frequency attenuation signal according to the control signal of the first anti-radiation configuration circuit to obtain the main path output signal, and inputs the main path output signal into the first signal superposition circuit; The equalization signal circuit performs equalization processing on the high-frequency attenuation signal according to the control signal of the second anti-radiation configuration circuit to obtain the equalization signal, and inputs the equalization signal into the first signal superposition circuit; The first signal superposition circuit superimposes the main path output signal and the equalization signal according to the control signal of the anti-radiation auxiliary circuit to obtain a superimposed signal; then connects the superimposed signal to the data recognition end and the edge recognition end respectively; the input end of the first signal superposition circuit includes a fifth input end (VI5), a sixth input end (VI6), a seventh input end (VI7), an eighth input end (VI8), a first reference current input end (I1), and a first superposition control signal input end (S1); the first superposition control signal input end (S1) is connected to the first control signal output end (EN1); the first reference current input end (I1) is connected to the first reference current output end (B1); the first superposition control signal input end (S1) is a 12-bit control signal, the first superposition control signal input end (S1) includes 12 input ends and 12 output ends, and the input ends and output ends correspond one by one; the output end of the first signal superposition circuit (106) includes a fifth output end (VO5) and a sixth output end (VO6); the fifth output end (VO5) is connected to the data recognition end; the sixth output end (VO6) is connected to the edge recognition end.

2. The anti-radiation FPGA embedded 28Gbps serial interface signal compensation circuit according to claim 1, characterized in that The input end of the main path signal circuit (104) includes a third input end (VI3), a fourth input end (VI4), and a main path control input end (SC); the main path control input end (SC) is a digital switch; the main path control input end (SC) includes seven input ends and seven output ends, and the input ends and output ends correspond one by one; the main path control input end (SC) is connected to the second control signal (CS2); the output end of the main path signal circuit (104) includes a third output end (VO3) and a fourth output end (VO4); the first receiving output end (RX1) is connected to the third input end (VI3); the second receiving output end (RX2) is connected to the fourth input end (VI4); the third output end (VO3) is connected to the seventh input end (VI7); the fourth output end (VO4) is connected to the eighth input end (VI8); The main path signal circuit (104) includes a first impedance matching resistor array, a second impedance matching resistor array, a first coupling capacitor (204), a second coupling capacitor (205), and a common mode voltage circuit; The first coupling capacitor (204) includes a first capacitor (C1) and the sixth terminal SC<5> of the main path control input end (SC); the first capacitor (C1) is in parallel with the sixth terminal SC<5> of the main path control input end (SC); The second coupling capacitor (205) includes a second capacitor (C2) and the sixth terminal SC<6> of the main path control input end (SC); the second capacitor (C2) is in parallel with the sixth terminal SC<6> of the main path control input end (SC); The first impedance matching resistor array (R1) includes five resistors connected in parallel; each resistor is in series with a pair of input and output ends of the main path control input end (SC); the five resistors are respectively in series with the first end to the fifth end of the main path control input end (SC) in sequence; the second impedance matching resistor array (R2) is the same as the first impedance matching resistor array (R1); The third input end (VI3) of the main path signal circuit (104) is connected to the input end of the first impedance matching resistor array; the third input end (VI3) of the main path signal circuit (104) is connected to one end of the first coupling capacitor (204); the other end of the first coupling capacitor (204) is connected to the third output end (VO3); The fourth input end (VI4) of the main path signal circuit (104) is connected to the input end of the second impedance matching resistor array; the fourth input end (VI4) of the main path signal circuit (104) is connected to one end of the second coupling capacitor (205); the other end of the second coupling capacitor (205) is connected to the fourth output end (VO4); The output ends of the first impedance matching resistor array and the second impedance matching resistor array are connected to the input end of the common mode voltage circuit (203); the common mode voltage circuit (203) is used to adjust the common mode terminal voltage of the main path signal circuit signal.

3. The signal compensation circuit for a 28 Gbps serial interface embedded in an anti-radiation FPGA according to claim 1, characterized in that, The input end of the equalization signal circuit (105) includes a first input end (VI1), a second input end (VI2), and an equalization control input end (EC); the equalization control input end (EC) is a digital switch; the equalization control input end (EC) includes sixteen input ends and sixteen output ends, and the input ends and the output ends correspond one by one; the equalization control input end (EC) is connected to a first control signal (CS1); the output end of the equalization signal circuit (105) includes a first output end (VO1) and a second output end (VO2); the first input end (VI1) is connected to a first receiving output end (RX1); The second input end (VI2) is connected to a second receiving output end (RX2); the first output end (VO1) is connected to a fifth input end (VI5); the second output end (VO2) is connected to a sixth input end (VI6); The equalization signal circuit (105) includes a first resistor array (302), a second resistor array (303), a third resistor array (305), and a fourth resistor array (306), a first input capacitor (C3), and a second input capacitor (C4); a first input terminal (VI1) of the equalization signal circuit (105) is connected to an input terminal of the first input capacitor (C3); an output terminal of the first input capacitor (C3) is respectively connected to an input terminal of the first resistor array, an input terminal of the second resistor array, and a first output terminal (VO1); a second input terminal (VI2) of the equalization signal circuit (105) is connected to an input terminal of the second input capacitor (C4); an output terminal of the second input capacitor (C4) is respectively connected to an input terminal of the third resistor array, an input terminal of the fourth resistor array, and a second output terminal (VO2) of the equalization signal circuit; an input terminal of the first resistor array (302) is connected to an input terminal of a parallel combination of a seventh resistor (R7) and an eighth resistor (R8); an output terminal of the parallel combination of the seventh resistor (R7) and the eighth resistor (R8) is connected to an input terminal of a fifth resistor (R5); an output terminal of the fifth resistor (R5) is connected to a drain of a PMOS switch transistor MP3; a third output terminal EC<2> of an equalization control input terminal (EC) is connected to a gate of the PMOS transistor MP3; an output terminal of the parallel combination of the seventh resistor (R7) and the eighth resistor (R8) is connected to an input terminal of a sixth resistor (R6); an output terminal of the sixth resistor (R6) is connected to a drain of a PMOS switch transistor MP4; a fourth output terminal EC<3> of the equalization control input terminal (EC) is connected to a gate of the PMOS transistor MP4; a source of the PMOS switch transistor MP4 is connected to a source of the PMOS transistor MP3; a source of the PMOS switch transistor MP4 and a source of the PMOS transistor MP3 are respectively connected to a drain of a PMOS switch transistor MP2; a source of the PMOS switch transistor MP4 and a source of the PMOS transistor MP3 are respectively connected to an input terminal of a fourth resistor (R4); a gate of the PMOS switch transistor MP2 is connected to a second output terminal EC<1> of the equalization control input terminal (EC); an output terminal of the fourth resistor (R4) is connected to a source of the PMOS switch transistor MP2; an output terminal of the fourth resistor (R4) and a source of the PMOS switch transistor MP2 are respectively connected to a drain of a PMOS switch transistor MP1; an output terminal of the fourth resistor (R4) and a source of the PMOS switch transistor MP2 are respectively connected to an input terminal of a third resistor (R3); a gate of the PMOS switch transistor MP1 is connected to a first output terminal EC<0> of the equalization control input terminal (EC); an output terminal of the third resistor (R3) is connected to a source of the PMOS switch transistor MP1; The source of the PMOS switch transistor MP1 is connected to an analog power supply terminal AVDD; The input end of the second resistor array (303) is connected to the input ends of the ninth resistor (R9) and the tenth resistor (R10) connected in parallel; the output ends of the ninth resistor (R9) and the tenth resistor (R10) connected in parallel are connected to the input end of the eleventh resistor (R11); the output end of the eleventh resistor (R11) is connected to the drain of the NMOS switch tube MN3; the output ends of the ninth resistor (R9) and the tenth resistor (R10) connected in parallel are connected to the input end of the twelfth resistor (R12); the output end of the twelfth resistor (R12) is connected to the drain of the NMOS switch tube MN4; the source of the NMOS switch tube MN3 is connected to the source of the NMOS switch tube MN4; the gate of the NMOS switch tube MN3 is connected to the fifth output end EC<4> of the equalization control input terminal (EC); the gate of the NMOS switch tube MN4 is connected to the eighth output end EC<7> of the equalization control input terminal (EC); the source of the NMOS switch tube MN3 and the source of the NMOS switch tube MN4 are connected to the drain of the NMOS switch tube MN2; the source of the NMOS switch tube MN3 and the source of the NMOS switch tube MN4 are connected to the input end of the thirteenth resistor (R13); the source of the NMOS switch tube MN2 is connected to the output end of the thirteenth resistor (R13); the gate of the NMOS switch tube MN2 is connected to the sixth output end EC<5> of the equalization control input terminal (EC); the source of the NMOS switch tube MN2 and the output end of the thirteenth resistor (R13) are respectively connected to the drain of the NMOS switch tube MN1; the source of the NMOS switch tube MN2 and the output end of the thirteenth resistor (R13) are respectively connected to the input end of the fourteenth resistor (R14); the source of the NMOS switch tube MN1 is connected to the output end of the fourteenth resistor (R14) and is grounded at the same time; the gate of the NMOS switch tube MN1 is connected to the seventh output end EC<6> of the equalization control input terminal (EC); the input end of the third resistor array (305) is connected to the input ends of the nineteenth resistor (R19) and the twentieth resistor (R20) connected in parallel; the output ends of the nineteenth resistor (R19) and the twentieth resistor (R20) connected in parallel are connected to the input end of the seventeenth resistor (R17); the output end of the seventeenth resistor (R17) is connected to the drain of the PMOS switch tube MP7; the eleventh output end EC<10> of the equalization control input terminal (EC) is connected to the gate of the PMOS tube MP7; the output ends of the nineteenth resistor (R19) and the twentieth resistor (R20) connected in parallel are connected to the input end of the eighteenth resistor (R18); the output end of the eighteenth resistor (R18) is connected to the drain of the PMOS switch tube MP8; the twelfth output end EC<11> of the equalization control input terminal (EC) is connected to the gate of the PMOS tube MP8; the source of the PMOS switch tube MP7 is connected to the source of the PMOS switch tube MP8; the source of the PMOS switch tube MP7 and the source of the PMOS switch tube MP8 are respectively connected to the drain of the PMOS switch tube MP6;The source electrodes of the PMOS switch transistor MP7 and the PMOS transistor MP8 are respectively connected to the input end of the sixteenth resistor (R16); the gate electrode of the PMOS switch transistor MP6 is connected to the tenth output end EC<9> of the equalization control input terminal (EC); the output end of the sixteenth resistor (R16) is connected to the source electrode of the PMOS switch transistor MP6; the output end of the sixteenth resistor (R16) and the source electrode of the PMOS switch transistor MP6 are respectively connected to the drain electrode of the PMOS switch transistor MP5; the output end of the sixteenth resistor (R16) and the source electrode of the PMOS switch transistor MP6 are respectively connected to the input end of the fifteenth resistor (R15); the gate electrode of the PMOS switch transistor MP5 is connected to the ninth output end EC<8> of the equalization control input terminal (EC); the output end of the fifteenth resistor (R15) is connected to the source electrode of the PMOS switch transistor MP5; the source electrode of the PMOS switch transistor MP5 is connected to the analog power supply terminal AVDD; the input end of the fourth resistor array (306) is connected to the input ends of the twenty-first resistor (R21) and the twenty-second resistor (R22) connected in parallel; the output ends of the twenty-first resistor (R21) and the twenty-second resistor (R22) connected in parallel are connected to the input end of the twenty-third resistor (R23); the output end of the twenty-third resistor (R23) is connected to the drain electrode of the NMOS switch transistor MN7; the output ends of the twenty-first resistor (R21) and the twenty-second resistor (R22) connected in parallel are respectively connected to the input ends of the twenty-fourth resistor (R24); the output end of the twenty-fourth resistor (R24) is connected to the drain electrode of the NMOS switch transistor MN8; the source electrodes of the NMOS switch transistor MN7 and the NMOS switch transistor MN8 are connected; the gate electrode of the NMOS switch transistor MN7 is connected to the thirteenth output end EC<12> of the equalization control input terminal (EC); the gate electrode of the NMOS switch transistor MN8 is connected to the sixteenth output end EC<15> of the equalization control input terminal (EC); the source electrodes of the NMOS switch transistor MN7 and the NMOS switch transistor MN8 are connected to the drain electrode of the NMOS switch transistor MN6; the source electrodes of the NMOS switch transistor MN7 and the NMOS switch transistor MN8 are connected to the input end of the twenty-fifth resistor (R25); the source electrode of the NMOS switch transistor MN6 is connected to the output end of the twenty-fifth resistor (R25); the gate electrode of the NMOS switch transistor MN6 is connected to the fourteenth output end EC<13> of the equalization control input terminal (EC); the source electrode of the NMOS switch transistor MN6 and the output end of the twenty-fifth resistor (R25) are respectively connected to the drain electrode of the NMOS switch transistor MN5; the source electrode of the NMOS switch transistor MN6 and the output end of the twenty-fifth resistor (R25) are respectively connected to the input end of the twenty-sixth resistor (R26); the source electrode of the NMOS switch transistor MN5 is connected to the output end of the twenty-sixth resistor (R26) and is grounded at the same time; the gate electrode of the NMOS switch transistor MN5 is connected to the fifteenth output end EC<14> of the equalization control input terminal (EC).; 4. The anti-radiation FPGA embedded 28Gbps serial interface signal compensation circuit according to claim 1, characterized in that The first signal superposition circuit (106) includes an enable control circuit (401), a first input pair of transistors (404), a second input pair of transistors (405), a first current source array (402), a second current source array (403), a first load resistor array (406), and a second load resistor array (407); The first input pair of transistors (404) includes an NMOS transistor MN11 and an NMOS transistor MN12; the fifth input terminal (VI5) of the first signal superposition circuit (106) is connected to the gate of MN11; the sixth input terminal (VI6) of the first signal superposition circuit (106) is connected to the gate of MN12; the source of NMOS transistor MN11 and the source of NMOS transistor MN12 are connected; the drain of MN11 is connected to the input terminal of the first load resistor array (406); the drain of MN12 is connected to the input terminal of the second load resistor array (407); The second input pair of transistors (405) includes an NMOS transistor MN13 and an NMOS transistor MN14; the seventh input terminal (VI7) of the first signal superposition circuit (106) is connected to the gate of MN13; the eighth input terminal (VI8) of the first signal superposition circuit (106) is connected to the gate of MN14; the source of NMOS transistor MN13 and the source of NMOS transistor MN14 are connected; the drain of MN13 is connected to the input terminal of the first load resistor array (406); the drain of MN14 is connected to the input terminal of the second load resistor array (407); The first load resistor array (406) includes a twenty-eighth resistor (R28), a PMOS switch transistor MP9, a PMOS switch transistor MP10, and a twenty-seventh resistor (R27); the input terminal of the first load resistor array (406) is simultaneously connected to the input terminal of the twenty-eighth resistor (R28), the input terminal of the twenty-seventh resistor (R27), and the fifth output terminal (VO5); the output terminal of the twenty-eighth resistor (R28) is connected to the drain of the PMOS switch transistor MP10; the source of the PMOS switch transistor MP10 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch transistor MP10 is connected to the second output terminal S1<1> of the first superposition control signal input terminal (S1); the output terminal of the twenty-seventh resistor (R27) is connected to the drain of the PMOS switch transistor MP9; the source of the PMOS switch transistor MP9 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch transistor MP9 is connected to the first output terminal S1<0> of the first superposition control signal input terminal (S1); The second load resistor array (407) includes a twenty-ninth resistor (R29), a PMOS switch transistor MP11, a PMOS switch transistor MP12, and a thirtieth resistor (R30); the input end of the second load resistor array (407) is simultaneously connected to the input end of the twenty-ninth resistor (R29), the input end of the thirtieth resistor (R30), and the sixth output end (VO6); the output end of the twenty-ninth resistor (R29) is connected to the drain of the PMOS switch transistor MP11; the source of the PMOS switch transistor MP11 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch transistor MP11 is connected to the second output end S1<1> of the first superimposed control signal input terminal (S1); the output end of the thirtieth resistor (R30) is connected to the drain of the PMOS switch transistor MP12; the source of the PMOS switch transistor MP12 is connected to the analog power supply terminal AVDD; the gate of the PMOS switch transistor MP12 is connected to the first output end S1<0> of the first superimposed control signal input terminal (S1); The first current source array includes four NMOS transistors; the sources of the four NMOS transistors are grounded respectively; the gate of each NMOS transistor is connected in series with an output end of the first superimposed control signal input terminal (S1); the gates of the four NMOS transistors are connected in series with the fifth to eighth output ends of the first superimposed control signal input terminal (S1) in sequence; the drains of the four NMOS transistors are connected in parallel and then connected to the source of the NMOS transistor MN11 and the source of the NMOS transistor MN12 respectively; The second current source array includes four NMOS transistors; the sources of the four NMOS transistors are grounded respectively; the gate of each NMOS transistor is connected in series with an output end of the first superimposed control signal input terminal (S1); the gates of the four NMOS transistors are connected in series with the ninth to twelfth output ends of the first superimposed control signal input terminal (S1) in sequence; the drains of the four NMOS transistors are connected in parallel and then connected to the source of the NMOS transistor MN13 and the source of the NMOS transistor MN14 respectively; The enabling control circuit includes an NMOS transistor MN9, an NMOS transistor MN10, and a PMOS switching transistor MP13; the first reference current input terminal (I1) is respectively connected to the drain of the NMOS transistor MN9 and the source of the PMOS switching transistor MP13; the source of the NMOS transistor MN9 is connected to the drain of the PMOS switching transistor MP13; the gate of the NMOS transistor MN9 is connected to the fourth input / output terminal S1<3> of the first superimposed control signal input terminal (S1); the gate of the PMOS switching transistor MP13 is connected to the third input / output terminal S1<2> of the first superimposed control signal input terminal (S1); the source of the NMOS transistor MN9 is connected to the drain of the NMOS transistor MN10; the source of the NMOS transistor MN10 is grounded; the gate of the NMOS transistor MN10 is connected to the third input / output terminal S1<2> of the first superimposed control signal input terminal (S1); the source of the NMOS transistor MN9 is respectively connected to the gates of four NMOS transistors of the first current source array; the source of the NMOS transistor MN9 is respectively connected to the gates of four NMOS transistors of the second current source array.

5. The anti-radiation FPGA embedded 28Gbps serial interface signal compensation circuit according to claim 4, wherein The anti-radiation FPGA embedded 28Gbps serial interface signal compensation circuit includes a second signal superposition circuit; the second signal superposition circuit superimposes the main path output signal and the equalization signal according to the control signal of the anti-radiation auxiliary circuit to obtain a superimposed signal; the first signal superposition circuit has the same structure as the second signal superposition circuit; the input of the second signal superposition circuit (107) includes a ninth input terminal (VI9), a tenth input terminal (VI10), an eleventh input terminal (VI11), a twelfth input terminal (VI12), a second reference current input terminal (I2) and a second superposition control signal input terminal (S2); the ninth input terminal (VI9) is connected to the first output terminal (VO1); the tenth input terminal (VI10) is connected to the second output terminal (VO2); the eleventh input terminal (VI11) is connected to the third output terminal (VO3); the twelfth input terminal (VI12) is connected to the fourth output terminal (VO4); the second superposition control signal input terminal (S2) is connected to the second control signal output terminal (EN2); the second reference current input terminal (I2) is connected to the second reference current output terminal (B2); the second superposition control signal input terminal (S2) is a 12-bit control signal, and the second superposition control signal input terminal (S2) includes 12 input terminals and 12 output terminals, and the input terminals and output terminals correspond one by one; the output of the second signal superposition circuit (107) is the seventh output terminal (VO7) and the eighth output terminal (VO8); the fifth output terminal (VO5), the sixth output terminal (VO6), the seventh output terminal (VO7) and the eighth output terminal (VO8) are sequentially connected to the input terminal of the data delay processing circuit; the data delay processing circuit delays the superimposed signals output by the first signal superposition circuit and the second signal superposition circuit, and inputs the delayed superimposed signals into the data recognition terminal and the edge recognition terminal respectively; the input of the data delay processing circuit includes a thirteenth input terminal (VI13), a fourteenth input terminal (VI14), a fifteenth input terminal (VI15) and a sixteenth input terminal (VI16); the output of the data delay processing circuit is the ninth output terminal (VO9) and the tenth output terminal (VO10); the ninth output terminal (VO9) is connected to the data recognition terminal; the tenth output terminal (VO10) is connected to the edge recognition terminal.

6. The anti-radiation FPGA embedded 28Gbps serial interface signal compensation circuit according to claim 2, characterized in that, The common-mode voltage circuit includes a first common-mode digital switch, a second common-mode digital switch and a third common-mode digital switch; the input terminals of the common-mode voltage circuit are respectively connected to the input terminals of the first common-mode digital switch, the second common-mode digital switch and the third common-mode digital switch; the output terminal of the first common-mode digital switch is connected to the 1.2V voltage; the output terminal of the second common-mode digital switch is connected to the 0.8V voltage; the output terminal of the third common-mode digital switch is connected to the ground; in the DC coupling scenario, the common-mode voltage circuit outputs and selects the 1.2V voltage mode or the grounded mode; in the AC coupling scenario, the common-mode voltage circuit outputs and selects to connect to the 0.8V voltage mode.

Images