Reconfigurable FFE equalization circuit based on multiphase clock serialization, Serdes transmitter and chip

Abstract

The invention provides a reconfigurable FFE equalization circuit based on multi-phase clock serialization, a Serdes transmitter and a chip, and the reconfigurable FFE equalization circuit based on multi-phase clock serialization comprises a multi-phase clock generation circuit which is used for receiving a differential voltage signal of an external clock source, generating a plurality of voltage signals with different phases, and outputting the voltage signals with different phases to the Serdes transmitter. A plurality of generated voltage signals with different phases are used as clock signals to be input into the reconfigurable FFE tap generation circuit; the reconfigurable FFE tap generation module is used for receiving multiple paths of parallel data signals input by an external signal source and serializing the multiple paths of parallel data signals based on the clock signal to generate a reconfigurable multi-tap signal; the generated multi-tap signal is used as the input of the multiplexing-driving circuit; and the multiplexing-driving circuit is used for serializing the multi-channel parallel multi-tap signals and transmitting the multi-channel parallel multi-tap signals to a channel. According to the invention, the number of reconfigurable taps is provided for different application scenes, and no extra delay unit is needed.

Description

Technical Field

[0001] The invention belongs to the field of electronic technology and relates to a reconfigurable FFE (Feed Forward Equalization) equalization circuit based on multi-phase clock serialization, a Serdes transmitter and a chip. Background Art

[0002] With the rapid development of applications such as artificial intelligence, big data, and autonomous driving, various application scenarios have an increasing demand for high-performance computing with high computing power and low power consumption and data centers with high bandwidth density. High-speed Serdes (Serializer-Reserializer) is widely used in data centers and high-performance computing. The transmitter is located at the transmitting end of the entire Serdes system, which converts low-speed parallel data into high-speed serial data and transmits it to the channel through the driving circuit. Although the use of Serdes technology has greatly improved the communication rate between data, it is still affected by many factors, such as skin effect, dielectric loss, reflection, noise, crosstalk, etc. Affected by these non-ideal factors, data transmission will be distorted, the bit error rate will increase, and signal integrity problems will be caused. In order to ensure the quality of signal transmission, the transmitter usually performs pre-distortion equalization on the signal before transmitting the data, that is, pre-enhancing the high-frequency component to offset the attenuation caused by channel loss.

[0003] Transmitter equalization usually adopts the feed-forward equalization (FFE) architecture, which is implemented as follows Figure 1 As shown. Its essence can be regarded as a finite impulse response filter (FIR), which delays the input data multiple times (T) during operation and treats the delayed data according to different weights (α -1 , α 0 , α 1 , …, α n ) are summed, the number of delayed data to be summed is called the number of taps, the delay length T is called the tap interval, and T is usually set to a fixed unit code element length 1UI (Unit Interval, code element length) so that the compensation point is set at the Nyquist frequency.

[0004] Usually, different delayed data are generated through the delay unit in the circuit, and the number of taps of the Serdes transmitter is determined during the circuit design, such as Figure 1 Therefore, when applied to channels with different losses, there may be problems of too many or insufficient taps, and the scope of application is greatly limited. At the same time, multiple delays for high-speed data will bring about greater power consumption and hardware overhead. Summary of the invention

[0005] In response to the technical problem in the prior art of generating different delay data based on delay units, the present invention provides a reconfigurable FFE equalization circuit, a Serdes transmitter and a chip based on multi-phase clock serialization, with the aim of providing a reconfigurable number of taps for different application scenarios without the need for additional delay units; at the same time, the system clock frequency is reduced, and the full-rate nodes in the circuit are reduced, thereby reducing the overall system power consumption.

[0006] The present invention is achieved through the following technical solutions: A reconfigurable FFE equalization circuit based on multi-phase clock serialization, comprising: A multi-phase clock generating circuit, used for receiving a differential voltage signal from an external clock source and generating a plurality of voltage signals with different phases, wherein the generated plurality of voltage signals with different phases are input as clock signals to a reconfigurable FFE tap generating circuit; A reconfigurable FFE tap generation module is used to receive multiple parallel data signals input from an external signal source, and to serialize the multiple parallel data signals based on the clock signal to generate a reconfigurable multi-tap signal; the generated multi-tap signal is used as an input of a multiplexing-driving circuit; Multiplexing-driving circuit, used to serialize multiple parallel multi-tap signals and transmit them to the channel.

[0007] Preferably, the multi-phase clock generation circuit comprises: a multi-phase delay generation module, a multi-phase injection locked ring oscillator, a frequency detector and a phase detector, and an operational amplifier Gm; The external clock source provides a differential voltage signal V INJ,P and V INJ,N The differential clock input terminals V INJP and V INJN connected to the first output terminal CKDL of the multi-phase delay generation module 0 , the second output terminal CKDL 1 , the third output terminal CKDL 2 , the fourth output terminal CKDL 3 , the fifth output terminal CKDL 4 , the sixth output terminal CKDL 5 , the seventh output terminal CKDL 6 , the eighth output terminal CKDL 7 respectively connected to the first input terminal CKDL of the multi-phase injection locked ring oscillator 0 , the second input terminal CKDL 1 , the third input terminal CKDL 2 , the fourth input terminal CKDL 3 , the fifth input terminal CKDL 4, the sixth input terminal CKDL 5 , the seventh input terminal CKDL 6 , the eighth input terminal CKDL 7 connected; the first output terminal CKR of the multi-phase injection locked ring oscillator 0 , the second output terminal CKR 45 , the third output terminal CKR 90 , the fourth output terminal CKR 135 , the fifth output terminal CKR 180 , the sixth output terminal CKR 225 , the seventh output terminal CKR 270 , the eighth output terminal CKR 315 respectively connected to the first output terminal CK of the multi-phase clock generating circuit 0 , the second output terminal CK 45 , the third output terminal CK 90 , the fourth output terminal CK 135 , the fifth output terminal CK 180 , the sixth output terminal CK 225 , the seventh output terminal CK 270 , the eighth output terminal CK 315 Connected; The first output terminal CKDL of the multi-phase delay generation module 0 , the second output terminal CKDL 1 , the third output terminal CKDL 2 , the fourth output terminal CKDL 3 , the fifth output terminal CKDL 4 , the sixth output terminal CKDL 5 , the seventh output terminal CKDL 6 , the eighth output terminal CKDL 7 The first input terminal CKDL of the frequency detector 0 , the second input terminal CKDL 1 , the third input terminal CKDL 2 , the fourth input terminal CKDL 3 , the fifth input terminal CKDL 4 , the sixth input terminal CKDL 5 , the seventh input terminal CKDL 6 , the eighth input terminal CKDL 7 Connected; the first differential output terminal V IP and the second differential output terminal V IN and the first differential input terminal V IP and the second differential input terminal V IN The output terminals of the operational amplifier Gm are connected to the bias voltage input terminals V ctrland the bias voltage input terminal V of the multi-phase injection-locked ring oscillator ctrl connect.

[0008] Furthermore, the reconfigurable FFE tap generation module and the multiplexing-driving module are both composed of 8 slices of the same structure, and the slices of the reconfigurable FFE tap generation module are signal-connected to the slices of the multiplexing-driving circuit in a one-to-one correspondence.

[0009] Furthermore, any slice of the reconfigurable FFE tap generation module includes a first reconfigurable serialization unit, a second reconfigurable serialization unit, and a third reconfigurable serialization unit; the MSB of the eight-way parallel data input by the external signal source 0 、MSB 1 、MSB 2 、MSB 3 、MSB 4 、MSB 5 、MSB 6 、MSB 7 respectively connected to the first input terminal MSB of the first reconfigurable serialization unit 0 , the second input terminal MSB 1 、The third input terminal MSB 2 , the fourth input terminal MSB 3 , the fifth input terminal MSB 4 , the sixth input terminal MSB 5 , the seventh input terminal MSB 6 , the eighth input terminal MSB 7 At the same time, the eight parallel data MSBs of the external signal source input 0 、MSB 1 、MSB 2 、MSB 3 、MSB 4 、MSB 5 、MSB 6 、MSB 7 respectively connected to the first input terminal MSB of the second reconfigurable serialization unit 0 , the second input terminal MSB 1 、The third input terminal MSB 2 , the fourth input terminal MSB 3 , the fifth input terminal MSB 4 , the sixth input terminal MSB 5 , the seventh input terminal MSB 6 、The eighth input terminal MSB 7 Connected; eight-way parallel data LSB of external signal source input 0 , LSB 1 , LSB 2 , LSB 3 , LSB4 , LSB 5 , LSB 6 , LSB 7 respectively connected to the first input terminal LSB of the third reconfigurable serialization unit 0 , the second input terminal LSB 1 , the third input terminal LSB 2 , the fourth input LSB 3 , the fifth input terminal LSB 4 , the sixth input terminal LSB 5 , the seventh input terminal LSB 6 , the eighth input terminal LSB 7 The ninth input terminal CK of any reconfigurable serialization unit 0 , the tenth input terminal CK 45 , the eleventh input terminal CK 90 , the twelfth input terminal CK 135 , the thirteenth input terminal CK 180 , the fourteenth input terminal CK 225 , the fifteenth input terminal CK 270 , the sixteenth input terminal CK 315 respectively connected to the first output terminal CK of the multi-phase clock generating circuit 0 , the second output terminal CK 45 , the third output terminal CK 90 , the fourth output terminal CK 135 , the fifth output terminal CK 180 , the sixth output terminal CK 225 , the seventh output terminal CK 270 , the eighth output terminal CK 315 One-to-one connection; any reconfigurable serialization unit has an output terminal T AP , T BP , T CP , T DP , T AN , T BN , T CN , T DN .

[0010] Furthermore, any reconfigurable serialization unit includes: first to eighth 4:1 multiplexers, first to eighth single pulse generation modules, and first to eighth 2:1 multiplexers; the input ends of the first to eighth 4:1 multiplexers sequentially receive eight parallel data input from an external signal source; the output of the first 4:1 multiplexer is connected to the input end of the first single pulse generation module, the output of the second 4:1 multiplexer is connected to the input end of the second single pulse generation module, and the output of the third 4:1 multiplexer is connected to the input end of the third single pulse generation module. The output of the fourth 4:1 multiplexer is connected to the input end of the fourth single pulse generating module, the output of the fifth 4:1 multiplexer is connected to the input end of the fifth single pulse generating module, the output of the sixth 4:1 multiplexer is connected to the input end of the sixth single pulse generating module, the output of the seventh 4:1 multiplexer is connected to the input end of the seventh single pulse generating module, and the output of the eighth 4:1 multiplexer is connected to the input end of the eighth single pulse generating module; the output end DP of the first single pulse generating module is connected to the input end of the DP of the first single pulse generating module. <0> and DN <0> The output terminal DP of the second single pulse generating module is connected to the first input terminal of the first 2:1 multiplexer and the first input terminal of the fifth 2:1 multiplexer respectively; <1> and DN <1> The output terminal DP of the third single pulse generating module is connected to the first input terminal of the second 2:1 multiplexer and the first input terminal of the sixth 2:1 multiplexer respectively; <2> and DN <2> The output terminal DP of the fourth single pulse generating module is connected to the first input terminal of the third 2:1 multiplexer and the first input terminal of the seventh 2:1 multiplexer respectively; <3> and DN <3> The output terminal DP of the fifth single pulse generating module is connected to the first input terminal of the fourth 2:1 multiplexer and the first input terminal of the eighth 2:1 multiplexer respectively; <4> and DN <4> The output terminal DP of the sixth single pulse generating module is connected to the second input terminal of the first 2:1 multiplexer and the second input terminal of the fifth 2:1 multiplexer respectively; <5> and DN <5> The output terminal DP of the seventh single pulse generating module is connected to the second input terminal of the second 2:1 multiplexer and the second input terminal of the sixth 2:1 multiplexer respectively; <6> and DN <6> The output terminal DP of the eighth single pulse generating module is connected to the second input terminal of the third 2:1 multiplexer and the second input terminal of the seventh 2:1 multiplexer respectively; <7> and DN <7>The first 2:1 multiplexer, the second 2:1 multiplexer, the third 2:1 multiplexer, and the fourth 2:1 multiplexer each have an output terminal T AP , T BP , T CP , T DP The fifth 2:1 multiplexer, the sixth 2:1 multiplexer, the seventh 2:1 multiplexer, and the eighth 2:1 multiplexer each have an output terminal T AN , T BN , T CN , T DN .

[0011] Further, any slice of the multiplex-drive circuit includes three groups of drive circuits with the same structure, and the three groups of drive circuits correspond to the first reconfigurable serialization unit, the second reconfigurable serialization unit, and the third reconfigurable serialization unit one by one; any drive circuit includes: a first MOS tube P 1 , the second MOS tube P 2 、The third MOS tube P 3 , the fourth MOS tube P 4 、The fifth MOS tube P 5 、The sixth MOS tube P 6 、The seventh MOS tube P 7 、The eighth MOS tube P 8 , tail current source; first MOS tube P 1 , the second MOS tube P 2 、The third MOS tube P 3 , the fourth MOS tube P 4 、The fifth MOS tube P 5 、The sixth MOS tube P 6 、The seventh MOS tube P 7 、The eighth MOS tube P 8 The source of the first MOS tube P is connected to the current source; 1 、The third MOS tube P 3 、The fifth MOS tube P 5 、The seventh MOS tube P 7 The drain of the FFE equalizer circuit is connected to the first output terminal OUT P , the second MOS tube P 2 , the fourth MOS tube P 4 , the sixth MOS tube P 6 、The eighth MOS tube P 8 The drain of the FFE equalizer circuit is connected to the second output terminal OUT N ; The first MOS tube P 1 、The third MOS tube P 3、The fifth MOS tube P 5 、The seventh MOS tube P 7 The gates of the corresponding reconfigurable serialization units are connected to the output terminals T AP , T BP , T CP , T DP One-to-one connection, the second MOS tube P 2 , the fourth MOS tube P 4 , the sixth MOS tube P 6 、The eighth MOS tube P 8 The gates of the corresponding reconfigurable serialization units are connected to the output terminals T AN , T BN , T CN , T DN One-to-one connection.

[0012] Furthermore, the current mode FFE equalization circuit further includes a first resistor R 1 , the second resistor R 2 、Load 2R L ; The first MOS tube P 1 、The third MOS tube P 3 、The fifth MOS tube P 5 、The seventh MOS tube P 7 The drain of the first resistor R 1 The first end of the second MOS tube P 2 , the fourth MOS tube P 4 , the sixth MOS tube P 6 、The eighth MOS tube P 8 The drain of the second resistor R 2 The first end of the first resistor R 1 The first end is connected to the load 2R L The first end of the second resistor R 2 The first end is connected to the load 2R L The second end of the first resistor R 1 The second end and the second resistor R 2 The second ends of are grounded.

[0013] Furthermore, the first MOS tube P 1 、The third MOS tube P 3 、The fifth MOS tube P 5 、The seventh MOS tube P 7 With the first resistor R 1 The output resistance formed by parallel connection is recorded as R, and the second MOS tube P 2 , the fourth MOS tube P 4 , the sixth MOS tube P 6 、The eighth MOS tube P 8With the second resistor R 2 The output resistance formed in parallel is recorded as R′, and R is equal to R′.

[0014] The present invention also provides a reconfigurable Serdes transmitter based on multi-phase clock serialization, characterized in that it includes the reconfigurable FFE equalization circuit based on multi-phase clock serialization as described above.

[0015] The present invention also provides a chip, comprising the reconfigurable FFE equalization circuit based on multi-phase clock serialization as described above.

[0016] Compared with the prior art, the present invention has the following beneficial effects: Compared with the Serdes transmitter equalization circuit with a fixed number of FFE taps, the present invention has the advantages of reconfigurable number of feedforward equalization taps and a large adjustment range of equalization strength. Specifically, unlike the current Serdes transmitter equalization circuit with a fixed number of taps, the present invention can reconfigure the input data of a total of multiple drivers, and can achieve a single tap with maximum output swing, as well as FFE settings with a minimum of two taps and a maximum of six taps. For application scenarios with low-loss channels, a smaller number of FFE taps can be allocated to achieve a higher output swing; for application scenarios with large losses, a larger number of FFE taps can be allocated to equalize heavier tailings.

[0017] Furthermore, compared with the existing Serdes transmitter equalization circuit, the present invention significantly reduces the system clock frequency and reduces the difficulty of circuit design. Specifically, as the wired communication rate gradually increases, most of the current architectures using full rate, half rate or quarter rate face the problem of high required system clock frequency and greater design difficulty. The present invention adopts a one-eighth rate architecture and performs sampling serialization through a multi-phase clock, reducing the maximum clock frequency required by the system to one-eighth of the Nyquist frequency, significantly reducing circuit design and manufacturing costs.

[0018] Furthermore, compared with the existing Serdes transmitter equalization circuit, the present invention has the advantage of low power consumption. Specifically, unlike most current architectures that use full rate, half rate or quarter rate, the present invention uses a one-eighth rate architecture to reduce the system's maximum clock frequency, thereby reducing system power consumption; at the same time, the present invention integrates the last level of serialization into the driving circuit, eliminates the high-speed nodes inside the system, and further reduces system power consumption.

[0019] The reconfigurable Serdes transmitter based on multi-phase clock serialization of the present invention realizes a higher signal rate and has higher energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 It is a schematic diagram of the structure of a traditional feedforward equalizer; Figure 2 It is a structural schematic diagram of a reconfigurable FFE equalization circuit based on multi-phase clock serialization of the present invention; Figure 3 It is a schematic diagram of a multi-phase clock generation circuit in the present invention; Figure 4 Schematic diagram of the structure of the reconfigurable FFE tap generation module in the present invention; Figure 5 It is a schematic diagram of the circuit of the reconfigurable serialization unit in the present invention; Figure 6 A signal timing diagram of an embodiment of the present invention; Figure 7 A schematic diagram of the connection relationship between the reconfigurable FFE tap generation module and the multiplexing-driving circuit in the present invention; Figure 8 This is a schematic diagram of the multiplexing-driving circuit in the present invention. DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0023] It should be noted that the process equipment or devices not specifically specified in the following embodiments are all conventional equipment or devices in the art.

[0024] It should be noted that the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. Moreover, unless otherwise specified, the numbering of each method step is only a convenient tool for identifying each method step, and is not intended to limit the order of arrangement of each method step or to define the scope of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the present invention without substantially changing the technical content.

[0025] In addition, it should be noted that the terms "first", "second", etc. of the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. The orientation or position relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention; in addition, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements.

[0026] refer to Figure 2 The reconfigurable FFE equalization circuit based on multi-phase clock serialization of the present invention adopts a current-mode structure, including: a multi-phase clock generation circuit, a reconfigurable FFE tap generation module, a multiplexing-driving module, a first resistor R 1 , the second resistor R 2 , load 2R L .

[0027] A multi-phase clock generating circuit, used for receiving a differential voltage signal from an external clock source, and generating a plurality of voltage signals with different phases to generate an accurate multi-phase clock, wherein the generated plurality of voltage signals with different phases are input as clock signals to a reconfigurable FFE tap generating circuit; A reconfigurable FFE tap generation module is used to receive multiple parallel data signals input from an external signal source, serialize the multiple parallel data signals based on the clock signal and adjust the relative delay to generate a reconfigurable multi-tap signal; the generated multi-tap signal is used as an input of a multiplexing-driving circuit; Multiplexing-driving circuit, used to serialize multiple parallel multi-tap signals and transmit them to the channel.

[0028] The multi-phase clock generation circuit has an external differential clock signal input terminal V INJP 、V INJN , the reconfigurable FFE tap generation module has an external parallel data input terminal MSB 0 、MSB 1 、MSB 2 、MSB 3 、MSB 4 、MSB 5 、MSB 6 、MSB 7 , LSB 0 , LSB 1 , LSB 2 , LSB 3 , LSB 4 , LSB 5 , LSB 6 , LSB 7 , multiplexing-driving module, the first resistor R 1 , the second resistor R 2 、Load 2R L Consists of drive unit, load 2R L Both ends are differential signal output terminals OUT P ,OUT N .

[0029] The external clock source provides a differential voltage signal V INJ,P and V INJ,N The external differential clock signal input terminal V INJP 、V INJN The 16 parallel data provided by the external signal source are connected to the first input terminal MSB of the reconfigurable FFE tap generation module 0 , the second input terminal MSB 1 、The third input terminal MSB 2 , the fourth input terminal MSB 3 , the fifth input terminal MSB 4 , the sixth input terminal MSB 5 , the seventh input terminal MSB 6 、The eighth input terminal MSB 7 , ninth input LSB 0 , tenth input LSB 1 , 11th input LSB 2 , 12th input LSB 3 , 13th input LSB 4, 14th input LSB 5 , 15th input LSB 6 , 16th input LSB 7 The first output terminal CK of the multi-phase clock generating circuit 0 , the second output terminal CK 45 , the third output terminal CK 90 , the fourth output terminal CK 135 , the fifth output terminal CK 180 , the sixth output terminal CK 225 , the seventh output terminal CK 270 , the eighth output terminal CK 315 respectively connected to the seventeenth input terminal CK of the reconfigurable FFE tap generation module 0 , the eighteenth input terminal CK 45 , the nineteenth input terminal CK 90 , the 20th input terminal CK 135 , the twenty-first input terminal CK 180 , the twenty-second input terminal CK 225 , the twenty-third input terminal CK 270 , the twenty-fourth input terminal CK 315 are connected.

[0030] The reconfigurable FFE tap generation module and the multiplexing-driving module are both composed of a number of slices of the same structure, wherein any reconfigurable FFE tap generation module slice corresponds to a multiplexing-driving circuit slice. Taking any of the slices as an example, the first output terminal T1 of the reconfigurable FFE tap generation module slice A(B、C、D)P , the second output terminal T1 A(B、C、D)N , the third output terminal T2 A(B、C、D)P , the fourth output terminal T2 A(B、C、D)N , the fifth output terminal T3 A(B、C、D)P , the sixth output terminal T3 A(B、C、D)N Respectively with the first input terminal T1 of the multiplexer-driver module A(B、C、D)P , the second input terminal T1 A(B、C、D)N , the third input terminal T2 A(B、C、D)P , the fourth input terminal T2 A(B、C、D)N , the fifth input terminal T3 A(B、C、D)P , the sixth input terminal T3 A(B、C、D)N The multiplexing-driving module serializes the input signal and transmits it to the channel. Taking any slice of the multiplexing-driving module as an example, the first driving circuit Drv 1 , the second driving circuit Drv 2 , the third driving circuit Drv 3 The first driving circuit Drv 1 The first output terminal of the second driving circuit Drv2 The first output terminal of the third driving circuit Drv 3 The first output terminal and the first resistor R 1 The first end of the first driving circuit Drv is connected; 1 The second output terminal of the second driving circuit Drv 2 The second output terminal of the third driving circuit Drv 3 The second output terminal and the second resistor R 2 The first end of the first resistor R 1 The first end is connected to the load 2R L The first end of the second resistor R 2 The first end is connected to the load 2R L The second end of the first resistor R 1 The second end and the second resistor R 2 The second ends of the first driving circuits Drv of all slices are grounded. 1 The first output terminal of the second driving circuit Drv 2 The first output terminal of the third driving circuit Drv 3 The first output terminal is connected in parallel with the first resistor R 1 The output resistance formed in series is recorded as R, and the first driving circuit Drv of all slices 1 The second output terminal of the second driving circuit Drv 2 The second output terminal of the third driving circuit Drv 3 The second output terminal is connected in parallel with the second resistor R 2 The output resistance formed in series is recorded as R′, and R is equal to R′.

[0031] The first resistor R 1 With the second resistor R 2 The specific resistance value of is selected according to the actual situation to achieve impedance matching. In a specific embodiment of the present invention, the first driving circuit Drv of all slices 1 The first output terminal of the second driving circuit Drv 2 The first output terminal of the third driving circuit Drv 3 The first output terminal is connected in parallel with the first resistor R 1 The output resistor R formed in series, and the first drive circuit Drv of all slices 1 The second output terminal of the second driving circuit Drv 2 The second output terminal of the third driving circuit Drv 3 The second output terminal is connected in parallel with the second resistor R 2 The output resistor R' formed in series is 50 ohms and the load is 2R L The size is 100 ohms.

[0032] refer to Figure 3 The multi-phase clock generation circuit includes: a multi-phase delay generation module, a multi-phase injection-locked ring oscillator, a frequency detector and a phase detector, and an operational amplifier Gm.

[0033] The external clock source provides a differential voltage signal V INJ,P and V INJ,N The differential clock input terminals V INJP and V INJN connected to the first output terminal CKDL of the multi-phase delay generation module 0 , the second output terminal CKDL 1 , the third output terminal CKDL 2 , the fourth output terminal CKDL 3 , the fifth output terminal CKDL 4 , the sixth output terminal CKDL 5 , the seventh output terminal CKDL 6 , the eighth output terminal CKDL 7 respectively connected to the first input terminal CKDL of the multi-phase injection locked ring oscillator 0 , the second input terminal CKDL 1 , the third input terminal CKDL 2 , the fourth input terminal CKDL 3 , the fifth input terminal CKDL 4 , the sixth input terminal CKDL 5 , the seventh input terminal CKDL 6 , the eighth input terminal CKDL 7 connected; the first output terminal CKR of the multi-phase injection locked ring oscillator 0 , the second output terminal CKR 45 , the third output terminal CKR 90 , the fourth output terminal CKR 135 , the fifth output terminal CKR 180 , the sixth output terminal CKR 225 , the seventh output terminal CKR 270 , the eighth output terminal CKR 315 After passing through the first buffer B0, the second buffer B1, the third buffer B2, the fourth buffer B3, the fifth buffer B4, the sixth buffer B5, the seventh buffer B6 and the eighth buffer B7, the first output terminal CK of the multi-phase clock generating circuit is connected to the first output terminal CK of the multi-phase clock generating circuit. 0 , the second output terminal CK 45 , the third output terminal CK 90 , the fourth output terminal CK 135 , the fifth output terminal CK 180 , the sixth output terminal CK 225 , the seventh output terminal CK 270, the eighth output terminal CK 315 are connected.

[0034] Furthermore, the first output terminal CKDL of the multi-phase delay generation module 0 , the second output terminal CKDL 1 , the third output terminal CKDL 2 , the fourth output terminal CKDL 3 , the fifth output terminal CKDL 4 , the sixth output terminal CKDL 5 , the seventh output terminal CKDL 6 , the eighth output terminal CKDL 7 The first input terminal CKDL of the frequency detector 0 , the second input terminal CKDL 1 , the third input terminal CKDL 2 , the fourth input terminal CKDL 3 , the fifth input terminal CKDL 4 , the sixth input terminal CKDL 5 , the seventh input terminal CKDL 6 , the eighth input terminal CKDL 7 The first differential output terminal V IP and the second differential output terminal V IN and the first differential input terminal V IP and the second differential input terminal V IN The output terminals of the operational amplifier Gm are connected to the bias voltage input terminals V ctrl and the bias voltage input terminal V of the multi-phase injection-locked ring oscillator ctrl connect.

[0035] In the locked state, the output signal frequency of the multi-phase injection locked ring oscillator is the same as the output clock frequency of the external clock source, and the oscillation frequency information of the multi-phase injection locked ring oscillator itself is lost. In the multi-phase delay generation module, there is a large phase error between adjacent voltage signals. The phase detector converts the signal CKDL 0 and CKDL 1 ,CKDL 2 and CKDL 3 ,CKDL 4 and CKDL 5 ,CKDL 6 and CKDL 7 If there is a phase error in the eight output signals, the first differential output terminal V IP and the second differential output terminal V INThe output voltage of the operational amplifier is different. IP and V IN The value of the first capacitor C1 of the output node is different, and the output terminal V ctrl size, and V ctrl The change is fed back to the multi-phase delay generation module and the multi-phase injection locked ring oscillator to adjust the current injected into the multi-phase delay generation module and the multi-phase injection locked ring oscillator, thereby changing the output signal frequency of the multi-phase delay generation module and the multi-phase injection locked ring oscillator, so that the intrinsic output signal frequency of the multi-phase delay generation module and the multi-phase injection locked ring oscillator is the same as the injection signal frequency of the external signal source. When the feedback system makes CKDL 0 ,CKDL 1 ,CKDL 2 ,CKDL 3 ,CKDL 4 ,CKDL 5 ,CKDL 6 ,CKDL 7 When the phase difference between them is the same, the operational amplifier output voltage V ctrl The multi-phase delay generation module and the multi-phase injection locked ring oscillator generate an output signal with a higher phase accuracy. Furthermore, due to the closed loop, the output signal CKR 0 , CKR 1 , CKR 2 CKRL 3 , CKR 4 , CKR 5 , CKR 6 , CKR 7 It has high phase accuracy; at the same time, since the multi-phase delay generation module does not form a closed loop, there is no accumulation of phase noise in the module, and the output signal CKDL of the multi-phase delay generation module 0 ,CKDL 1 ,CKDL 2 ,CKDL 3 ,CKDL 4 ,CKDL 5 ,CKDL 6 ,CKDL 7 The multi-phase injection locked ring oscillator is injected into the multi-phase injection locked ring oscillator respectively, and the multi-phase injection locked ring oscillator is further de-jittered to reduce the phase noise of the output signal of the multi-phase injection locked ring oscillator. 0 , the second output terminal CKR 45 , the third output terminal CKR 90, the fourth output terminal CKR 135 , the fifth output terminal CKR 180 , the sixth output terminal CKR 225 , the seventh output terminal CKR 270 , the eighth output terminal CKR 315 After passing through the AC-coupled first buffer B0, second buffer B1, third buffer B2, fourth buffer B3, fifth buffer B4, sixth buffer B5, seventh buffer B6 and eighth buffer B7, the signal duty cycle of 50% is restored and connected to the first output terminal CK of the multi-phase clock generating circuit respectively. 0 , the second output terminal CK 45 , the third output terminal CK 90 , the fourth output terminal CK 135 , the fifth output terminal CK 180 , the sixth output terminal CK 225 , the seventh output terminal CK 270 , the eighth output terminal CK 315 are connected.

[0036] For further reference, Figure 4 The reconfigurable FFE tap generation module is composed of 8 slices of the same structure. For any slice, the 16-way parallel data input from the external signal source is connected to the MSB of the first input terminal of the slice. 0 , the second input terminal MSB 1 、The third input terminal MSB 2 , the fourth input terminal MSB 3 , the fifth input terminal MSB 4 , the sixth input terminal MSB 5 , the seventh input terminal MSB 6 、The eighth input terminal MSB 7 , ninth input LSB 0 , tenth input LSB 1 , 11th input LSB 2 , 12th input LSB 3 , 13th input LSB 4 , 14th input LSB 5 , 15th input LSB 6 , 16th input LSB 7 The output terminal CK of the multi-phase clock generating circuit 0 , CK 45 , CK 90 , CK 135 , CK 180 , CK 225 , CK 270 , CK 315The seventeenth input terminal CK of the reconfigurable FFE tap generation module slice is respectively connected to 0 , the eighteenth input terminal CK 45 , the nineteenth input terminal CK 90 , the 20th input terminal CK 135 , the twenty-first input terminal CK 180 , the twenty-second input terminal CK 225 , the twenty-third input terminal CK 270 , the twenty-fourth input terminal CK 315 are connected.

[0037] Furthermore, any slice of the reconfigurable FFE tap generation module is composed of three reconfigurable serialization units. 0 、MSB 1 、MSB 2 、MSB 3 、MSB 4 、MSB 5 、MSB 6 、MSB 7 respectively connected to the first input terminal MSB of the first reconfigurable serialization unit 0 , the second input terminal MSB 1 、The third input terminal MSB 2 , the fourth input terminal MSB 3 , the fifth input terminal MSB 4 , the sixth input terminal MSB 5 , the seventh input terminal MSB 6 、The eighth input terminal MSB 7 connected; at the same time, the parallel data MSB 0 、MSB 1 、MSB 2 、MSB 3 、MSB 4 、MSB 5 、MSB 6 、MSB 7 respectively connected to the first input terminal MSB of the second reconfigurable serialization unit 0 , the second input terminal MSB 1 、The third input terminal MSB 2 , the fourth input terminal MSB 3 , the fifth input terminal MSB 4 , the sixth input terminal MSB 5 , the seventh input terminal MSB 6 、The eighth input terminal MSB 7 Connected. Parallel data LSB 0 , LSB 1 , LSB 2 , LSB 3, LSB 4 , LSB 5 , LSB 6 , LSB 7 respectively connected to the first input terminal LSB of the third reconfigurable serialization unit 0 , the second input terminal LSB 1 , the third input terminal LSB 2 , the fourth input LSB 3 , the fifth input terminal LSB 4 , the sixth input terminal LSB 5 , the seventh input terminal LSB 6 , the eighth input terminal LSB 7 The ninth input terminal CK of any reconfigurable serialization unit 0 , the tenth input terminal CK 45 , the eleventh input terminal CK 90 , the twelfth input terminal CK 135 , the thirteenth input terminal CK 180 , the fourteenth input terminal CK 225 , the fifteenth input terminal CK 270 , the sixteenth input terminal CK 315 respectively connected to the first output terminal CK of the multi-phase clock generating circuit 0 , the second output terminal CK 45 , the third output terminal CK 90 , the fourth output terminal CK 135 , the fifth output terminal CK 180 , the sixth output terminal CK 225 , the seventh output terminal CK 270 , the eighth output terminal CK 315 One-to-one connection; any reconfigurable serialization unit has an output terminal T AP , T BP , T CP , T DP , T AN , T BN , T CN , T DN .

[0038] refer to Figure 5 Taking any reconfigurable serialization unit as an example, the reconfigurable serialization unit includes: first to eighth 4:1 multiplexers, first to eighth single pulse generation modules, and 8:4 multiplexers; the 8:4 multiplexers are composed of first to eighth 2:1 multiplexers. The reconfigurable serialization unit has a first input terminal D <0> , the second input terminal D <1> , the third input terminal D <2> , the fourth input terminal D <3> , the fifth input terminal D <4>, the sixth input terminal D <5> , the seventh input terminal D <6> , the eighth input terminal D <7> , the ninth input terminal CK 0 , the tenth input terminal CK 45 , the eleventh input terminal CK 90 , the twelfth input terminal CK 135 , the thirteenth input terminal CK 180 , the fourteenth input terminal CK 225 , the fifteenth input terminal CK 270 , the sixteenth input terminal CK 315 Any 4:1 multiplexer has four input terminals, wherein the input terminals of the first to fourth 4:1 multiplexers are connected to the first input terminal D <0> , the second input terminal D <1> , the third input terminal D <2> , the fourth input terminal D <3> The fifth to eighth 4:1 multiplexer input terminals are respectively connected to the fifth input terminal D <4> , the sixth input terminal D <5> , the seventh input terminal D <6> , the eighth input terminal D <7> Any single pulse generating module has eight input terminals, wherein the input terminals of any single pulse generating module are respectively connected to the ninth input terminal CK 0 , the tenth input terminal CK 45 , the eleventh input terminal CK 90 , the twelfth input terminal CK 135 , the thirteenth input terminal CK 180 , the fourteenth input terminal CK 225 , the fifteenth input terminal CK 270 , the sixteenth input terminal CK 315 External input control signal S 0 , S 1 . Parallel data MSB 0 (LSB 0 )、MSB 1 (LSB 1 )、MSB 2 (LSB 2 )、MSB 3 (LSB 3 )、MSB 4 (LSB 4 )、MSB 5 (LSB 5 )、MSB 6 (LSB 6 )、MSB 7 (LSB 7) and the first input terminal D <0> , the second input terminal D <1> , the third input terminal D <2> , the fourth input terminal D <3> , the fifth input terminal D <4> , the sixth input terminal D <5> , the seventh input terminal D <6> , the eighth input terminal D <7> Control signal S 0 , S 1 Used to select different signals for operation. The output of the first 4:1 multiplexer is connected to the input end of the first single pulse generating module, the output of the second 4:1 multiplexer is connected to the input end of the second single pulse generating module, the output of the third 4:1 multiplexer is connected to the input end of the third single pulse generating module, the output of the fourth 4:1 multiplexer is connected to the input end of the fourth single pulse generating module, the output of the fifth 4:1 multiplexer is connected to the input end of the fifth single pulse generating module, the output of the sixth 4:1 multiplexer is connected to the input end of the sixth single pulse generating module, the output of the seventh 4:1 multiplexer is connected to the input end of the seventh single pulse generating module, and the output of the eighth 4:1 multiplexer is connected to the input end of the eighth single pulse generating module. The output terminal DP of the first single pulse generating module <0> and DN <0> The output terminal DP of the second single pulse generating module is connected to the first input terminal of the first 2:1 multiplexer and the first input terminal of the fifth 2:1 multiplexer respectively; <1> and DN <1> The output terminal DP of the third single pulse generating module is connected to the first input terminal of the second 2:1 multiplexer and the first input terminal of the sixth 2:1 multiplexer respectively; <2> and DN <2> The output terminal DP of the fourth single pulse generating module is connected to the first input terminal of the third 2:1 multiplexer and the first input terminal of the seventh 2:1 multiplexer respectively; <3> and DN <3> The output terminal DP of the fifth single pulse generating module is connected to the first input terminal of the fourth 2:1 multiplexer and the first input terminal of the eighth 2:1 multiplexer respectively; <4> and DN <4> The output terminal DP of the sixth single pulse generating module is connected to the second input terminal of the first 2:1 multiplexer and the second input terminal of the fifth 2:1 multiplexer respectively; <5> and DN <5> The output terminal DP of the seventh single pulse generating module is connected to the second input terminal of the second 2:1 multiplexer and the second input terminal of the sixth 2:1 multiplexer respectively; <6> and DN<6> The output terminal DP of the eighth single pulse generating module is connected to the second input terminal of the third 2:1 multiplexer and the second input terminal of the seventh 2:1 multiplexer respectively; <7> and DN <7> They are respectively connected to the second input terminal of the fourth 2:1 multiplexer and the second input terminal of the eighth 2:1 multiplexer.

[0039] refer to Figure 6 In one specific embodiment of the present invention, the control signal S 0 , S 1 The reconfigurable serialization unit selects the first (fifth) input terminal D <0> The data is ANDed to generate a single pulse. The first (fifth) single pulse generation module outputs the signal DP 0 DN 0 (DP 4 DN 4 ) and the rising edge of the input signal CK 0 The rising edge is aligned with the falling edge of the input signal CK 180 Under the control of the above signal, the output result of the single pulse generation module is a single pulse signal with a width of one unit pulse width and a spacing of seven unit pulse widths. Similar to this embodiment, the second (sixth), third (seventh), and fourth (eighth) single pulse generation modules output signals DP 1 and DN 1 (DP 5 and DN 5 )、DP 2 and DN 2 (DP 6 and DN 6 )、DP 3 and DN 3 (DP 7 and DN 7 ) with the rising and falling edges of CK 45 and CK 225 , CK 90 and CK 270 , CK 135 and CK 315 Align. Single pulse generation module output terminal DP <0:7> and DN <0:7> 8:4 multiplexer input DP <0:7> and DN <0:7> In this embodiment, DP 0 (DN 0 ) and DP 4 (DN 4 ) through the 8:4 multiplexer input, and the 8:4 multiplexer output is signal TAP (T AN ). Under the control of the above signal, the output result of the 8:4 multiplexer is T AP is a single pulse signal with a width of one unit pulse width and a spacing of three unit pulse widths. Similar to this embodiment, DP 1 (DN 1 ) and DP 5 (DN 5 )、DP 2 (DN 2 ) and DP 6 (DN 6 )、DP 3 (DN 3 ) and DP 7 (DN 7 ) through the 8:4 multiplexer input, and the 8:4 multiplexer output is signal T BP (T BN )、T CP (T CN )、T DP (T DN ). That is, the first 2:1 multiplexer, the second 2:1 multiplexer, the third 2:1 multiplexer, and the fourth 2:1 multiplexer each have an output terminal T AP , T BP , T CP , T DP The fifth 2:1 multiplexer, the sixth 2:1 multiplexer, the seventh 2:1 multiplexer, and the eighth 2:1 multiplexer each have an output terminal T AN , T BN , T CN , T DN It should be noted that the relative phase relationship between signals described in this embodiment is only exemplary, and actual use cases must be based on what can be implemented by ordinary technicians in this field.

[0040] The 8 reconfigurable FFE tap generation module slices are connected to the multiplexer-driving circuit slices respectively, referring to Figure 7 Taking any of the slices as an example, the first output terminal T1 of the FFE tap generation module can be reconstructed A(B、C、D)P , the second output terminal T1 A(B、C、D)N , the third output terminal T2 A(B、C、D)P , the fourth output terminal T2 A(B、C、D)N , the fifth output terminal T3 A(B、C、D)P , the sixth output terminal T3 A(B、C、D)N Respectively with the first input terminal T1 of the multiplexer-driver module A(B、C、D)P , the second input terminal T1 A(B、C、D)N , the third input terminal T2 A(B、C、D)P, the fourth input terminal T2 A(B、C、D)N , the fifth input terminal T3 A(B、C、D)P , the sixth input terminal T3 A(B、C、D)N The multiplexing-driver module serializes the input signal and transmits it to the channel.

[0041] refer to Figure 8 The multiplexer-driver circuit (MUX-Driver) is composed of 8 slices with the same structure. Any slice contains three sets of driver circuits with the same structure to generate PAM-4 multi-level modulation signals. Taking any driver circuit as an example, the circuit consists of the first MOS tube P 1 , the second MOS tube P 2 、The third MOS tube P 3 , the fourth MOS tube P 4 、The fifth MOS tube P 5 , the sixth MOS tube P 6 、The seventh MOS tube P 7 、The eighth MOS tube P 8 , and the tail current source form a de-emphasis FFE unit. The first MOS tube P 1 , the second MOS tube P 2 、The third MOS tube P 3 , the fourth MOS tube P 4 、The fifth MOS tube P 5 , the sixth MOS tube P 6 、The seventh MOS tube P 7 、The eighth MOS tube P 8 The source of the first MOS tube P is connected to a current source, and the amplitude modulation of different slice taps is achieved by adjusting the size of the tail current source. 1 、The third MOS tube P 3 、The fifth MOS tube P 5 、The seventh MOS tube P 7 The drain is connected to the first output terminal OUT P , the second MOS tube P 2 , the fourth MOS tube P 4 , the sixth MOS tube P 6 、The eighth MOS tube P 8 The drain is connected to the second output terminal OUT N . The first MOS tube P 1 、The third MOS tube P 3 、The fifth MOS tube P 5 、The seventh MOS tube P 7 The gates are respectively used as T AP , T BP , T CP , T DP The input end of the second MOS tube P 2 , the fourth MOS tube P4 , the sixth MOS tube P 6 、The eighth MOS tube P 8 The gates are respectively used as T AN , T BN , T CN , T DN The first MOS tube P 1 、The third MOS tube P 3 、The fifth MOS tube P 5 、The seventh MOS tube P 7 According to the input terminal T AP , T BP , T CP , T DP The signal is turned on or off in turn, and T AP , T BP , T CP , T DP The four data paths are serialized into one. Similarly, the second MOS tube P 2 , the fourth MOS tube P 4 , the sixth MOS tube P 6 、The eighth MOS tube P 8 According to the input terminal T AN , T BN , T CN , T DN The signal is turned on or off in turn, and T AN , T BN , T CN , T DN Four data paths are serialized into one path. This structure combines high-speed serialization with the drive circuit, reduces the number of high-speed nodes inside the circuit, increases the internal bandwidth of the circuit and reduces the overall circuit power consumption. Taking any of the slices as an example, the first drive unit Drv 1 The first output terminal and the second driving unit Drv 2 The first output terminal of the third driving unit Drv 3 The first output terminal and the first resistor R 1 The first end of the first driving unit Drv 1 The second output terminal of the second drive unit Drv 2 The second output terminal of the third driving unit Drv 3 The second output terminal and the second resistor R 2 The first end of the first resistor R 1 The first end is connected to the load 2R L The first end of the second resistor R 2 The first end is connected to the load 2R L The second end of the first resistor R 1 The second end of the second resistor R 2The second ends of are grounded.

[0042] Although specific embodiments of the present invention are described above, those skilled in the art should understand that these are merely examples and that various changes or modifications may be made to the embodiments without departing from the principles and essence of the present invention. The scope of protection of the present invention is limited only by the appended claims.

Claims

1. A reconfigurable FFE equalization circuit based on multi-phase clock serialization, characterized in that: include: A multi-phase clock generating circuit, used for receiving a differential voltage signal from an external clock source and generating a plurality of voltage signals with different phases, wherein the generated plurality of voltage signals with different phases are input as clock signals to a reconfigurable FFE tap generating circuit; A reconfigurable FFE tap generation module, used for receiving a plurality of parallel data signals inputted from an external signal source, and serializing the plurality of parallel data signals based on the clock signal to generate a reconfigurable multi-tap signal; The generated multi-tap signal is used as an input of a multiplexing-driving circuit; Multiplexing-driving circuit, used to serialize multiple parallel multi-tap signals and transmit them to the channel.

2. The reconfigurable FFE equalization circuit based on multi-phase clock serialization according to claim 1, characterized in that: The multi-phase clock generation circuit comprises: a multi-phase delay generation module, a multi-phase injection locked ring oscillator, a frequency and phase detector and an operational amplifier Gm; The external clock source provides a differential voltage signal V INJ,P and V INJ,N The differential clock input terminals V INJP and V INJN The first output terminal CKDL0, the second output terminal CKDL1, the third output terminal CKDL2, the fourth output terminal CKDL3, the fifth output terminal CKDL4, the sixth output terminal CKDL5, the seventh output terminal CKDL6, and the eighth output terminal CKDL7 of the multi-phase delay generating module are respectively connected to the first input terminal CKDL0, the second input terminal CKDL1, the third input terminal CKDL2, the fourth input terminal CKDL3, the fifth input terminal CKDL4, the sixth input terminal CKDL5, the seventh input terminal CKDL6, and the eighth input terminal CKDL7 of the multi-phase injection locked ring oscillator; the first output terminal CKR0, the second output terminal CKR 45 , the third output terminal CKR 90 , the fourth output terminal CKR 135 , the fifth output terminal CKR 180 , the sixth output terminal CKR 225 , the seventh output terminal CKR 270 , the eighth output terminal CKR 315 The first output terminal CK0 and the second output terminal CK 45 , the third output terminal CK 90 , the fourth output terminal CK 135 , the fifth output terminal CK 180 , the sixth output terminal CK 225 , the seventh output terminal CK 270 , the eighth output terminal CK 315 Connected; The first output terminal CKDL0, the second output terminal CKDL1, the third output terminal CKDL2, the fourth output terminal CKDL3, the fifth output terminal CKDL4, the sixth output terminal CKDL5, the seventh output terminal CKDL6, and the eighth output terminal CKDL7 of the multi-phase delay generation module are respectively connected to the first input terminal CKDL0, the second input terminal CKDL1, the third input terminal CKDL2, the fourth input terminal CKDL3, the fifth input terminal CKDL4, the sixth input terminal CKDL5, the seventh input terminal CKDL6, and the eighth input terminal CKDL7 of the frequency detector; the first differential output terminal V IP and the second differential output terminal V IN and the first differential input terminal V IP and the second differential input terminal V IN The output terminals of the operational amplifier Gm are connected to the bias voltage input terminals V ctrl and the bias voltage input terminal V of the multi-phase injection-locked ring oscillator ctrl connect.

3. The reconfigurable FFE equalization circuit based on multi-phase clock serialization according to claim 2, characterized in that: The reconfigurable FFE tap generation module and the multiplexing-driving module are both composed of 8 slices with the same structure, and the slices of the reconfigurable FFE tap generation module are signal-connected with the slices of the multiplexing-driving circuit in a one-to-one correspondence.

4. The reconfigurable FFE equalization circuit based on multi-phase clock serialization according to claim 3, characterized in that: Any slice of the reconfigurable FFE tap generation module includes a first reconfigurable serialization unit, a second reconfigurable serialization unit, and a third reconfigurable serialization unit; the eight parallel data MSB0, MSB1, MSB2, MSB3, MSB4, MSB5, MSB6, and MSB7 input by the external signal source are respectively connected to the first input terminal MSB0, the second input terminal MSB1, the third input terminal MSB2, the fourth input terminal MSB3, the fifth input terminal MSB4, the sixth input terminal MSB5, the seventh input terminal MSB6, and the eighth input terminal MSB7 of the first reconfigurable serialization unit; at the same time, the eight parallel data MSB0, MSB1, MSB2, MSB3, MSB4, MSB5, MSB6, and MSB7 input by the external signal source are respectively connected to the second reconfigurable serialization unit. The first input terminal MSB0, the second input terminal MSB1, the third input terminal MSB2, the fourth input terminal MSB3, the fifth input terminal MSB4, the sixth input terminal MSB5, the seventh input terminal MSB6, and the eighth input terminal MSB7 of the reconfigurable serialization unit are connected; the eight parallel data LSB0, LSB1, LSB2, LSB3, LSB4, LSB5, LSB6, and LSB7 input by the external signal source are respectively connected to the first input terminal LSB0, the second input terminal LSB1, the third input terminal LSB2, the fourth input terminal LSB3, the fifth input terminal LSB4, the sixth input terminal LSB5, the seventh input terminal LSB6, and the eighth input terminal LSB7 of the third reconfigurable serialization unit; the ninth input terminal CK0 and the tenth input terminal CK 45 , the eleventh input terminal CK 90 , the twelfth input terminal CK 135 , the thirteenth input terminal CK 180 , the fourteenth input terminal CK 225 , the fifteenth input terminal CK 270 , the sixteenth input terminal CK 315 The first output terminal CK0 and the second output terminal CK 45 , the third output terminal CK 90 , the fourth output terminal CK 135 , the fifth output terminal CK 180 , the sixth output terminal CK 225 , the seventh output terminal CK 270 , the eighth output terminal CK 315 One-to-one connection; any reconfigurable serialization unit has an output terminal T AP 、T BP 、T CP 、T DP 、T AN 、T BN 、T CN 、T DN .

5. The reconfigurable FFE equalization circuit based on multi-phase clock serialization according to claim 4, characterized in that: Any reconfigurable serialization unit includes: first to eighth 4:1 multiplexers, first to eighth single pulse generation modules, and first to eighth 2:1 multiplexers; the input ends of the first to eighth 4:1 multiplexers sequentially receive eight parallel data input from an external signal source; the output of the first 4:1 multiplexer is connected to the input end of the first single pulse generation module, the output of the second 4:1 multiplexer is connected to the input end of the second single pulse generation module, and the output of the third 4:1 multiplexer is connected to the input end of the third single pulse generation module. The output of the fourth 4:1 multiplexer is connected to the input end of the fourth single pulse generating module, the output of the fifth 4:1 multiplexer is connected to the input end of the fifth single pulse generating module, the output of the sixth 4:1 multiplexer is connected to the input end of the sixth single pulse generating module, the output of the seventh 4:1 multiplexer is connected to the input end of the seventh single pulse generating module, and the output of the eighth 4:1 multiplexer is connected to the input end of the eighth single pulse generating module; the output end DP of the first single pulse generating module ... <0> and DN <0> The output terminal DP of the second single pulse generating module is connected to the first input terminal of the first 2:1 multiplexer and the first input terminal of the fifth 2:1 multiplexer respectively; <1> and DN <1> The output terminal DP of the third single pulse generating module is connected to the first input terminal of the second 2:1 multiplexer and the first input terminal of the sixth 2:1 multiplexer respectively; <2> and DN <2> The output terminal DP of the fourth single pulse generating module is connected to the first input terminal of the third 2:1 multiplexer and the first input terminal of the seventh 2:1 multiplexer respectively; <3> and DN <3> The output terminal DP of the fifth single pulse generating module is connected to the first input terminal of the fourth 2:1 multiplexer and the first input terminal of the eighth 2:1 multiplexer respectively; <4> and DN <4> The output terminal DP of the sixth single pulse generating module is connected to the second input terminal of the first 2:1 multiplexer and the second input terminal of the fifth 2:1 multiplexer respectively; <5> and DN <5> The output terminal DP of the seventh single pulse generating module is connected to the second input terminal of the second 2:1 multiplexer and the second input terminal of the sixth 2:1 multiplexer respectively; <6> and DN <6> The output terminal DP of the eighth single pulse generating module is connected to the second input terminal of the third 2:1 multiplexer and the second input terminal of the seventh 2:1 multiplexer respectively; <7> and DN <7> The first 2:1 multiplexer, the second 2:1 multiplexer, the third 2:1 multiplexer, and the fourth 2:1 multiplexer each have an output terminal T AP 、T BP 、T CP 、T DP The fifth 2:1 multiplexer, the sixth 2:1 multiplexer, the seventh 2:1 multiplexer, and the eighth 2:1 multiplexer each have an output terminal T AN 、T BN 、T CN 、T DN .

6. The reconfigurable FFE equalization circuit based on multi-phase clock serialization according to claim 4, characterized in that: Any slice of the multiplexing-driving circuit includes three groups of driving circuits with the same structure, and the three groups of driving circuits correspond to the first reconfigurable serialization unit, the second reconfigurable serialization unit, and the third reconfigurable serialization unit one by one; any driving circuit includes: a first MOS tube P1, a second MOS tube P2, a third MOS tube P3, a fourth MOS tube P4, a fifth MOS tube P5, a sixth MOS tube P6, a seventh MOS tube P7, an eighth MOS tube P8, and a tail current source; the source electrodes of the first MOS tube P1, the second MOS tube P2, the third MOS tube P3, the fourth MOS tube P4, the fifth MOS tube P5, the sixth MOS tube P6, the seventh MOS tube P7, and the eighth MOS tube P8 are connected to the current source; the drain electrodes of the first MOS tube P1, the third MOS tube P3, the fifth MOS tube P5, and the seventh MOS tube P7 are connected to the first output terminal OUT of the FFE equalization circuit P The drains of the second MOS transistor P2, the fourth MOS transistor P4, the sixth MOS transistor P6, and the eighth MOS transistor P8 are connected to the second output terminal OUT of the FFE equalization circuit. N The gates of the first MOS transistor P1, the third MOS transistor P3, the fifth MOS transistor P5, and the seventh MOS transistor P7 are respectively connected to the output terminals T of the corresponding reconfigurable serialization units. AP 、T BP 、T CP 、T DP The gates of the second MOS transistor P2, the fourth MOS transistor P4, the sixth MOS transistor P6, and the eighth MOS transistor P8 are connected one by one to the output terminal T of the corresponding reconfigurable serialization unit. AN 、T BN 、T CN 、T DN One-to-one connection.

7. The reconfigurable FFE equalization circuit based on multi-phase clock serialization according to claim 6, characterized in that: The current mode FFE equalization circuit also includes a first resistor R1, a second resistor R2, a load 2R L The drains of the first MOS tube P1, the third MOS tube P3, the fifth MOS tube P5, and the seventh MOS tube P7 are all connected to the first end of the first resistor R1; the drains of the second MOS tube P2, the fourth MOS tube P4, the sixth MOS tube P6, and the eighth MOS tube P8 are all connected to the first end of the second resistor R2; the first end of the first resistor R1 is also connected to the load 2R L The first end of the second resistor R2 is connected to the load 2R L The second end of the first resistor R1 and the second end of the second resistor R2 are both grounded.

8. The reconfigurable FFE equalization circuit based on multi-phase clock serialization according to claim 7, characterized in that: The output resistance formed by connecting the first MOS transistor P1, the third MOS transistor P3, the fifth MOS transistor P5, the seventh MOS transistor P7 in parallel with the first resistor R1 is recorded as R, and the output resistance formed by connecting the second MOS transistor P2, the fourth MOS transistor P4, the sixth MOS transistor P6, the eighth MOS transistor P8 in parallel with the second resistor R2 is recorded as R′, and R is equal to R′.

9. A reconfigurable SerDes transmitter based on multi-phase clock serialization, characterized in that: A reconfigurable FFE equalization circuit based on multi-phase clock serialization comprising any one of claims 1-8.

10. A chip, characterized in that: A reconfigurable FFE equalization circuit based on multi-phase clock serialization comprising any one of claims 1-8.

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