DAC gain modulation circuit

Abstract

The invention discloses a DAC (Digital-to-Analog Converter) gain modulation circuit, which can realize flexible adjustment of output gains of a multi-channel DAC, and each channel can be adjusted by using an independent resistor and also can be adjusted by selecting a single resistor. Compared with a conventional DAC circuit using a single resistor for adjustment, the circuit can independently adjust the output amplitude of the multi-channel DAC, reduces additional external channel gain adjusting devices needed by a user, and is convenient to switch and use in various application modes such as interleaving, independence and modulation. Meanwhile, by adjusting the internal resistance proportion, the output current proportion of each channel can be flexibly adjusted, and the circuit has the advantages of being simple in structure, low in channel error, flexible in modulation and the like, and can be applied to design of high-precision multi-channel current type DAC, DDS and other devices.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a DAC gain modulation circuit. Background Art

[0002] DAC (digital-to-analog converter) is a digital-to-analog signal conversion circuit, which is divided into voltage type and current type according to the output. The current type is most widely used in high-precision applications. In the field of signal modulation applications, multi-channel products such as two-channel and four-channel are usually required, and there are strict requirements for channel gain consistency and flexible adjustment. To solve this problem, a bandgap reference is usually used inside the circuit to make multiple current mirrors for the channels. When the mirror current is adjusted independently, the gain is controlled. However, the channel matching accuracy is poor, and the total current output range cannot be adjusted independently when the channel is used independently, which has great limitations. Summary of the invention

[0003] The object of the present invention is to provide a DAC gain modulation circuit to solve the problems in the background technology.

[0004] In order to solve the above technical problems, the present invention provides a DAC gain modulation circuit, comprising:

[0005] A first operational amplifier, a second operational amplifier, a third operational amplifier, a first PMOS tube 11, a second PMOS tube 12, a third PMOS tube 13, a fourth PMOS tube 14, a fifth PMOS tube 21, a sixth PMOS tube 22, a seventh PMOS tube 23, an eighth PMOS tube 24, a ninth PMOS tube 30, a tenth PMOS tube 31, a first NMOS tube 34, a second NMOS tube 36, a third NMOS tube 37, a first resistor 15, a second resistor 25, a third resistor 32, and a fourth resistor 35;

[0006] The positive input terminal of the first operational amplifier is connected to the reference voltage Vref, the negative input terminal is connected to the first end of the first resistor, and the output terminal outputs a bias voltage bias1 to the gate terminal of the first PMOS tube, the gate terminal of the second PMOS tube, and the gate terminal of the ninth PMOS tube;

[0007] The second operational amplifier has a positive input terminal connected to a reference signal Vref, a negative input terminal connected to a first terminal of a second resistor, and an output terminal outputting a bias voltage bias3 to a gate terminal of a fifth PMOS tube and a gate terminal of a sixth PMOS tube;

[0008] The third operational amplifier has a positive input terminal connected to a reference voltage Vref, a negative input terminal connected to a first terminal of a third resistor, and an output terminal connected to a gate terminal of the first NMOS transistor and a gate terminal of the second NMOS transistor at the same time; Vref is a reference voltage provided by a reference circuit;

[0009] The source end of the first PMOS tube is connected to VDD, and the drain end is connected to the source end of the third PMOS tube; the source end of the second PMOS tube is connected to VDD, and the drain end is connected to the source end of the fourth PMOS tube; the drain end of the third PMOS tube is connected to the first end of the first resistor, and the drain end of the fourth PMOS tube outputs a reference current Iref1, the gate end of the third PMOS tube and the gate end of the fourth PMOS tube are both connected to the bias voltage bias2, and the second end of the first resistor is connected to GND;

[0010] The source end of the fifth PMOS tube is connected to VDD, and the drain end is connected to the source end of the seventh PMOS tube; the source end of the sixth PMOS tube is connected to VDD, and the drain end is connected to the source end of the eighth PMOS tube; the drain end of the seventh PMOS tube is connected to the first end of the second resistor, and the drain end of the eighth PMOS tube outputs a reference current Iref2, the gate end of the seventh PMOS tube and the gate end of the eighth PMOS tube are connected to a bias voltage bias2, and the second end of the second resistor is connected to GND; bias2 is a bias voltage provided by the reference circuit;

[0011] The source end of the ninth PMOS tube is connected to VDD, the drain end is connected to the source end of the tenth PMOS tube, and the drain end of the tenth PMOS tube is connected to the first end of the third resistor; the source end of the first NMOS tube is connected to GND, and the drain end is connected to the second end of the third resistor; the source end of the second NMOS tube is connected to GND, and the drain end is connected to the second end of the fourth resistor, and the first end of the fourth resistor is connected to the drain end of the seventh PMOS tube;

[0012] The source end of the third NMOS tube is connected to GND, the drain end is connected to the output end of the third operational amplifier, and the gate end is connected to the signal sel.

[0013] In one embodiment, the first resistor and the second resistor are modulation resistors external to the device, and the first operational amplifier and the second operational amplifier respectively convert the reference voltage of the first channel and the second channel into a reference current. When the gain of each channel is modulated independently, the function selection signal sel is 1, at which time the third NMOS tube is turned on and the second NMOS tube is turned off. There is no current path on the fourth resistor, and the gain of each channel is independently modulated according to the external resistor. Iref1 of the first channel is Vref / R15, and Iref2 of the second channel is Vref / R25; R15 is the resistance value of the first resistor, and R25 is the resistance value of the second resistor.

[0014] In one implementation, when the function selection signal sel is 0, the external port B is suspended without connecting the second resistor, the gain modulation circuit works, the third operational amplifier clamps the voltage of the node C and the external port B to the voltage Vref, the currents on the second PMOS tube, the fourth PMOS tube, the sixth PMOS tube, and the eighth PMOS tube are the same, at this time Iref1=Iref2=Vref / R15, and the gains of the first channel and the second channel are both adjusted by the first resistor; wherein the external port B is the common connection end of the negative input terminal of the second operational amplifier, the drain terminal of the seventh PMOS tube, and the first end of the fourth resistor, and the node C is the common connection point of the drain terminal of the tenth PMOS tube, the negative input terminal of the third operational amplifier, and the first end of the third resistor.

[0015] In one embodiment, when a single resistor is adjusted, the first NMOS transistor and the second NMOS transistor adjust the proportional range within the working range of the transistor saturation region. At this time, the resistance value R32 of the third resistor and the resistance value R35 of the fourth resistor need to be changed at the same time, so that the ratio of Iref1 and Iref2 is equal to R32 / R35.

[0016] In one implementation, the sizes of the first PMOS tube, the second PMOS tube, the ninth PMOS tube, the fifth and sixth PMOS tubes, and the sixth PMOS tube all need to be consistent, the sizes of the third PMOS tube, the fourth PMOS tube, the tenth PMOS tube, the seventh PMOS tube, and the eighth PMOS tube all need to be consistent, and the sizes of the third resistor and the fourth resistor all need to be consistent.

[0017] A DAC gain modulation circuit provided by the present invention can select, through switch control, to use an independent external resistor to adjust the gain of each channel or to use a single resistor to adjust the gain of all channels. At the same time, it can also realize rapid adjustment of the total current ratio of different channel outputs through digital control or adjustment of the internal resistance ratio. It has the characteristics of simple structure, convenient use, high adjustment accuracy, etc., can be flexibly switched between interleaved or independent channel modes, and can be applied to the design of high-precision multi-channel current-type DAC, DDS and other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is the functional schematic diagram of the DAC device;

[0019] Figure 2 This is the schematic diagram of the DAC gain modulation circuit. DETAILED DESCRIPTION

[0020] The following is a further detailed description of a DAC gain modulation circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0021] Figure 1 This is a functional schematic diagram of a DAC device used in the specific implementation of the present invention. The device is a typical current-steering digital-to-analog converter, including an interface circuit, frequency multiplication and clock distribution, a data buffer stage, a decoding circuit, a reference circuit, and a current source array. The digital signal data_in is input by the interface circuit, and is converted into a switch signal through the data buffer stage and the decoding circuit to control the opening and closing of the current source array, thereby outputting a corresponding analog current signal. The current source reference current is generated by the reference circuit and the gain control circuit, and is adjusted according to the required current value. The current regulating resistor can be integrated internally or externally.

[0022] Figure 2 The DAC gain modulation circuit provided by the present invention includes an operational amplifier 10, an operational amplifier 20, an operational amplifier 33, a PMOS tube 11, a PMOS tube 12, a PMOS tube 13, a PMOS tube 14, a PMOS tube 21, a PMOS tube 22, a PMOS tube 23, a PMOS tube 24, a PMOS tube 30, a PMOS tube 31, an NMOS tube 34, an NMOS tube 36, an NMOS tube 37, a resistor 15, a resistor 25, a resistor 32, and a resistor 35.

[0023] The positive input terminal of the operational amplifier 10 is connected to the reference voltage Vref, the negative input terminal is connected to the first end of the resistor 15, and the output terminal outputs the bias voltage bias1 to the gate terminal of the PMOS tube 11, the gate terminal of the PMOS tube 12, and the gate terminal of the PMOS tube 30. The positive input terminal of the operational amplifier 20 is connected to the reference signal Vref, the negative input terminal is connected to the first end of the resistor 25, and the output terminal outputs the bias voltage bias3 to the gate terminal of the PMOS tube 21 and the gate terminal of the PMOS tube 22. The positive input terminal of the operational amplifier 33 is connected to the reference voltage Vref, the negative input terminal is connected to the first end of the resistor 32, and the output terminal is simultaneously connected to the gate terminal of the NMOS tube 34 and the gate terminal of the NMOS tube 36.

[0024] The source end of the PMOS tube 11 is connected to VDD, and the drain end is connected to the source end of the PMOS tube 13; the source end of the PMOS tube 12 is connected to VDD, and the drain end is connected to the source end of the PMOS tube 14; the drain end of the PMOS tube 13 is connected to the first end of the resistor 15, and the drain end of the PMOS tube 14 outputs a reference current Iref1, the gate end of the PMOS tube 13 and the gate end of the PMOS tube 14 are both connected to the bias voltage bias2, and the second end of the resistor 15 is connected to GND.

[0025] The source end of the PMOS tube 21 is connected to VDD, and the drain end is connected to the source end of the PMOS tube 23; the source end of the PMOS tube 22 is connected to VDD, and the drain end is connected to the source end of the PMOS tube 24; the drain end of the PMOS tube 23 is connected to the first end of the resistor 25, and the drain end of the PMOS tube 24 outputs a reference current Iref2; the gate end of the PMOS tube 23 and the gate end of the PMOS tube 24 are connected to the bias voltage bias2, and the second end of the resistor 25 is connected to GND.

[0026] The source end of the PMOS tube 30 is connected to VDD, and the drain end is connected to the source end of the PMOS tube 31, and the drain end of the PMOS tube 31 is connected to the first end of the resistor 32; the source end of the NMOS tube 34 is connected to GND, and the drain end is connected to the second end of the resistor 32; the source end of the NMOS tube 36 is connected to GND, and the drain end is connected to the second end of the resistor 35, and the first end of the resistor 35 is connected to the drain end of the PMOS tube 23.

[0027] The source end of the NMOS tube 37 is connected to GND, the drain end is connected to the output end of the operational amplifier 33, and the gate end is connected to the signal sel. Vref is the reference voltage provided by the reference circuit, bias2 is the bias voltage provided by the reference circuit, Iref1 is the reference current provided by DAC channel 1, and Iref2 is the reference current provided by DAC channel 2.

[0028] Resistor 15 and resistor 25 are external modulation resistors of the device. The resistance value of resistor 15 is R15, and the resistance value of resistor 25 is R25. Operational amplifier 10 and operational amplifier 20 are respectively used to convert the reference voltage of channel 1 and channel 2 to the reference current. When the gain of each channel is modulated independently, the function selection signal sel is 1. At this time, NMOS tube 37 is turned on and NMOS tube 36 is turned off. There is no current path on resistor 35. The gain of each channel is independently modulated according to the external resistor. Iref1 of channel 1 = Vref / R15, and Iref2 of channel 2 = Vref / R25.

[0029] When the function selection signal sel is 0, the external port B is left floating without connecting the resistor 25, and the gain modulation circuit works. The operational amplifier 33 clamps the voltage of the node C and the external port B to the voltage Vref. The currents on the common-source and common-gate circuit PMOS tubes 12 and 14 and the common-source and common-gate circuit PMOS tubes 22 and 24 are the same. At this time, Iref1=Iref2=Vref / R15, and the gains of channel 1 and channel 2 are both adjusted by resistor 15.

[0030] It should be noted that, in order to ensure the matching degree, the sizes of PMOS tube 11, PMOS tube 12, PMOS tube 30, PMOS tube 21, PMOS tube 22 need to be consistent, the sizes of PMOS tube 13, PMOS tube 14, PMOS tube 31, PMOS tube 23, PMOS tube 24 need to be consistent, and the sizes of resistor 32 and resistor 35 need to be consistent. When adjusting a single resistor, NMOS tube 34 and NMOS tube 36 can adjust the proportional range within the working range of the transistor saturation region. At this time, the resistance value R32 of resistor 32 and the resistance value R35 of resistor 35 need to be changed at the same time, so that the ratio of Iref1 to Iref2 is equal to R32 / R35.

[0031] The DAC gain modulation circuit proposed in the present invention can select each channel to use an independent external resistor to adjust the gain or use a single resistor to adjust the gain of all channels. It also has a current proportional adjustment function and has the characteristics of simple structure, easy use, high adjustment accuracy, etc. It can be applied to the design of multi-channel current-type DAC and similar devices.

[0032] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A DAC gain modulation circuit, characterized in that: include: A first operational amplifier, a second operational amplifier, a third operational amplifier, a first PMOS tube 11, a second PMOS tube 12, a third PMOS tube 13, a fourth PMOS tube 14, a fifth PMOS tube 21, a sixth PMOS tube 22, a seventh PMOS tube 23, an eighth PMOS tube 24, a ninth PMOS tube 30, a tenth PMOS tube 31, a first NMOS tube 34, a second NMOS tube 36, a third NMOS tube 37, a first resistor 15, a second resistor 25, a third resistor 32, and a fourth resistor 35; The positive input terminal of the first operational amplifier is connected to the reference voltage Vref, the negative input terminal is connected to the first end of the first resistor, and the output terminal outputs a bias voltage bias1 to the gate terminal of the first PMOS tube, the gate terminal of the second PMOS tube, and the gate terminal of the ninth PMOS tube; The second operational amplifier has a positive input terminal connected to a reference signal Vref, a negative input terminal connected to a first terminal of a second resistor, and an output terminal outputting a bias voltage bias3 to a gate terminal of a fifth PMOS tube and a gate terminal of a sixth PMOS tube; The third operational amplifier has a positive input terminal connected to a reference voltage Vref, a negative input terminal connected to a first terminal of a third resistor, and an output terminal connected to a gate terminal of the first NMOS transistor and a gate terminal of the second NMOS transistor at the same time; Vref is a reference voltage provided by a reference circuit; The source end of the first PMOS tube is connected to VDD, and the drain end is connected to the source end of the third PMOS tube; the source end of the second PMOS tube is connected to VDD, and the drain end is connected to the source end of the fourth PMOS tube; the drain end of the third PMOS tube is connected to the first end of the first resistor, and the drain end of the fourth PMOS tube outputs a reference current Iref1, the gate end of the third PMOS tube and the gate end of the fourth PMOS tube are both connected to the bias voltage bias2, and the second end of the first resistor is connected to GND; The source end of the fifth PMOS tube is connected to VDD, and the drain end is connected to the source end of the seventh PMOS tube; the source end of the sixth PMOS tube is connected to VDD, and the drain end is connected to the source end of the eighth PMOS tube; the drain end of the seventh PMOS tube is connected to the first end of the second resistor, and the drain end of the eighth PMOS tube outputs a reference current Iref2, the gate end of the seventh PMOS tube and the gate end of the eighth PMOS tube are connected to a bias voltage bias2, and the second end of the second resistor is connected to GND; bias2 is a bias voltage provided by the reference circuit; The source end of the ninth PMOS tube is connected to VDD, the drain end is connected to the source end of the tenth PMOS tube, and the drain end of the tenth PMOS tube is connected to the first end of the third resistor; the source end of the first NMOS tube is connected to GND, and the drain end is connected to the second end of the third resistor; the source end of the second NMOS tube is connected to GND, and the drain end is connected to the second end of the fourth resistor, and the first end of the fourth resistor is connected to the drain end of the seventh PMOS tube; The source end of the third NMOS tube is connected to GND, the drain end is connected to the output end of the third operational amplifier, and the gate end is connected to the signal sel.

2. The DAC gain modulation circuit according to claim 1, characterized in that: The first resistor and the second resistor are modulation resistors external to the device. The first operational amplifier and the second operational amplifier respectively convert the reference voltage of the first channel and the second channel into a reference current. When the gain of each channel is modulated independently, the function selection signal sel is 1. At this time, the third NMOS tube is turned on and the second NMOS tube is turned off. There is no current path on the fourth resistor. The gain of each channel is independently modulated according to the external resistor. Iref1 of the first channel is Vref / R15, and Iref2 of the second channel is Vref / R25; R15 is the resistance value of the first resistor, and R25 is the resistance value of the second resistor.

3. The DAC gain modulation circuit according to claim 1, wherein: When the function selection signal sel is 0, the external port B is suspended without connecting the second resistor, the gain modulation circuit works, the third operational amplifier clamps the voltage of the node C and the external port B to the voltage Vref, the currents on the second PMOS tube, the fourth PMOS tube, the sixth PMOS tube, and the eighth PMOS tube are the same, at this time Iref1=Iref2=Vref / R15, and the gains of the first channel and the second channel are both adjusted by the first resistor; wherein the external port B is a common connection end of the negative input end of the second operational amplifier, the drain end of the seventh PMOS tube, and the first end of the fourth resistor, and the node C is a common connection point of the drain end of the tenth PMOS tube, the negative input end of the third operational amplifier, and the first end of the third resistor.

4. The DAC gain modulation circuit according to claim 3, characterized in that: When a single resistor is adjusted, the first NMOS tube and the second NMOS tube adjust the proportional range within the working range of the transistor saturation region. At this time, the resistance value R32 of the third resistor and the resistance value R35 of the fourth resistor need to be changed at the same time, so that the ratio of Iref1 to Iref2 is equal to R32 / R35.

5. The DAC gain modulation circuit according to claim 1, wherein: The sizes of the first PMOS tube, the second PMOS tube, the ninth PMOS tube, the fifth and sixth PMOS tubes, and the sixth PMOS tube all need to be consistent, the sizes of the third PMOS tube, the fourth PMOS tube, the tenth PMOS tube, the seventh PMOS tube, and the eighth PMOS tube all need to be consistent, and the sizes of the third resistor and the fourth resistor all need to be consistent.

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