FPGA-based QC-LDPC code decoder and implementation method thereof

Abstract

The invention discloses a QC-LDPC code decoder based on an FPGA and an implementation method thereof, and belongs to the technical field of communication. A channel information and posterior probability storage unit LLRRAM; and a front-end shift register unit Fshifter. A data selector is introduced in front of a variable node processing unit (VNU), the selector is connected with a shift register, and the selector flexibly connects an output value of the shift register to the VNU, so that the RAM read operation of the current layer is advanced to the data updating stage of the previous layer, the updated data of the current layer is partially written into a storage unit (LLLRRAM), and the updated data of the current layer is partially transmitted to the VNU of the next layer. Three clock cycles read by the RAM are reduced, the efficiency is improved, and the decoding performance is not reduced; in addition, an intra-layer parallel decoding algorithm and a four-stage pipeline structure technology are adopted, so that the throughput of the decoder is further improved; and the decoding speed is improved, the delay is reduced, the performance is not reduced, and the method is suitable for LDPC decoding application in a high-speed communication scene.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and more specifically, to a QC-LDPC code decoder based on FPGA and an implementation method thereof. Background Art

[0002] In digital communication systems, signals are subject to various noises and interferences during transmission, resulting in errors in the transmitted data. In order to improve the reliability of data transmission, forward error correction coding technology is usually used. As a very efficient error correction code, LDPC code has become one of the important coding schemes in modern communication systems due to its excellent performance close to the Shannon limit. It is widely used in various fields such as deep space communication and terahertz communication. The decoder of LDPC code has been widely studied in terms of code architecture, decoding algorithm and hardware implementation. Among them, how to improve the throughput and hardware resource utilization of LDPC decoder while ensuring decoding performance has become a research hotspot.

[0003] Among the many decoding algorithms for LDPC codes, layered iterative decoding is widely favored due to its excellent convergence. In terms of hardware implementation, the system throughput can be improved by reducing the clock cycle of data processing at each layer, or by adding more pipeline stages. However, when the next layer needs to use the updated LLR value, the update process of the previous layer may not be completed, resulting in the failure to update the data in time, which in turn affects the decoding performance. Therefore, the speed of data processing within the layer becomes a key factor limiting the throughput of the decoder. With the introduction of the pipeline, the read-write conflict problem of the message memory further aggravates the problem of limited throughput and reduced decoding performance.

[0004] There are several main solutions at present. One is to introduce a waiting cycle in the processing process, and the operation of the next layer will not start until the calculation of the previous layer is completed and the updated LLR value is obtained. However, the introduced waiting cycle is usually long, which greatly affects the decoding throughput; another method is not to set a waiting cycle, and continuously process the operations of each layer. When encountering a pipeline conflict, the old LLR value is read, and the update contribution of the previous layer is temporarily ignored in the current layer processing.

[0005] However, when the number of conflicting sub-matrices is large, this method will significantly reduce the decoding performance; another method is to reduce the number of conflicts by reordering the processing of the sub-matrices and delaying the use of the updated contribution values ​​based on the above method, but this method only reduces data update conflicts and does not solve the problem of reducing decoding performance. Summary of the invention

[0006] 1. Technical issues to be solved

[0007] The purpose of the present invention is to provide a QC-LDPC code decoder based on FPGA and its implementation method, so as to solve the problem raised in the above background technology that when the number of conflicting sub-matrices is large, this method will significantly reduce the decoding performance; another method is to reduce the number of conflicts by reordering the processing of the sub-matrices and postponing the use time of updating the contribution value on the basis of the above method, but this method only reduces the data update conflict and does not solve the problem of reducing the decoding performance.

[0008] 2. Technical solution

[0009] A QC-LDPC code decoder based on FPGA, comprising:

[0010] The channel information and posterior probability storage unit LLR_RAM is used to store the initially input channel data and the LLR information after the data update iteration. There are n RAM storage blocks in total, where n is the number of column blocks of the check matrix H;

[0011] The front-end shift register unit F_shifter is used to perform a circular right shift operation on the data output by the LLR_RAM according to the shift requirements of the unit matrix in each layer of the check matrix H. There are k F_shifter storage blocks in total, and k is the maximum value of the number of non-negative unit matrices in the column blocks of each layer;

[0012] The variable node calculation unit VNU is used to update and calculate the external information data of the variable node during the iteration process. There are m variable node calculation units in total, where m is the number of rows of the unit matrix in the check matrix H;

[0013] The check node calculation unit CNU is used to update and calculate the external information data of the check node during the iteration process. There are m check node calculation units in total, where m is the number of rows of the unit matrix in the check matrix H;

[0014] The posterior probability update module LUU verifies the node information according to the updated variable node information and updates the posterior probability LLR of the layer. There are m posterior probability update units in total, where m is the number of rows of the unit matrix in the check matrix H.

[0015] The back-end shift register unit B_shifter is used to reverse shift part of the data output by the LUU and write it back to the RAM, and perform a circular right shift operation on the unit matrix according to the H matrix shift requirement of the next layer. There are k B_shifter storage blocks in total, and k is the maximum value of the number of non-negative unit matrices in the column blocks of each layer;

[0016] The data selector unit Data_selector is used to select the output data of the shift registers at the front end and the back end, connect the data to the VNU module, and start the data iteration of the next layer;

[0017] The check node information storage FIFO unit R_M_FIFO is mainly used to store the updated external information of the check node. There are k check node information storage R_M_FIFO units in total, where k is the maximum value of the number of non-negative unit matrices in each layer column block;

[0018] The variable node information storage FIFO module Q_M_FIFO is mainly used to store the updated external information of the variable node. There are k check node information storage Q_M_FIFO units in total, where k is the maximum value of the number of non-negative unit matrices in each layer column block;

[0019] The control module Con_M controls the same-layer data processing and data exchange between different layers of all the above modules, as well as the timing of 4-pipeline frame interleaving decoding.

[0020] Preferably, the channel information and posterior probability storage unit LLR_RAM is completely written with data only when initialized and iterations are completed, and the remaining data iteration layers are only selectively written, and the write selection is controlled by the control module Con_M; only in the initial iteration, the first layer of data is read out in full according to the requirements of the first layer matrix, and the remaining layers are selectively partially read out, and the LLR_RAM data is read, which is 3 clocks ahead of the data processing of this layer, and the read selection is controlled by the control module Con_M.

[0021] Preferably, the front-end roller shift register unit F_shifter includes a data selector module Data_selector, and the output data of the front-end roller shift register unit F_shifter is no longer completely shifted and output according to the shift requirements of the current layer of the traditional structure, but is partially shifted and output according to the part connected to the next layer according to the data selector module Data_selector, and controlled by the control module Con_M.

[0022] Preferably, the data selector module Data_selector selects data connected to the variable node calculation unit VNU according to the current iteration layer number, and the data are the output values ​​of the front-end and back-end shift register units respectively.

[0023] Preferably, the output data of the back-end shift register unit B_shifter is no longer completely restored to the original LLR sequence by the traditional structure, but is determined by whether the data selector module Data_selector is connected to the variable node calculation unit VNU of the next layer. If it is connected to the VNU of the next layer, it is processed according to the shift requirements of the block matrix of the next layer; if it is not connected to the next layer, it is shifted and restored to the original LLR sequence and written back to the LLR_RAM module.

[0024] Preferably, the control module Con_M starts from the channel input to the LLR_RAM unit, controls the data processing order of each layer, from F_shifter to VNU, then to CNU, then to LUU, and finally to B_shifter, and then writes back to the RAM_LLR module as needed; manages the data flow between layers, the data is transferred from the first layer to the second layer, and then to the last layer in turn, completing a data iteration until the required number of data iterations is completed; controls 4-pipeline frame interleaved decoding, because each layer of data processing requires 4 clocks, so 4-pipeline frame interleaved decoding is used, when processing data within a layer, each clock corresponds to different frame data processing.

[0025] Preferably, a method for implementing a QC-LDPC code decoder based on FPGA:

[0026] S1: Initialization: The received four-frame channel initial information LLR is divided into blocks and stored in each storage block of the LLR_RAM unit according to the columns of the check matrix H, and the check node information of all 0 is written in each R_M_FIFO unit. At the same time, the number of iterations iter is initialized to 0;

[0027] S2: First layer data iteration: First, read the data in the LLR_RAM unit corresponding to the non-negative block matrix in the first layer of the check matrix H, extract the data corresponding to each frame in turn, and shift it in the front-end shift register unit F_shifter. The shifted data is sent to VNU for variable node data update, and then sent to CNU for check node update. LUU updates the posterior probability of the data, and finally sends the posterior probability LLR data to the B_shifter unit;

[0028] S3: Data update of subsequent layers: During the update process of the first-layer VNU module, the second-layer data is prepared based on the non-negative block matrix in the second-layer check matrix H. If the first-layer H matrix block and the second-layer H matrix block are adjacent to each other and are non-negative matrices, the data can be directly obtained by shifting the LLR data corresponding to the first layer through the B_shifter unit without re-reading the LLR_RAM unit; if the first-layer H matrix block is a negative matrix and the second-layer H matrix block is a non-negative matrix, the LLR data corresponding to the second layer needs to read the information from the RAM_LLR unit and perform the corresponding shift operation through the F_shifter unit; if the first-layer H matrix block is a non-negative matrix and the second-layer H matrix block is a negative matrix, the LLR data corresponding to the first layer needs to be shifted and restored through the B_shifter unit and written back to the LLR_RAM unit. The data obtained by the second layer is sent to the Data_selector data selection module after the shift operation, and then sent to the VNU, and the data is updated using operations similar to the first layer;

[0029] S4: Iteration process: Repeat the above steps until the data update of all layers is completed, and the number of iterations iter increases by 1. If the set number of iterations is not reached, continue to update the data. When the iteration is completed, the posterior probability LLR output by the LUU is restored to the original sequence by the B_shifter unit and written back to the RAM_LLR unit;

[0030] S5: Output decoding result: read the updated data from the RAM_LLR unit, perform decoding decision, and finally output the result.

[0031] Preferably, the data processing algorithm used is the layered minimum sum algorithm LMSA.

[0032] 3. Beneficial effects

[0033] Compared with the prior art, the advantages of the present invention are:

[0034] The present invention provides a QC-LDPC code decoder based on FPGA and its implementation method. Based on the traditional LDPC decoder structure, the present invention makes improvements, especially introducing a data selector Data_selector before the variable node processing unit VNU. The two input ends of the selector are respectively connected to the shift registers of the system input and output ends, and the output value of the shift register is flexibly connected to the VNU through the selector, so as to advance the RAM read operation of the current layer to the data update stage of the previous layer;

[0035] The present invention provides a QC-LDPC code decoder based on FPGA and its implementation method, wherein the updated data of the current layer is also partially written into the LLR_RAM unit and partially transmitted to the VNU of the next layer, thereby reducing three clock cycles of RAM reading, improving data transmission efficiency, and not reducing decoding performance;

[0036] The present invention adopts an intra-layer parallel decoding algorithm and a 4-stage pipeline structure technology to further improve the decoder throughput. This design significantly improves the decoding speed and reduces latency without reducing performance, and is suitable for LDPC decoding applications in high-speed communication scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the structure of a QC-LDPC decoder based on FPGA and an implementation method thereof of the present invention;

[0038] Figure 2 A schematic diagram of 4-pipeline frame interleaved decoding is provided for the FPGA-based QC-LDPC code decoder and its implementation method of the present invention;

[0039] Figure 3A schematic diagram of a QC-LDPC decoder flow chart of a QC-LDPC code decoder based on FPGA and an implementation method thereof provided by the present invention;

[0040] Figure 4 A timing diagram of 4-pipeline frame interleaved decoding of a QC-LDPC decoder is provided for the FPGA-based QC-LDPC code decoder and its implementation method of the present invention;

[0041] Figure 5 The present invention provides a QC-LDPC code decoder based on FPGA and its implementation method, and provides a decoding performance diagram of the QC-LDPC decoder using BPSK modulation under an AWGN channel. DETAILED DESCRIPTION

[0042] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0043] In the description of the present invention, “plurality” means two or more than two, unless otherwise clearly and specifically defined.

[0044] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "mounted / connected", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0045] See also Figure 1-5 , the present invention provides a technical solution:

[0046] A QC-LDPC code decoder based on FPGA, comprising:

[0047] It includes a channel information and posterior probability storage unit LLR_RAM, a front-end drum shift register unit F_shifter, a variable node calculation unit VNU, a check node calculation unit CNU, a posterior probability update unit LUU, a rear-end drum shift register unit B_shifter, a data selector module Data_selector, a check node information storage FIFO unit R_M_FIFO, a variable node information storage FIFO unit Q_M_FIFO, and a control module Con_M;

[0048] The LLR values ​​corresponding to the non-negative block sub-matrices of the next layer are no longer read out from the LLR_RAM unit and shifted to the VNU. Instead, they are obtained by shifting the LLR values ​​corresponding to the sub-matrices of the current layer and the next layer that are adjacent and non-negative to each other; if they are adjacent, the current layer is a negative sub-matrix, and the lower layer is not a negative matrix, the LLR of the next layer is read from the LLR_RAM unit 3 clocks in advance and sent to the F_shifter unit; if the current layer is a non-negative sub-matrix and the lower layer is a negative matrix, the LLR of the current layer is shifted and restored and written back to the LLR_RAM. In addition, the intra-layer parallel decoding algorithm and the 4-stage pipeline structure technology are used, such as Figure 2 As shown, the decoder throughput is further improved;

[0049] The channel information and posterior probability storage unit LLR_RAM is used to store the initially input channel data and the LLR information after the data update iteration. There are n RAM storage blocks in total, where n is the number of column blocks of the check matrix H;

[0050] The front-end shift register unit F_shifter is used to perform a circular right shift operation on the data output by the LLR_RAM according to the shift requirements of the unit matrix in each layer of the check matrix H. There are k F_shifter storage blocks in total, and k is the maximum value of the number of non-negative unit matrices in the column blocks of each layer;

[0051] The variable node calculation unit VNU is used to update and calculate the external information data of the variable node during the iteration process. There are m variable node calculation units in total, where m is the number of rows of the unit matrix in the check matrix H;

[0052] The check node calculation unit CNU is used to update and calculate the external information data of the check node during the iteration process. There are m check node calculation units in total, where m is the number of rows of the unit matrix in the check matrix H;

[0053] The posterior probability update module LUU verifies the node information according to the updated variable node information and updates the posterior probability LLR of the layer. There are m posterior probability update units in total, where m is the number of rows of the unit matrix in the check matrix H.

[0054] The back-end shift register unit B_shifter is used to reverse shift part of the data output by the LUU and write it back to the RAM, and perform a circular right shift operation on the unit matrix according to the H matrix shift requirement of the next layer. There are k B_shifter storage blocks in total, and k is the maximum value of the number of non-negative unit matrices in the column blocks of each layer;

[0055] The data selector unit Data_selector is used to select the output data of the shift registers at the front end and the back end, connect the data to the VNU module, and start the data iteration of the next layer;

[0056] The check node information storage FIFO unit R_M_FIFO is mainly used to store the updated external information of the check node. There are k check node information storage R_M_FIFO units in total, where k is the maximum value of the number of non-negative unit matrices in each layer column block;

[0057] The variable node information storage FIFO module Q_M_FIFO is mainly used to store the updated external information of the variable node. There are k check node information storage Q_M_FIFO units in total, where k is the maximum value of the number of non-negative unit matrices in each layer column block;

[0058] Control module Con_M, controls the same-layer data processing and data exchange between different layers of all the above modules, as well as the timing of 4-pipeline frame interleaving decoding;

[0059] Specifically, the channel information and posterior probability storage unit LLR_RAM is fully written only when initialized and the iteration is completed, and the remaining data iteration layers are only selectively written, and the write selection is controlled by the control module Con_M; only in the initial iteration, the first layer of data is read out according to the requirements of the first layer matrix, and the remaining layers are selectively read out, and the LLR_RAM data is read, which is 3 clocks ahead of the data processing of this layer, and the read selection is controlled by the control module Con_M.

[0060] Furthermore, the front-end roller shift register unit F_shifter includes a data selector module Data_selector. The output data of the front-end roller shift register unit F_shifter is no longer completely shifted and output according to the shift requirements of the current layer according to the traditional structure, but is partially shifted and output according to the part connected to the next layer according to the data selector module Data_selector, controlled by the control module Con_M.

[0061] Furthermore, the data selector module Data_selector selects data connected to the variable node computing unit VNU according to the current iteration layer number, and the data are the output values ​​of the front-end and back-end shift register units respectively.

[0062] Furthermore, the output data of the back-end shift register unit B_shifter is no longer completely restored to the original LLR sequence by the traditional structure, but is determined by whether the data selector module Data_selector is connected to the variable node calculation unit VNU of the next layer. If it is connected to the VNU of the next layer, it is processed according to the shift requirements of the block matrix of the next layer; if it is not connected to the next layer, the shift is restored to the original LLR sequence and written back to the LLR_RAM module.

[0063] Furthermore, the control module Con_M controls the data processing order of each layer starting from the channel input to the LLR_RAM unit, from F_shifter to VNU, then to CNU, then to LUU, and finally to B_shifter, and then writes back to the RAM_LLR module as needed; manages the data flow between layers, the data is transferred from the first layer to the second layer, and then to the last layer in turn, completing a data iteration until the required number of data iterations is completed; controls 4-pipeline frame interleaved decoding. Since each layer of data processing requires 4 clocks, 4-pipeline frame interleaved decoding is used. When processing data within a layer, each clock corresponds to different frame data processing.

[0064] It is worth noting that a QC-LDPC code decoder implementation method based on FPGA is shown in the attached process. Figure 3 :

[0065] S1: Initialization: The received four-frame channel initial information LLR is divided into blocks and stored in each storage block of the LLR_RAM unit according to the columns of the check matrix H, and the check node information of all 0 is written in each R_M_FIFO unit. At the same time, the number of iterations iter is initialized to 0;

[0066] S2: First layer data iteration: First, read the data in the LLR_RAM unit corresponding to the non-negative block matrix in the first layer of the check matrix H, extract the data corresponding to each frame in turn, and shift it in the front-end shift register unit F_shifter. The shifted data is sent to VNU for variable node data update, and then sent to CNU for check node update. LUU updates the posterior probability of the data, and finally sends the posterior probability LLR data to the B_shifter unit;

[0067] S3: Data update of subsequent layers: During the update process of the first-layer VNU module, the second-layer data is prepared based on the non-negative block matrix in the second-layer check matrix H. If the first-layer H matrix block and the second-layer H matrix block are adjacent to each other and are non-negative matrices, the data can be directly obtained by shifting the LLR data corresponding to the first layer through the B_shifter unit without re-reading the LLR_RAM unit; if the first-layer H matrix block is a negative matrix and the second-layer H matrix block is a non-negative matrix, the LLR data corresponding to the second layer needs to read the information from the RAM_LLR unit and perform the corresponding shift operation through the F_shifter unit; if the first-layer H matrix block is a non-negative matrix and the second-layer H matrix block is a negative matrix, the LLR data corresponding to the first layer needs to be shifted and restored through the B_shifter unit and written back to the LLR_RAM unit. The data obtained by the second layer is sent to the Data_selector data selection module after the shift operation, and then sent to the VNU, and the data is updated using operations similar to the first layer;

[0068] S4: Iteration process: Repeat the above steps until the data update of all layers is completed, and the number of iterations iter increases by 1. If the set number of iterations is not reached, continue to update the data. When the iteration is completed, the posterior probability LLR output by the LUU is restored to the original sequence by the B_shifter unit and written back to the RAM_LLR unit;

[0069] S5: Output decoding result: read the updated data from the RAM_LLR unit, perform decoding decision, and finally output the result.

[0070] Embodiment 1:

[0071] The specific processing steps of a QC-LDPC code decoder based on FPGA and its implementation method provided by the embodiment of the present invention are as follows: Figure 4 As shown;

[0072] S1: Initialization: The received four-frame channel initial information LLR is stored in the channel information and each storage block of the posterior probability storage unit LLR_RAM according to the columns of the check matrix H. The storage address of each storage block is 0 to 3, which corresponds to the same LLR storage position in different frames; write all 0 check node information of 16 storage addresses to each storage block of the check node information storage FIFO module R_M_FIFO; initialize the number of iterations iter to 0;

[0073] S2: first layer data iteration;

[0074] a) According to the first-layer block division of the check matrix H, the stored data in each storage block of the LLR_RAM unit at the non-negative block submatrix of the first layer of the check matrix H is read in sequence. The first clock reads the data corresponding to the first frame, and the second clock reads the data corresponding to the second frame. At the same time, the second clock starts to read the variable node data corresponding to the first layer of the first frame stored in each storage block of R_M_FIFO; the initial information reading of four frames of LLR blocks is completed within the first four clocks, and the variable node information corresponding to the four frames of the first layer is completed from the second to the fifth clocks; the read initial data of the LLR block is sequentially sent to each shift unit of the front-end shift register unit Fl_shifter corresponding to the first layer in the reading order, and the shift is performed according to the shift requirements of the first layer of the check matrix. F_shifter only consumes one clock to complete the shift operation. The four frames of LLR block data share the same F_shifter, which is distinguished by the four clocks sent in sequence. The data reading operation is controlled by the control module Con_M;

[0075] b) The output data of the first-layer front-end shift register unit F_shifter is connected to all the calculation units of VNU by the data selection module Data_selector. At this time, the variable node data of each frame of R_M_FIFO read are also all connected to the calculation units of VNU. After the calculation units of VNU complete the data update of the variable nodes, the data is sent to the calculation units of CNU and the storage units of Q_M_FIFO. CNU reads the information just stored in Q_M_FIFO during the data update of the check node. After the check node data is updated, the data is sent to the calculation units of each module of LUU and the storage units of R_M_FIFO. After the calculation units of LUU complete the data update of the sent check node information and Q_M_FIFO storage information, the data is sent to the shift units of the back-end shift register B_shifter; the four frames of LLR block data share the same VNU, CNU, LUU modules, and are distinguished by the four clocks sent in sequence. The data reading operation is controlled by the control module Con_M;

[0076] c) The data sent to each shift unit of the back-end shift register B_shifter are shifted by the control module according to the non-negative blocks in the second-layer blocks of the check matrix H. If the blocks of the first layer and the second layer are adjacent and are not negative to each other, the check block of the second layer is directly shifted by the B_shifter shift unit corresponding to the first layer, instead of being re-read from the LLR_RAM storage unit. The shifted block is connected to each calculation unit of the VNU of the second layer by the data selection module Data_selector to start the second-layer data update; if the blocks of the first layer and the second layer are adjacent, the check block corresponding to the first layer is not negative, while the check block of the second layer is negative, then the posterior probability LLR block output by the LUU of the first layer is directly shifted to restore the original sequence and written back to the corresponding storage position of RAM_LLM; if the blocks of the first layer and the second layer are adjacent, the check block corresponding to the first layer is negative, while the check block of the second layer is negative, then the posterior probability LLR block output by the LUU of the first layer is directly shifted to restore the original sequence and written back to the corresponding storage position of RAM_LLM; if the blocks of the first layer and the second layer are adjacent, the check block corresponding to the first layer is negative, while the check block of the second layer is negative If it is not negative, it is necessary to read the LLR information block from the corresponding storage position of RAM_LLM three clocks in advance before the output of the B_shifter shift unit, of which two clocks are used for reading, and one clock is sent to the shift unit corresponding to the front-end shift register module F_shifter for shift output, and the output data is sent to the data selection module Data_selector to connect to the VNU calculation unit of the second layer. At this time, the shift unit of the front-end shift register module F_shifter and the shift unit of the back-end shift register module B_shifter are simultaneously connected to the data selection module Data_selector, and are connected to the VNU module calculation unit of the second layer by Data_selector, so as to start the second layer data update; the four frames of LLR block data share the same back-end shift register module B_shifter, and are distinguished by the four clocks sent in sequence;

[0077] Second layer data update: the second layer data is obtained by c), and the data of this layer is updated according to similar operations of b) and c), and the third layer data is obtained for update;

[0078] The above operation is performed until the last layer of data is updated, and an iteration operation is completed. At this time, the iteration count iter is incremented by 1. If the iteration number requirement is not met, the new layer of data is obtained according to 2c), and the data of this layer is updated according to similar operations of 2b) and 2c) until the iteration requirement is met. When the iteration is completed, the posterior probability LLR output by each calculation unit of the LUU module is sent to the shift unit of the back-end shift register module B_shifter to restore the original LLR sequence and write it back to the RAM_LLR storage unit;

[0079] The iterated data is completely read out from the RAM_LLR storage unit, decoded and judged, and output;

[0080] The data processing algorithm used in the implementation case is the layered minimum sum algorithm LMSA;

[0081] The calculation formula of the VNU module is:

[0082]

[0083] It is represented as the external message propagated from the i-th variable node of the n-th layer to the j-th check node at the it-th iteration. For a specific m and n, Updated by the posterior probability LLR in the nth layer.

[0084] The calculation formula of the CNU module is:

[0085]

[0086] in It means that at the it-th iteration, the external message is propagated from the j-th check node of the n-th layer to the i-th variable node. N(j)\i represents the set of variable nodes participating in the jth check equation, excluding the ith variable node. Where α is the attenuation factor α∈(0,1).

[0087] The calculation formula of the LUU module is:

[0088]

[0089] represents the update of the posterior LLR of the i-th variable node in the n-th layer at the it-th iteration;

[0090] The implementation case was tested in an AWGN channel using BPSK modulation, such as Figure 5 As shown. The normalization factor is set to α = 0.75. At the same time, the initialization information LLR, VNU information and posterior probability information LLR are quantized according to the method of [6,6,8]. In the decoding process, the maximum number of iterations is set to 5, 10 and 15 times respectively, and the bit error rate is counted and compared with the bit error rate of 10 iterations of the LNMS algorithm without any modification in MATLAB. Figure 5 It can be seen from the figure that when the number of iterations is set to 10, the decoding performance of the decoder basically reaches the best. -5 When , the performance gap between the decoder and MATLAB's 10-pass decoding is less than 0.1 dB.

[0091] The implementation case was tested in an AWGN channel using BPSK modulation, such as Figure 5As shown. The normalization factor is set to α = 0.75. At the same time, the initialization information LLR, VNU information and posterior probability information LLR are quantized according to the method of [6,6,8]. In the decoding process, the maximum number of iterations is set to 5, 10 and 15 times respectively, and the bit error rate is counted and compared with the bit error rate of 10 iterations of the LNMS algorithm without any modification in MATLAB. Figure 5 It can be seen from the figure that when the number of iterations is set to 10, the decoding performance of the decoder basically reaches the best. -5 When , the performance gap between the decoder and MATLAB's 10-pass decoding is less than 0.1 dB.

[0092] The specific throughput of the implementation case is obtained by the following formula:

[0093]

[0094] Where N ldpc Represents the LDPC code length used, N fram Represents the number of frames that can be decoded simultaneously, f clk Represents the system clock frequency used, Rate is the bit rate, N iter Represents the number of iterations, N lay Represents the number of decoder layers, C lay Indicates the number of clocks required for each layer iteration. At a clock frequency of 254M, it is calculated that a single iteration can achieve a maximum throughput of 102.87Gb / s. This decoder is suitable for QC-LDPC decoding in high-speed communication scenarios. The FPGA implementation statistics of this case are shown in the following table;

[0095]

[0096] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and descriptions are only preferred examples of the present invention and are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A QC-LDPC code decoder based on FPGA, characterized in that: include: The channel information and posterior probability storage unit LLR_RAM is used to store the initially input channel data and the LLR information after the data update iteration. There are n RAM storage blocks in total, where n is the number of column blocks of the check matrix H; The front-end shift register unit F_shifter is used to perform a circular right shift operation on the data output by the LLR_RAM according to the shift requirements of the unit matrix in each layer of the check matrix H. There are k F_shifter storage blocks in total, and k is the maximum value of the number of non-negative unit matrices in the column blocks of each layer; The variable node calculation unit VNU is used to update and calculate the external information data of the variable node during the iteration process. There are m variable node calculation units in total, where m is the number of rows of the unit matrix in the check matrix H; The check node calculation unit CNU is used to update and calculate the external information data of the check node during the iteration process. There are m check node calculation units in total, where m is the number of rows of the unit matrix in the check matrix H; The posterior probability update module LUU verifies the node information according to the updated variable node information and updates the posterior probability LLR of the layer. There are m posterior probability update units in total, where m is the number of rows of the unit matrix in the check matrix H. The back-end shift register unit B_shifter is used to reverse shift part of the data output by the LUU and write it back to the RAM, and perform a circular right shift operation on the unit matrix according to the H matrix shift requirement of the next layer. There are k B_shifter storage blocks in total, and k is the maximum value of the number of non-negative unit matrices in the column blocks of each layer; The data selector unit Data_selector is used to select the output data of the shift registers at the front end and the back end, connect the data to the VNU module, and start the data iteration of the next layer; The check node information storage FIFO unit R_M_FIFO is mainly used to store the updated external information of the check node. There are k check node information storage R_M_FIFO units in total, where k is the maximum value of the number of non-negative unit matrices in each layer column block; The variable node information storage FIFO module Q_M_FIFO is mainly used to store the updated external information of the variable node. There are k check node information storage Q_M_FIFO units in total, where k is the maximum value of the number of non-negative unit matrices in each layer column block; The control module Con_M controls the same-layer data processing and data exchange between different layers of all the above modules, as well as the timing of 4-pipeline frame interleaving decoding.

2. The FPGA-based QC-LDPC code decoder according to claim 1, characterized in that: The channel information and posterior probability storage unit LLR_RAM is fully written only when initialized and iteration is completed, and the remaining data iteration layers are only selectively written, and the write selection is controlled by the control module Con_M; only in the initial iteration, the first layer of data is read out according to the requirements of the first layer matrix, and the remaining layers are selectively partially read out, and the LLR_RAM data is read, which is 3 clocks ahead of the data processing of this layer, and the read selection is controlled by the control module Con_M.

3. The FPGA-based QC-LDPC code decoder according to claim 2, characterized in that: The front-end roller shift register unit F_shifter includes a data selector module Data_selector. The output data of the front-end roller shift register unit F_shifter is no longer completely shifted and output according to the shift requirements of the current layer as in the traditional structure, but is partially shifted and output according to the part connected to the next layer according to the data selector module Data_selector, and is controlled by the control module Con_M.

4. The FPGA-based QC-LDPC code decoder according to claim 3, characterized in that: The data selector module Data_selector selects data connected to the variable node calculation unit VNU according to the current iteration layer number, and the data are the output values ​​of the front-end and back-end shift register units respectively.

5. The FPGA-based QC-LDPC code decoder according to claim 4, characterized in that: The output data of the back-end shift register unit B_shifter is no longer completely restored to the original LLR sequence by the traditional structure, but is determined by whether the data selector module Data_selector is connected to the variable node calculation unit VNU of the next layer. If it is connected to the VNU of the next layer, it is processed according to the shift requirements of the block matrix of the next layer; if it is not connected to the next layer, it is shifted and restored to the original LLR sequence and written back to the LLR_RAM module.

6. The FPGA-based QC-LDPC code decoder according to claim 1, characterized in that: The control module Con_M starts from the channel input to the LLR_RAM unit, controls the data processing order of each layer, from F_shifter to VNU, then to CNU, then to LUU, and finally to B_shifter, and then writes back to the RAM_LLR module as needed; manages the data flow between layers, the data is transferred from the first layer to the second layer, and then to the last layer in turn, completing a data iteration until the required number of data iterations is completed; controls 4-pipeline frame interleaving decoding. Since each layer of data processing requires 4 clocks, 4-pipeline frame interleaving decoding is used. When processing data within a layer, each clock corresponds to different frame data processing.

7. The method for implementing a QC-LDPC code decoder based on FPGA according to any one of claims 1 to 6, characterized in that: S1: Initialization: The received four-frame channel initial information LLR is divided into blocks and stored in each storage block of the LLR_RAM unit according to the columns of the check matrix H, and the check node information of all 0 is written in each R_M_FIFO unit. At the same time, the number of iterations iter is initialized to 0; S2: First layer data iteration: First, read the data in the LLR_RAM unit corresponding to the non-negative block matrix in the first layer of the check matrix H, extract the data corresponding to each frame in turn, and shift it in the front-end shift register unit F_shifter. The shifted data is sent to VNU for variable node data update, and then sent to CNU for check node update. LUU updates the posterior probability of the data, and finally sends the posterior probability LLR data to the B_shifter unit; S3: Data update of subsequent layers: During the update process of the first-layer VNU module, the second-layer data is prepared based on the non-negative block matrix in the second-layer check matrix H. If the first-layer H matrix block and the second-layer H matrix block are adjacent to each other and are non-negative matrices, the data can be directly obtained by shifting the LLR data corresponding to the first layer through the B_shifter unit without re-reading the LLR_RAM unit; if the first-layer H matrix block is a negative matrix and the second-layer H matrix block is a non-negative matrix, the LLR data corresponding to the second layer needs to read information from the RAM_LLR unit and perform corresponding shift operations through the F_shifter unit; if the first-layer H matrix block is a non-negative matrix and the second-layer H matrix block is a negative matrix, the LLR data corresponding to the first layer needs to be shifted and restored through the B_shifter unit and written back to the LLR_RAM unit. The data obtained by the second layer is sent to the Data_selector data selection module after the shift operation, and then sent to the VNU, and the data is updated using operations similar to the first layer; S4: Iteration process: Repeat the above steps until the data update of all layers is completed, and the number of iterations iter increases by 1. If the set number of iterations is not reached, continue to update the data. When the iteration is completed, the posterior probability LLR output by the LUU is restored to the original sequence by the B_shifter unit and written back to the RAM_LLR unit; S5: Output decoding result: read the updated data from the RAM_LLR unit, perform decoding decision, and finally output the result.

8. The method for implementing a QC-LDPC code decoder based on FPGA according to claim 7, characterized in that: The data processing algorithm used is the layered minimum sum algorithm LMSA.

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