A QC-LDPC code decoder based on FPGA and its implementation method
By introducing data selector and 4-pipeline frame interleaved decoding technology on FPGA, the data processing of QC-LDPC code decoder is optimized, the problem of decoding performance degradation is solved, and efficient decoding in high-speed communication is achieved.
Patent Information
- Application Number
- CN202411855004.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2044-12-17
AI Technical Summary
The decoding performance of existing LDPC decoders is significantly reduced when the number of conflicting sub-matrices is large. Although existing methods reduce data update conflicts, they fail to effectively solve the performance problem.
An FPGA-based QC-LDPC code decoder is used. By introducing a data selector and 4-pipeline frame interleaved decoding technology, the data processing sequence and storage method are optimized, the RAM read clock cycle is reduced, and an intra-layer parallel decoding algorithm and a 4-stage pipeline structure are adopted.
It improves the decoder's throughput and decoding speed, reduces latency, and is suitable for high-speed communication scenarios.
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Figure CN119814046B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication technology, and more particularly to an FPGA-based QC-LDPC code decoder and an implementation method thereof. Background Art
[0002] In digital communication systems, signals are subject to various noise and interference during transmission, resulting in errors in the transmitted data. To improve data transmission reliability, forward error correction (FEC) coding is often employed. As a highly efficient error-correcting code, LDPC codes, with their excellent performance close to the Shannon limit, have become a key coding scheme in modern communication systems, widely used in fields such as deep space communications and terahertz communications. LDPC code decoders have been extensively studied in terms of code architecture, decoding algorithms, and hardware implementation. Improving LDPC decoder throughput and hardware resource utilization while maintaining decoding performance has become a hot topic.
[0003] Among the numerous decoding algorithms for LDPC codes, layered iterative decoding is widely favored due to its excellent convergence. In hardware implementation, system throughput can be improved by reducing the clock cycles required for data processing at each layer or by adding more pipeline stages. However, by the time the next layer needs to use the updated LLR values, the previous layer's update process may not have completed, resulting in delayed data updates and thus impacting decoding performance. Therefore, the speed of data processing within a layer becomes a key factor limiting decoder throughput. With the introduction of pipelining, read-write conflicts in the message memory further exacerbate the throughput limitations and degraded decoding performance.
[0004] Several approaches are currently available to address this issue. One involves introducing a wait period during processing, requiring the next layer to begin operations only after the previous layer completes its calculations and obtains updated LLR values. However, this introduced wait period is often long, significantly impacting decoding throughput. Another approach involves eliminating the wait period and processing each layer continuously. When encountering a pipeline conflict, the previous LLR value is read and the updated contribution of the previous layer is temporarily ignored during processing of the current layer.
[0005] However, when the number of conflicting sub-matrices is large, this method will significantly reduce the decoding performance. Another method is to reduce the number of conflicts by reordering the sub-matrices and delaying the use of updated contribution values based on the above method. However, this method only reduces data update conflicts and does not solve the problem of reduced decoding performance. Summary of the Invention
[0006] 1. Technical problems to be solved
[0007] The object of the present invention is to provide an FPGA-based QC-LDPC code decoder and its implementation method to solve the problem raised in the above background technology that when the number of conflicting sub-matrices is large, this method will significantly reduce the decoding performance; another method is to reduce the number of conflicts by reordering the processing of the sub-matrices and postponing the use of the updated contribution value on the basis of the above method, but this method only reduces data update conflicts and does not solve the problem of reduced decoding performance.
[0008] 2. Technical solution
[0009] A QC-LDPC code decoder based on FPGA, comprising:
[0010] The channel information and posterior probability storage unit LLR_RAM is used to store the initial incoming channel data and the LLR information after data update iterations. There are n RAM storage blocks in total, where n is the number of column blocks in the check matrix H;
[0011] The front-end shift register unit F_shifter is used to perform a circular right shift operation on the data output by the LLR_RAM according to the shift requirements of the identity matrix in each layer of the check matrix H. There are k F_shifter storage blocks in total, where k is the maximum number of non-negative identity matrices in the column blocks of each layer;
[0012] Variable node calculation unit VNU, used to update and calculate the external information data of the variable node during the iteration process. There are m variable node calculation units in total, where m is the number of rows of the unit matrix in the check matrix H;
[0013] The check node calculation unit CNU is used to update and calculate the external information data of the check node during the iteration process. There are m check node calculation units in total, where m is the number of rows of the identity matrix in the check matrix H;
[0014] The posterior probability update module LUU verifies the node information according to the updated variable node information and updates the posterior probability LLR of the layer. There are m posterior probability update units in total, where m is the number of rows of the unit matrix in the check matrix H.
[0015] The back-end shift register unit B_shifter is used to reverse shift part of the data output by the LUU and write it back to the RAM, and perform a circular right shift operation on the unit matrix according to the H matrix shift requirement of the next layer. There are k B_shifter storage blocks in total, where k is the maximum number of non-negative unit matrices in the column blocks of each layer;
[0016] The data selector unit Data_selector is used to select the output data of the front-end and back-end shift registers, connect the data to the VNU, and start the data iteration of the next layer;
[0017] The check node information storage FIFO unit R_M_FIFO is mainly used to store the updated external information of the check node. There are k check node information storage R_M_FIFOs in total, where k is the maximum value of the number of non-negative unit matrices in each layer of column blocks;
[0018] The variable node information storage FIFO module Q_M_FIFO is mainly used to store the updated external information of the variable node. There are k check node information storage Q_M_FIFOs in total, where k is the maximum value of the number of non-negative unit matrices in each layer of column blocks;
[0019] The control module Con_M controls the same-layer data processing and data exchange between different layers of the posterior probability update module LUU, the VNU and the variable node information storage FIFO module Q_M_FIFO, as well as the timing of 4-pipeline frame interleaved decoding.
[0020] Preferably, the channel information and posterior probability storage unit LLR_RAM is completely written only when initialized and iterations are completed, and the remaining data iteration layers are only selectively written, and the write selection is controlled by the control module Con_M; only in the initial iteration, the first layer of data is read out in full according to the requirements of the first layer matrix, and the remaining layers are selectively read out, and the LLR_RAM data is read, which is three clocks ahead of the data processing of this layer, and the read selection is controlled by the control module Con_M.
[0021] Preferably, the front-end shift register unit F_shifter includes a data selector module Data_selector, and the output data of the front-end shift register unit F_shifter is no longer completely shifted and output according to the shift requirements of the current layer of the traditional structure, but is partially shifted and output according to the part connected to the next layer of the data selector module Data_selector, controlled by the control module Con_M.
[0022] Preferably, the data selector module Data_selector selects data connected to the variable node calculation unit VNU according to the current iteration layer number, and the data are the output values of the front-end and back-end shift register units respectively.
[0023] Preferably, the output data of the back-end shift register unit B_shifter is no longer determined by the complete restoration of the original LLR sequence of the traditional structure, but is determined by whether the data selector module Data_selector is connected to the variable node calculation unit VNU of the next layer. If it is connected to the VNU of the next layer, it is processed according to the shift requirements of the block matrix of the next layer; if it is not connected to the next layer, it is shifted and restored to the original LLR sequence and written back to LLR_RAM.
[0024] Preferably, the control module Con_M starts from the channel input to LLR_RAM, controls the data processing order of each layer, from F_shifter to VNU, then to CNU, then to LUU, and finally to B_shifter, and then writes back to RAM_LLR as needed; manages the data flow between layers, the data is transferred from the first layer to the second layer, and then to the last layer in turn, completing one data iteration until the required number of data iterations is completed; controls 4-pipe frame interleaved decoding, since each layer of data processing requires 4 clocks, so 4-pipe frame interleaved decoding is used, when processing data within a layer, each clock corresponds to different frame data processing.
[0025] Preferably, a method for implementing a QC-LDPC code decoder based on FPGA:
[0026] S1: Initialization: The received four-frame channel initial information LLR is divided into blocks according to the columns of the check matrix H and stored in each storage block of LLR_RAM, and the check node information of all 0s is written into each R_M_FIFO. At the same time, the number of iterations iter is initialized to 0;
[0027] S2: First layer data iteration: First, read the data from the LLR_RAM corresponding to the non-negative block matrix in the first layer of the check matrix H, extract the data corresponding to each frame in turn, and shift it in the front-end shift register unit F_shifter. The shifted data is sent to the VNU for variable node data update, and then sent to the CNU for check node update. The LUU updates the posterior probability of the data, and finally sends the posterior probability LLR data to B_shifter;
[0028] S3: Data update of subsequent layers: During the update process of the first-layer VNU, the second-layer data is prepared based on the non-negative block matrix in the second-layer check matrix H. If the first-layer H matrix block and the second-layer H matrix block are adjacent to each other and are non-negative matrices, the data can be directly obtained from the corresponding LLR data of the first layer through B_shifter shifting without re-reading LLR_RAM; if the first-layer H matrix block is a negative matrix and the second-layer H matrix block is a non-negative matrix, the LLR data corresponding to the second layer needs to read information from RAM_LLR and perform corresponding shift operations through F_shifter; if the first-layer H matrix block is a non-negative matrix and the second-layer H matrix block is a negative matrix, the LLR data corresponding to the first layer needs to be shifted and restored through B_shifter and written back to LLR_RAM. The data obtained by the second layer is sent to the Data_selector data selection module after the shift operation, and then sent to VNU, and the data is updated using operations similar to the first layer;
[0029] S4: Iteration process: Repeat the above steps until the data update of all layers is completed, and the number of iterations iter increases by 1. If the set number of iterations is not reached, continue to update the data. When the iteration is completed, the posterior probability LLR output by the LUU is restored to the original sequence by B_shifter and written back to RAM_LLR;
[0030] S5: Output decoding result: Read the updated data from RAM_LLR, perform decoding judgment, and finally output the result.
[0031] Preferably, the data processing algorithm used is the layered minimum sum algorithm (LMSA).
[0032] 3. Beneficial effects
[0033] Compared with the prior art, the advantages of the present invention are:
[0034] This invention provides an FPGA-based QC-LDPC code decoder and its implementation method. Based on the traditional LDPC decoder structure, the invention improves upon it by introducing a data selector (Data_selector) before the variable node processing unit (VNU). The selector's two inputs are connected to the system's input and output shift registers, respectively. The selector flexibly connects the shift register's output value to the VNU, thereby advancing the RAM read operation of the current layer to the data update phase of the previous layer.
[0035] The present invention provides an FPGA-based QC-LDPC code decoder and its implementation method. The updated data of the current layer is also partially written into the LLR_RAM and partially transferred to the VNU of the next layer, which reduces three clock cycles of RAM reading, improves data transfer efficiency, and does not reduce decoding performance.
[0036] This invention uses an intra-layer parallel decoding algorithm and a four-stage pipeline structure to further improve decoder throughput. This design significantly improves decoding speed and reduces latency without compromising performance, making it suitable for LDPC decoding applications in high-speed communication scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 Schematic diagram of the structure of a QC-LDPC code decoder based on FPGA and its implementation method of the present invention;
[0038] Figure 2 A schematic diagram of 4-pipeline frame interleaved decoding is provided for the FPGA-based QC-LDPC code decoder and its implementation method of the present invention;
[0039] Figure 3A schematic diagram of the flow of a QC-LDPC decoder provided by the FPGA-based QC-LDPC code decoder and its implementation method of the present invention;
[0040] Figure 4 A timing diagram of 4-pipeline frame interleaved decoding of a QC-LDPC decoder is provided for the FPGA-based QC-LDPC code decoder and its implementation method of the present invention;
[0041] Figure 5 The present invention provides a QC-LDPC code decoder based on FPGA and its implementation method, and provides a decoding performance diagram of the QC-LDPC decoder using BPSK modulation under AWGN channel. DETAILED DESCRIPTION
[0042] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.
[0043] In the description of the present invention, “plurality” means two or more, unless otherwise clearly defined.
[0044] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "provided with," "mounted / connected," and "connected" should be understood in a broad sense. For example, "connected" can mean a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be internal communication between two components. Those skilled in the art will be able to understand the specific meanings of the above terms in the present invention in specific circumstances.
[0045] See also Figure 1-5 , the present invention provides a technical solution:
[0046] A QC-LDPC code decoder based on FPGA, comprising:
[0047] It includes a channel information and posterior probability storage unit LLR_RAM, a front-end shift register unit F_shifter, a variable node calculation unit VNU, a check node calculation unit CNU, a posterior probability update unit LUU, a back-end drum shift register unit B_shifter, a data selector module Data_selector, a check node information storage FIFO unit R_M_FIFO, a variable node information storage FIFO unit Q_M_FIFO, and a control module Con_M;
[0048] The LLR values corresponding to the non-negative block sub-matrices of the next layer are no longer read out from LLR_RAM and shifted to VNU. Instead, they are obtained by shifting the LLR values corresponding to the sub-matrices of the current layer and the next layer that are adjacent and non-negative to each other; if they are adjacent, the current layer is a negative sub-matrix and the next layer is not a negative matrix, the LLR of the next layer is read from LLR_RAM 3 clocks in advance and sent to F_shifter; if the current layer is a non-negative sub-matrix and the next layer is a negative matrix, the LLR of the current layer is shifted and restored and written back to LLR_RAM. In addition, the intra-layer parallel decoding algorithm and 4-stage pipeline structure technology are adopted, such as Figure 2 As shown, the decoder throughput is further improved;
[0049] The channel information and posterior probability storage unit LLR_RAM is used to store the initial incoming channel data and the LLR information after data update iterations. There are n RAM storage blocks in total, where n is the number of column blocks in the check matrix H;
[0050] The front-end shift register unit F_shifter is used to perform a circular right shift operation on the data output by the LLR_RAM according to the shift requirements of the identity matrix in each layer of the check matrix H. There are k F_shifter storage blocks in total, where k is the maximum number of non-negative identity matrices in the column blocks of each layer;
[0051] Variable node calculation unit VNU, used to update and calculate the external information data of the variable node during the iteration process. There are m variable node calculation units in total, where m is the number of rows of the unit matrix in the check matrix H;
[0052] The check node calculation unit CNU is used to update and calculate the external information data of the check node during the iteration process. There are m check node calculation units in total, where m is the number of rows of the identity matrix in the check matrix H;
[0053] The posterior probability update module LUU verifies the node information according to the updated variable node information and updates the posterior probability LLR of the layer. There are m posterior probability update units in total, where m is the number of rows of the unit matrix in the check matrix H.
[0054] The back-end shift register unit B_shifter is used to reverse shift part of the data output by the LUU and write it back to the RAM, and perform a circular right shift operation on the unit matrix according to the H matrix shift requirement of the next layer. There are k B_shifter storage blocks in total, where k is the maximum number of non-negative unit matrices in the column blocks of each layer;
[0055] The data selector unit Data_selector is used to select the output data of the front-end and back-end shift registers, connect the data to the VNU, and start the data iteration of the next layer;
[0056] The check node information storage FIFO unit R_M_FIFO is mainly used to store the updated external information of the check node. There are k check node information storage R_M_FIFOs in total, where k is the maximum value of the number of non-negative unit matrices in each layer of column blocks;
[0057] The variable node information storage FIFO module Q_M_FIFO is mainly used to store the updated external information of the variable node. There are k check node information storage Q_M_FIFOs in total, where k is the maximum value of the number of non-negative unit matrices in each layer of column blocks;
[0058] A control module Con_M controls the same-layer data processing and data exchange between different layers of the posterior probability update module LUU, the VNU, and the variable node information storage FIFO module Q_M_FIFO, as well as the timing of 4-pipeline frame interleaved decoding;
[0059] Specifically, the channel information and posterior probability storage unit LLR_RAM is fully written only upon initialization and iteration completion. For the remaining data iteration layers, only selective writing is performed, and the write selection is controlled by the control module Con_M. Only during the initial iteration, the first layer of data is read out in full according to the first layer matrix requirements, and the remaining layers are selectively read out. The LLR_RAM data is read three clocks ahead of the data processing of this layer, and the read selection is controlled by the control module Con_M.
[0060] Furthermore, the front-end shift register unit F_shifter includes a data selector module Data_selector. The output data of the front-end shift register unit F_shifter is no longer completely shifted and output according to the shift requirements of the current layer of the traditional structure, but is partially shifted and output according to the part connected to the next layer of the data selector module Data_selector, controlled by the control module Con_M.
[0061] Furthermore, the data selector module Data_selector selects data connected to the variable node calculation unit VNU according to the current iteration layer number, and the data are the output values of the front-end and back-end shift register units respectively.
[0062] Furthermore, the output data of the back-end shift register unit B_shifter is no longer determined by the complete restoration of the original LLR sequence of the traditional structure, but is determined by whether the data selector module Data_selector is connected to the variable node calculation unit VNU of the next layer. If it is connected to the VNU of the next layer, it is processed according to the shift requirements of the block matrix of the next layer; if it is not connected to the next layer, the shift is restored to the original LLR sequence and written back to LLR_RAM.
[0063] Furthermore, the control module Con_M starts from the channel input to LLR_RAM, controls the data processing order of each layer, from F_shifter to VNU, then to CNU, then to LUU, and finally to B_shifter, and then writes back to RAM_LLR as needed; manages the data flow between layers, data is passed from the first layer to the second layer, and then to the last layer in turn, completing a data iteration until the required number of data iterations is completed; controls 4-pipeline frame interleaved decoding. Since each layer of data processing requires 4 clocks, 4-pipeline frame interleaved decoding is used. When processing data within a layer, each clock corresponds to different frame data processing.
[0064] It is worth noting that a QC-LDPC code decoder implementation method based on FPGA is shown in the attached flow. Figure 3 :
[0065] S1: Initialization: The received four-frame channel initial information LLR is divided into blocks according to the columns of the check matrix H and stored in each storage block of LLR_RAM, and the check node information of all 0s is written into each R_M_FIFO. At the same time, the number of iterations iter is initialized to 0;
[0066] S2: First layer data iteration: First, read the data from the LLR_RAM corresponding to the non-negative block matrix in the first layer of the check matrix H, extract the data corresponding to each frame in turn, and shift it in the front-end shift register unit F_shifter. The shifted data is sent to the VNU for variable node data update, and then sent to the CNU for check node update. The LUU updates the posterior probability of the data, and finally sends the posterior probability LLR data to B_shifter;
[0067] S3: Data update of subsequent layers: During the update process of the first-layer VNU, the second-layer data is prepared based on the non-negative block matrix in the second-layer check matrix H. If the first-layer H matrix block and the second-layer H matrix block are adjacent to each other and are non-negative matrices, the data can be directly obtained from the corresponding LLR data of the first layer through B_shifter shifting without re-reading LLR_RAM; if the first-layer H matrix block is a negative matrix and the second-layer H matrix block is a non-negative matrix, the LLR data corresponding to the second layer needs to read information from RAM_LLR and perform corresponding shift operations through F_shifter; if the first-layer H matrix block is a non-negative matrix and the second-layer H matrix block is a negative matrix, the LLR data corresponding to the first layer needs to be shifted and restored through B_shifter and written back to LLR_RAM. The data obtained by the second layer is sent to the Data_selector data selection module after the shift operation, and then sent to VNU, and the data is updated using operations similar to the first layer;
[0068] S4: Iteration process: Repeat the above steps until the data update of all layers is completed, and the number of iterations iter increases by 1. If the set number of iterations is not reached, continue to update the data. When the iteration is completed, the posterior probability LLR output by the LUU is restored to the original sequence by B_shifter and written back to RAM_LLR;
[0069] S5: Output decoding result: Read the updated data from RAM_LLR, perform decoding judgment, and finally output the result.
[0070] Example 1:
[0071] The present invention provides an FPGA-based QC-LDPC code decoder and its implementation method, including the following specific processing steps: Figure 4 As shown;
[0072] S1: Initialization: The received four-frame channel initial information LLR is stored in the channel information and posterior probability storage unit LLR_RAM in blocks and segments according to the columns of the check matrix H. The storage addresses of each storage block are 0 to 3, corresponding to the same LLR storage location in different frames; the check node information storage FIFO module R_M_FIFO is first written to each storage block with 16 storage addresses of all 0 check node information; the number of iterations iter is initialized to 0;
[0073] S2: first layer data iteration;
[0074] a) According to the first-layer block division of the check matrix H, the stored data in each storage block of the LLR_RAM corresponding to the non-negative block submatrix of the first layer of the check matrix H is read in sequence. The first clock reads the data corresponding to the first frame, and the second clock reads the data corresponding to the second frame. At the same time, the second clock starts to read the variable node data corresponding to the first layer of the first frame stored in each storage block of the R_M_FIFO; the initial information of the four frames of LLR blocks is read in the first four clocks, and the variable node information corresponding to the four frames of the first layer is completed from the second to the fifth clocks; the read initial data of the LLR block is sequentially sent to the respective shift units of the front-end shift register unit Fl_shifter corresponding to the first layer in the reading order, and shifted according to the shift requirements of the first layer of the check matrix. F_shifter only consumes one clock to complete the shift operation. The four frames of LLR block data share the same F_shifter and are distinguished in sequence by the four clocks sent in. The data reading operation is controlled by the control module Con_M;
[0075] b) The output data of the first-layer front-end shift register unit F_shifter is connected to all the calculation units of the VNU unit by the data selection module Data_selector. At this time, the variable node data of each frame read from the R_M_FIFO is also connected to all the calculation units of the VNU. After completing the data update of the variable node, each calculation unit of the VNU sends the data to the calculation units of the CNU and the storage units of the Q_M_FIFO. The CNU reads the information just stored in the Q_M_FIFO during the update of the check node data. After the check node data is updated, the data is sent to the calculation units of the LUU and the storage units of the R_M_FIFO. After completing the data update of the check node information and the Q_M_FIFO storage information, each calculation unit of the LUU sends the data to the shift units of the back-end shift register B_shifter. The four frames of LLR block data share the same VNU, CNU, and LUU, and are distinguished by the four clocks sent in sequence. The data reading operation is controlled by the control module Con_M.
[0076] c) The data sent to each shift unit of the back-end shift register B_shifter is shifted by the control module according to the non-negative blocks in the second layer of the check matrix H. If the blocks of the first layer and the second layer are adjacent and are not negative to each other, the check block of the second layer is directly shifted by the B_shifter shift unit corresponding to the first layer instead of being re-read from the LLR_RAM. The shifted block is connected to each calculation unit of the VNU of the second layer by the data selection module Data_selector to start the second layer data update; if the blocks of the first layer and the second layer are adjacent, the check block corresponding to the first layer is not negative, and the check block of the second layer is negative, then the posterior probability LLR block output by the LUU of the first layer is directly shifted to restore the original sequence and written back to the corresponding storage location of RAM_LLM; if the blocks of the first layer and the second layer are adjacent, the check block corresponding to the first layer is negative, and the check block of the second layer is not negative If it is negative, it is necessary to read the LLR information block from the corresponding storage location of RAM_LLM three clocks in advance before the output of the B_shifter shift unit. Two clocks are used for reading, and one clock is sent to the shift unit corresponding to the front-end shift register module F_shifter for shift output. The output data is sent to the data selection module Data_selector to be connected to the VNU calculation unit of the second layer. At this time, the shift unit of the front-end shift register module F_shifter and the shift unit of the back-end shift register module B_shifter are simultaneously connected to the data selection module Data_selector, and are connected to the VNU calculation unit of the second layer by Data_selector to start the second-layer data update; the four frames of LLR block data share the same back-end shift register module B_shifter, and are distinguished by the four clocks sent in sequence;
[0077] Second layer data update: Obtain the second layer data by c), and update the data of this layer according to similar operations of b) and c), and obtain the third layer data for update;
[0078] The above operations are repeated until the last layer of data is updated, completing one iteration. At this point, the iteration counter iter is incremented by 1. If the required number of iterations has not been met, the new layer of data is obtained according to 2c), and the data of this layer is updated according to similar operations in 2b) and 2c) until the required number of iterations is met. When the iteration is complete, the posterior probability LLRs output by each calculation unit of the LUU are sent to the shift unit of the back-end shift register module B_shifter to restore the original LLR sequence and write it back to RAM_LLR.
[0079] Read the iterated data completely from RAM_LLR, make decoding decisions, and output;
[0080] The data processing algorithm used in the implementation case is the layered minimum sum algorithm LMSA;
[0081] The calculation formula of VNU is:
[0082]
[0083] It is represented as the external message propagated from the i-th variable node in the n-th layer to the j-th check node at the it-th iteration. For a specific m and n, Updated by the posterior probability LLR in the nth layer.
[0084] The calculation formula for CNU is:
[0085]
[0086] in It means that at the it-th iteration, the external message is propagated from the j-th check node in the n-th layer to the i-th variable node. represents the set of variable nodes participating in the jth check equation, excluding the i-th variable node. is the attenuation factor ∈(0, 1).
[0087] The calculation formula for LUU is:
[0088]
[0089] represents the update of the posterior LLR of the i-th variable node in the n-th layer at the it-th iteration;
[0090] The implementation case was tested in an AWGN channel using BPSK modulation, such as Figure 5 As shown. The normalization factor is set to α = 0.75. At the same time, the initialization information LLR, VNU information and posterior probability information LLR are quantized according to the method of [6,6,8]. During the decoding process, the maximum number of iterations is set to 5, 10 and 15 times respectively, and the bit error rate is counted and compared with the bit error rate of 10 iterations of the LNMS algorithm without any modification in MATLAB. Figure 5 It can be seen from the figure that when the number of iterations is set to 10, the decoding performance of the decoder basically reaches the best. -5 When , the performance gap between the decoder and MATLAB's 10-pass decoding is less than 0.1 dB.
[0091] The implementation case was tested in an AWGN channel using BPSK modulation, such as Figure 5As shown. The normalization factor is set to α = 0.75. At the same time, the initialization information LLR, VNU information and posterior probability information LLR are quantized according to the method of [6,6,8]. During the decoding process, the maximum number of iterations is set to 5, 10 and 15 times respectively, and the bit error rate is counted and compared with the bit error rate of 10 iterations of the LNMS algorithm without any modification in MATLAB. Figure 5 It can be seen from the figure that when the number of iterations is set to 10, the decoding performance of the decoder basically reaches the best. -5 When , the performance gap between the decoder and MATLAB's 10-pass decoding is less than 0.1 dB.
[0092] The specific throughput of the implementation case is obtained by the following formula:
[0093]
[0094] In the formula Represents the LDPC code length used, Represents the number of frames that can be decoded simultaneously, Represents the system clock frequency used, Rate is the bit rate, represents the number of iterations, Represents the number of decoder layers, Represents the number of clocks required for each layer iteration. At a 254M clock frequency, calculations show that a single iteration can achieve a maximum throughput of 102.87 Gb / s. This decoder is suitable for QC-LDPC decoding in high-speed communication scenarios. The statistical results of the FPGA implementation of this case are shown in the following table.
[0095] LUT Resources FF Resources BRAM Resources Clock frequency (M) Throughput (Gb / s) 178943 101698 396 254 102.87
[0096] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely preferred examples of the present invention and are not intended to limit the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and improvements fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.
Claims
1. A QC-LDPC code decoder based on FPGA, characterized in that: include: The channel information and posterior probability storage unit LLR_RAM is used to store the initial incoming channel data and the LLR information after data update iterations. There are n RAM storage blocks in total, where n is the number of column blocks in the check matrix H; The front-end shift register unit F_shifter is used to perform a circular right shift operation on the data output by the LLR_RAM according to the shift requirements of the identity matrix in each layer of the check matrix H. There are k F_shifter storage blocks in total, where k is the maximum number of non-negative identity matrices in the column blocks of each layer; Variable node calculation unit VNU, used to update and calculate the external information data of the variable node during the iteration process. There are m variable node calculation units in total, where m is the number of rows of the unit matrix in the check matrix H; The check node calculation unit CNU is used to update and calculate the external information data of the check node during the iteration process. There are m check node calculation units in total, where m is the number of rows of the identity matrix in the check matrix H; The posterior probability update module LUU verifies the node information according to the updated variable node information and updates the posterior probability LLR of the layer. There are m posterior probability update units in total, where m is the number of rows of the unit matrix in the check matrix H. The back-end shift register unit B_shifter is used to reverse shift part of the data output by the LUU and write it back to the RAM, and perform a circular right shift operation on the unit matrix according to the H matrix shift requirement of the next layer. There are k B_shifter storage blocks in total, where k is the maximum number of non-negative unit matrices in the column blocks of each layer; The data selector unit Data_selector is used to select the output data of the front-end and back-end shift registers, connect the data to the VNU, and start the data iteration of the next layer; The check node information storage FIFO unit R_M_FIFO is mainly used to store the updated external information of the check node. There are k check node information storage R_M_FIFOs in total, where k is the maximum value of the number of non-negative unit matrices in each layer of column blocks; The variable node information storage FIFO module Q_M_FIFO is mainly used to store the updated external information of the variable node. There are k check node information storage Q_M_FIFOs in total, where k is the maximum value of the number of non-negative unit matrices in each layer of column blocks; The control module Con_M controls the same-layer data processing and data exchange between different layers of the posterior probability update module LUU, the VNU and the variable node information storage FIFO module Q_M_FIFO, as well as the timing of 4-pipeline frame interleaved decoding.
2. The FPGA-based QC-LDPC code decoder according to claim 1, wherein: The channel information and posterior probability storage unit LLR_RAM is fully written only upon initialization and iteration completion. The remaining data iteration layers are only selectively written, and the write selection is controlled by the control module Con_M. Only during the initial iteration, the first layer of data is read out in full according to the first layer matrix requirements, and the remaining layers are selectively partially read out. The LLR_RAM data is read three clocks ahead of the data processing of this layer, and the read selection is controlled by the control module Con_M.
3. The FPGA-based QC-LDPC code decoder according to claim 2, wherein: The front-end shift register unit F_shifter includes a data selector module Data_selector. The output data of the front-end shift register unit F_shifter is no longer completely shifted and output according to the shift requirements of the current layer in the traditional structure, but is partially shifted and output according to the part connected to the next layer according to the data selector module Data_selector, controlled by the control module Con_M.
4. The FPGA-based QC-LDPC code decoder according to claim 3, wherein: The data selector module Data_selector selects data connected to the variable node calculation unit VNU according to the current iteration layer number, and the data are the output values of the front-end and back-end shift register units respectively.
5. The FPGA-based QC-LDPC code decoder according to claim 4, wherein: The output data of the back-end shift register unit B_shifter is no longer completely restored to the original LLR sequence by the traditional structure, but is determined by whether the data selector module Data_selector is connected to the variable node calculation unit VNU of the next layer. If it is connected to the VNU of the next layer, it is processed according to the shift requirements of the block matrix of the next layer; if it is not connected to the next layer, the shift is restored to the original LLR sequence and written back to LLR_RAM.
6. The FPGA-based QC-LDPC code decoder according to claim 1, wherein: The control module Con_M starts from the channel input to LLR_RAM, controls the data processing order of each layer, from F_shifter to VNU, then to CNU, then to LUU, and finally to B_shifter, and then writes back to RAM_LLR as needed; manages the data flow between layers, data is transferred from the first layer to the second layer, and then to the last layer in sequence, completing one data iteration until the required number of data iterations is completed; controls 4-pipeline frame interleaved decoding. Since each layer of data processing requires 4 clocks, 4-pipeline frame interleaved decoding is used. When processing data within a layer, each clock corresponds to different frame data processing.
7. The method for implementing a QC-LDPC code decoder based on FPGA according to any one of claims 1 to 6, characterized in that: S1: Initialization: The received four-frame channel initial information LLR is divided into blocks according to the columns of the check matrix H and stored in each storage block of LLR_RAM, and the check node information of all 0s is written into each R_M_FIFO. At the same time, the number of iterations iter is initialized to 0; S2: First layer data iteration: First, read the data from the LLR_RAM corresponding to the non-negative block matrix in the first layer of the check matrix H, extract the data corresponding to each frame in turn, and shift it in the front-end shift register unit F_shifter. The shifted data is sent to the VNU for variable node data update, and then sent to the CNU for check node update. The LUU updates the posterior probability of the data, and finally sends the posterior probability LLR data to B_shifter; S3: Data update of subsequent layers: During the first layer VNU update process, the second layer data is prepared based on the non-negative block matrix in the second layer check matrix H. If the first layer H matrix block and the second layer H matrix block are adjacent to each other and are non-negative matrices, the data can be directly obtained from the corresponding LLR data of the first layer through B_shifter shifting without re-reading LLR_RAM; If the H matrix block of the first layer is a negative matrix and the H matrix block of the second layer is a non-negative matrix, the LLR data corresponding to the second layer needs to read information from RAM_LLR and perform corresponding shift operations through F_shifter; if the H matrix block of the first layer is a non-negative matrix and the H matrix block of the second layer is a negative matrix, the LLR data corresponding to the first layer needs to be shifted and restored through B_shifter and written back to LLR_RAM. The data obtained in the second layer is sent to the Data_selector data selection module after the shift operation, and then sent to the VNU, and the data is updated using operations similar to the first layer; S4: Iteration process: Repeat the above steps until the data update of all layers is completed, and the number of iterations iter increases by 1. If the set number of iterations is not reached, continue to update the data. When the iteration is completed, the posterior probability LLR output by the LUU is restored to the original sequence by B_shifter and written back to RAM_LLR; S5: Output decoding result: Read the updated data from RAM_LLR, perform decoding judgment, and finally output the result.
8. The method for implementing a QC-LDPC code decoder based on FPGA according to claim 7, wherein: The data processing algorithm used is the layered minimum sum algorithm (LMSA).
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