Frequency domain equalization method based on pd-dd-lms architecture, medium and device

Abstract

The application discloses a frequency domain equalization method based on a PD-DD-LMS architecture, a medium and equipment, relates to the field of digital signal processing of coherent optical communication systems, and mainly comprises the following steps: converting an input sequence into multiple data blocks by using an odd-even separation and serial-parallel conversion method, performing fast Fourier transform to obtain multiple frequency domain input block vectors, obtaining a frequency domain output block vector by using a multiple-input multiple-output frequency domain equalizer, performing inverse fast Fourier transform, discarding a preset number of elements in the front to obtain a time domain output block vector, and updating filter tap weights by using a phase-related decision-directed least mean square multiplication algorithm and a gradient descent algorithm according to the time domain output block vector. The frequency domain equalization method based on the PD-DD-LMS architecture, the medium and the equipment can reduce the computational complexity without reducing the anti-phase noise and anti-frequency offset performance.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing in coherent optical communication systems, and more specifically, to a frequency domain equalization method, medium, and device based on a PD-DD-LMS architecture. Background Technology

[0002] With the rapid development of communication technology, fiber optic communication systems have become the mainstream transmission method in modern communication networks due to their advantages such as large bandwidth, high transmission rate, and strong anti-interference capability. However, as the scale and transmission rate of fiber optic communication networks continue to increase, the system's performance and transmission quality face increasingly complex challenges. In coherent optical communication systems, signals encounter problems such as dispersion, nonlinear effects, and frequency shift after transmission through optical fibers. These problems lead to serious degradation of signal quality, especially in high-speed, high-capacity systems, where the impact is particularly pronounced.

[0003] To overcome the negative impacts of various impairments in coherent optical transmission systems, adaptive FIR filters play a crucial role. The tap coefficients of the FIR filter are updated using an adaptive tap algorithm. When the phase noise of the transmitter laser and the local oscillator (LO) laser, as well as the frequency offset between them, causes large carrier phase fluctuations during the delay time, it severely degrades the performance of FIR filters with long delay taps.

[0004] A novel architecture for a digital coherent optical receiver finite impulse response (FIR) filter based on the phase-dependent decision-directed least-meansquare algorithm (PD-DD-LMS) introduces a two-stage decision-guided carrier phase estimator to remove fast phase fluctuations from the error signal that updates the FIR filter tap coefficients. This achieves stable adaptation of the filter tap coefficients for high-order quadrature amplitude modulation (QAM) signals and exhibits better resistance to phase noise and frequency offset compared to the traditional DD-LMS method.

[0005] However, the computational complexity of FIR filters increases with the number of delay taps. Due to high power consumption and high gate density, it is difficult to implement FIR filters with a large number of delay taps in application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Therefore, a new equalization method that can reduce computational complexity is needed. Summary of the Invention

[0006] The purpose of this invention is to provide a frequency domain equalization method, medium, and device based on the PD-DD-LMS architecture, which can effectively reduce computational complexity without reducing phase noise and frequency offset resistance performance.

[0007] This invention provides a frequency domain equalization method based on the PD-DD-LMS architecture, comprising the following steps: S1: Based on the input sequence, multiple data blocks are obtained using parity separation and serial-to-parallel conversion methods;

[0008] S2: Based on the multiple data blocks, obtain multiple frequency domain input block vectors using Fast Fourier Transform; S3: Based on the multiple frequency domain input block vectors, obtain frequency domain output block vectors using a Multiple Input Multiple Output Frequency Domain Equalizer; S4: Perform Inverse Fast Fourier Transform on the frequency domain output block vectors and discard a predetermined number of elements to obtain a time domain output block vector; S5: Based on the time domain output block vectors, update the filter tap weights using the Phase Correlation Decision Oriented Least Mean Square Multiplication Algorithm and the Gradient Descent Algorithm.

[0009] Further, step S1 specifically includes: S11: performing parity separation on the input sequence to obtain... Even-numbered polarization sequences Odd sequence Even-numbered polarization sequences The input sequence includes odd-polarization sequences; Polarization input sequence and Polarization input sequence; S12: Using a serial-to-parallel conversion method, according to a preset number, the polarization input sequence is... The polarization even sequence, the The polarization odd sequence, the The polarization even sequence, the The polarization odd-numbered sequences are divided into multiple data blocks.

[0010] Further, step S2 specifically includes: obtaining multiple frequency domain input block vectors based on the multiple data blocks using a fast Fourier transform, as shown in the formula:

[0011] ,

[0012] in, Indicates the first Frequency domain input block vectors Represents the Fast Fourier Transform. ; This indicates that the matrix is ​​transposed.

[0013] Further, step S3 specifically includes: obtaining the frequency domain output block vector based on the plurality of frequency domain input block vectors using a multi-input multi-output frequency domain equalizer, as shown in the formula:

[0014] ,

[0015] ,

[0016] in, for Polarization One time-domain output block vector for Polarization One time-domain output block vector , , , , , , and These represent the tap coefficients of the frequency domain filters of the eight sub-equalizers in a multi-input multi-output frequency domain equalizer; This represents the dot product operation between frequency domain vectors; , , , Represent the even number sequence and the odd number sequence respectively. and The polarization of the first One frequency domain input block vector.

[0017] Further, step S5 specifically includes: S51: obtaining an error vector based on the time-domain output block vector using the phase-correlation decision-oriented least mean square multiplication algorithm; S52: filling the error vector with a preset number of zeros and then obtaining a frequency-domain error vector using a fast Fourier transform; S53: obtaining a gradient vector based on the frequency-domain error vector and the plurality of frequency-domain input block vectors; S54: updating the filter tap weights based on the gradient vector.

[0018] Further, step S51 specifically includes: based on the time-domain output block vector, using the phase-correlation decision orientation least mean square multiplication algorithm to obtain the error vector, as shown in the formula:

[0019] ,

[0020] ,

[0021] ,

[0022] ,

[0023] ,

[0024] in, For the error vector, express polarization( represent and The desired signal in the polarization training mode or the decoded signal in the tracking mode; express Tap coefficient vector of the first-stage phase estimator for polarization express Tap coefficient vector of the second-stage phase estimator for polarization equalizer Output block vector in polarization; It is the step size parameter, symbol This refers to taking its conjugate vector. It is the tap coefficient vector that controls the first-stage phase estimator. The error signal; It is the step size parameter. It is the tap coefficient vector that controls the second-stage phase estimator. Error signal.

[0025] Further, step S54 specifically includes: updating the filter tap weights according to the gradient vector, as shown in the formula:

[0026] ,

[0027] in, The updated filter tap weights are applied to the next data block. The filter tap weights applied to the current data block before the update. Let step size be the parameter for stochastic gradient descent. The gradient vector, Indicates using Fill with zeros.

[0028] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the frequency domain equalization method based on the PD-DD-LMS architecture described above.

[0029] The present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the frequency domain equalization method based on the PD-DD-LMS architecture described above.

[0030] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the frequency domain equalization method based on the PD-DD-LMS architecture described above.

[0031] Implementing the frequency domain equalization method, medium, and device based on the PD-DD-LMS architecture provided by this invention has the following beneficial effects:

[0032] This invention utilizes parity separation and serial-to-parallel conversion methods to convert the input sequence into multiple data blocks and performs Fast Fourier Transform (FFT) to obtain multiple frequency domain input block vectors. A Multi-Input Multi-Output (MIMO) frequency domain equalizer is then used to obtain frequency domain output block vectors, followed by an Inverse Fast Fourier Transform (IFFT). A predetermined number of elements are discarded to obtain a time domain output block vector. Based on the time domain output block vector, the filter tap weights are updated using a phase-correlation decision-oriented least mean square multiplication algorithm and a gradient descent algorithm. This invention is applicable to polarization multiplexing transmission systems. While possessing the same anti-phase noise and anti-frequency shift performance as time-domain equalization, it reduces computational complexity through block-by-block signal processing and efficient implementation of Discrete Fourier Transform (DFT). Attached Figure Description

[0033] The present invention will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings:

[0034] Figure 1 This is a flowchart of the frequency domain equalization method based on the PD-DD-LMS architecture provided by the present invention;

[0035] Figure 2 This is a schematic diagram of the overall structure of the frequency domain equalization method based on the PD-DD-LMS architecture provided by this invention.

[0036] Figure 3 This is a schematic diagram of the phase-related decision-oriented least mean square multiplication algorithm provided by the present invention;

[0037] Figure 4 This is a simulation result diagram showing the performance comparison between the present invention and time-domain equalization.

[0038] Figure 5 This is a graph showing the performance comparison experiment results between the present invention and time-domain equalization.

[0039] Figure 6 This is a comparison chart of computational complexity between the present invention and time-domain balanced computation.

[0040] Figure 7 This is a structural block diagram of the computer device provided by the present invention. Detailed Implementation

[0041] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0042] Figure 1 A schematic diagram of the frequency domain equalization method based on the PD-DD-LMS architecture in this embodiment is shown. In this embodiment, the frequency domain equalization method based on the PD-DD-LMS architecture includes the following steps:

[0043] S1: Based on the input sequence, multiple data blocks are obtained using parity separation and serial-to-parallel conversion methods;

[0044] In one exemplary embodiment, step S1 specifically includes:

[0045] S11: Perform parity separation on the input sequence to obtain... Even-numbered polarization sequences Odd sequence Even-numbered polarization sequences The input sequence includes odd-polarization sequences; Polarization input sequence and Polarization input sequence;

[0046] S12: Using a serial-to-parallel conversion method, according to a preset quantity, the... The polarization even sequence, the The polarization odd sequence, the The polarization even sequence, the The polarization odd-numbered sequences are divided into multiple data blocks;

[0047] As an exemplary embodiment, in step S1, the input sequence is... , Each branch undergoes parity separation to obtain four odd / even sequences; using a serial-to-parallel (S / P) converter, each branch is further divided into many sub-branches. Point data block, This is equal to the discrete frequency response of the frequency domain equalizer; that is, the preset quantity is the discrete frequency response of the frequency domain equalizer. Figure 2 The diagram shown is the overall structural principle of the frequency domain equalization method based on the PD-DD-LMS architecture in this embodiment. It will draw from... and Polarization input sequence The sequences are divided into odd-numbered and even-numbered sequences. Since frequency domain equalization is processed in blocks, the sequences are further divided into sequences of length [missing information]. Data blocks, using Indicates the first A length of The input block vector;

[0048] S2: Based on the multiple data blocks, use Fast Fourier Transform to obtain multiple frequency domain input block vectors;

[0049] In one exemplary embodiment, step S2 specifically includes: obtaining multiple frequency domain input block vectors based on the multiple data blocks using a fast Fourier transform, as shown in the formula:

[0050] ,

[0051] in, Indicates the first Frequency domain input block vectors Represents the Fast Fourier Transform. ; This indicates transposing the matrix;

[0052] As an exemplary embodiment, in step S2, the data block is subjected to a Fast Fourier Transform (FFT) using a 50% overlap preservation method, that is, the frequency domain input block vector of the sub-equalizers (including even-numbered and odd-numbered sub-equalizers) is represented as... By using a 50% overlap factor, the input sequence includes L samples from the current data block and L samples from the previous data block;

[0053] S3: Based on the multiple frequency domain input block vectors, use a multi-input multi-output frequency domain equalizer to obtain the frequency domain output block vector;

[0054] In one exemplary embodiment, step S3 specifically includes: obtaining a frequency domain output block vector based on the plurality of frequency domain input block vectors using a multiple-input multiple-output frequency domain equalizer, as shown in the formula:

[0055] ,

[0056] ,

[0057] in, for Polarization One time-domain output block vector for Polarization One time-domain output block vector , , , , , , and These represent the tap coefficients of the frequency domain filters of the eight sub-equalizers in a multi-input multi-output frequency domain equalizer; This represents the dot product operation between frequency domain vectors; , , , Represent the even number sequence and the odd number sequence respectively. and The polarization of the first One frequency domain input block vector;

[0058] As an exemplary embodiment, in step S3, the data block is correspondingly sent to a 2 × 2 butterfly structure finite impulse response (FIR) filter to achieve frequency domain adaptive equalization; the eight frequency domain filters consist of even-numbered sub-equalizers and odd-numbered sub-equalizers; four even-numbered sub-equalizers are in one 2 × 2 butterfly structure, and four odd-numbered sub-equalizers are in another 2 × 2 butterfly structure; in the frequency domain, the output block vector is:

[0059] ,

[0060] ,

[0061] It should be noted that in step S3, the L tap coefficient vectors of the sub-equalizer are... Padding with an equal number of zeros and performing a 2L-point FFT, the frequency domain tap coefficient vector of the sub-equalizer is represented as: ,in , express or polarization, , Indicates an even or odd sequence;

[0062] S4: Perform a fast inverse Fourier transform on the frequency domain output block vector and discard a preset number of elements to obtain the time domain output block vector;

[0063] As an exemplary embodiment, in step S4, the inverse FFT (IFFT) is performed and the previous values ​​are discarded. Each element obtains the output block vector in the time domain. , That is, perform an inverse fast Fourier transform (IFFT) on the frequency domain output block vector of the sub-equalizer and discard the values. forward Each element yields the output block vector in the time domain. ;

[0064] S5: Based on the time-domain output block vector, update the filter tap weights using the phase-correlation decision-oriented least mean square multiplication algorithm and the gradient descent algorithm;

[0065] In one exemplary embodiment, step S5 specifically includes:

[0066] S51: Based on the time-domain output block vector, the error vector is obtained using the phase-correlation decision-oriented least mean square multiplication algorithm;

[0067] In an exemplary embodiment, step S51 specifically includes: obtaining an error vector based on the time-domain output block vector using a phase-correlation decision orientation least mean square multiplication algorithm, as shown in the formula:

[0068] ,

[0069] ,

[0070] ,

[0071] ,

[0072] ,

[0073] in, For the error vector, express polarization( represent and The desired signal in the polarization training mode or the decoded signal in the tracking mode; express Tap coefficient vector of the first-stage phase estimator for polarization express Tap coefficient vector of the second-stage phase estimator for polarization equalizer Output block vector in polarization; It is the step size parameter, symbol This refers to taking its conjugate vector. It is the tap coefficient vector that controls the first-stage phase estimator. The error signal; It is the step size parameter. It is the tap coefficient vector that controls the second-stage phase estimator. The error signal;

[0074] S52: After filling the error vector with a preset number of zeros, the frequency domain error vector is obtained by using a fast Fourier transform.

[0075] As an exemplary embodiment, in step S52, equal quantities are used... Fill the error vector with zeros and perform... Point FFT yields the frequency domain error vector , Indicates using Fill with zeros;

[0076] S53: Obtain the gradient vector based on the frequency domain error vector and the plurality of frequency domain input block vectors;

[0077] As an exemplary embodiment, in step S53, based on the frequency domain error vector, the block vector is then input. Take the conjugate, and finally... Perform inverse Fast Fourier Transform and discard... After The elements yield the gradient vector. ;

[0078] S54: Update the filter tap weights based on the gradient vector;

[0079] In one exemplary embodiment, step S54 specifically includes: updating the filter tap weights according to the gradient vector, as shown in the formula:

[0080] ,

[0081] in, The updated filter tap weights are applied to the next data block. The filter tap weights applied to the current data block before the update. Let step size be the parameter for stochastic gradient descent. The gradient vector, Indicates using Fill with zeros;

[0082] As an exemplary embodiment, in step S5, the PD-DD-LMS algorithm is used to calculate the error in the time domain. The obtained error vector is padded with L zeros and then converted into a frequency domain vector of length 2L. Finally, the filter tap weights are updated in the frequency domain by using the gradient descent algorithm.

[0083] In one embodiment, the frequency domain equalization method based on the PD-DD-LMS architecture includes the following steps: in the digital signal processing section of the signal receiver, the input sequence... , Each branch undergoes parity separation to obtain four odd / even sequences. Unlike time-domain equalization, which uses sample-by-sample processing, frequency-domain equalization uses block processing. Using a serial-to-parallel (S / P) converter, each branch is further divided into many L-point data blocks, where L equals the discrete frequency response of the frequency equalizer. The data blocks are subjected to a Fast Fourier Transform (FFT) using a 50% overlap preservation method. The data blocks are then fed into corresponding 2 × 2 butterfly-structured finite impulse response (FIR) filters to achieve adaptive frequency domain equalization. The eight frequency-domain filters consist of even-numbered and odd-numbered sub-equalizers. Four even-numbered sub-equalizers are in one 2 × 2 butterfly structure, and four odd-numbered sub-equalizers are in another 2 × 2 butterfly structure. In the frequency domain, the output block vector is:

[0084] ,

[0085] ,

[0086] Perform the inverse FFT (IFFT) and discard the first L elements to obtain the output block vector in the time domain. , In the time domain, the PD-DD-LMS algorithm is used for error calculation. The obtained error vector is padded with L zeros and then converted into a frequency domain vector of length 2L. Finally, the filter tap weights are updated in the frequency domain using the gradient descent algorithm. Figure 4 This is a simulation result diagram showing the performance comparison between the present invention and time-domain equalization. Figure 5 This is a graph showing the performance comparison experiment results between the present invention and time-domain equalization. Figure 6 This is a comparison chart of computational complexity between the present invention and time-domain balanced computation.

[0087] It can be seen that the technical solution of the present invention can achieve the same effect as time-domain equalization after carrier phase estimation, but its computational complexity is greatly reduced.

[0088] In one embodiment, the frequency domain equalization method based on the PD-DD-LMS architecture can be implemented in the following manner. Figure 2 This is a schematic diagram of the overall structure of an embodiment of the present invention, showing the input sequences from x and y polarization. The sequences are divided into odd-numbered and even-numbered sequences. Since frequency domain equalization processes data in blocks, the sequences are further divided into data blocks of length L. This represents the k-th input block vector of length L.

[0089] The frequency domain input block vector of the sub-equalizer (including even-numbered and odd-numbered sub-equalizers) is represented as:

[0090] ,

[0091] By using a 50% overlap factor, the input sequence includes L samples from the current data block and L samples from the previous data block.

[0092] The L tap coefficient vectors of the sub-equalizer Padding with an equal number of zeros and performing a 2L-point FFT, the frequency domain tap coefficient vector of the sub-equalizer is represented as:

[0093] ,

[0094] Where p and q represent x or y polarization.

[0095] Perform an inverse fast Fourier transform (IFFT) on the frequency domain output block vector of the sub-equalizer and discard the values. The first L elements yield the output block vector in the time domain. .

[0096] The tap coefficients of the sub-equalizer are updated in the frequency domain using the gradient descent algorithm, and their expression is as follows:

[0097] ,

[0098] in The gradient vector is calculated as follows: first, the error vector is calculated in the time domain. Then fill with an equal number of zeros (L) and perform a 2L-point FFT to obtain:

[0099] ,

[0100] Then input the block vector. Take the conjugate, and finally... Perform inverse Fast Fourier Transform and discard... The last L elements are obtained .

[0101] Error vector Using the phase-correlation decision-oriented least mean square multiplication algorithm (the algorithm principle is as follows) Figure 3 As shown), it is calculated in the time domain, and its expression is:

[0102] ,

[0103] in This represents the desired signal in the training mode or the decoded signal in the tracking mode in the p-polarization (p represents x or y) mode. This represents the tap coefficient vector of the first-stage phase estimator for p-polarization. This represents the tap coefficient vector of the p-polarized second-stage phase estimator. This represents the output block vector on the p-polarization of the equalizer.

[0104] The update expression for the tap coefficients of the first-stage phase estimator is:

[0105] ,

[0106] It is the step size parameter, symbol This refers to taking its conjugate vector. It is the tap coefficient vector that controls the first-stage phase estimator. The error signal is expressed as follows:

[0107] ;

[0108] The update expression for the tap coefficients of the second-stage phase estimator is:

[0109] ,

[0110] It is the step size parameter, symbol This refers to taking its conjugate vector. It is the tap coefficient vector that controls the second-stage phase estimator. The error signal is expressed as follows:

[0111] .

[0112] This embodiment provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the steps of the frequency domain equalization method based on the PD-DD-LMS architecture described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium may also include combinations of the above types of memory.

[0113] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the frequency domain equalization method based on the PD-DD-LMS architecture described above.

[0114] like Figure 7As shown, the computer device 120 may include: at least one processor 121, such as a central processing unit (CPU), at least one communication interface 123, memory 124, and at least one communication bus 122. The communication bus 122 is used to enable communication between these components. The communication interface 123 may include a display screen and a keyboard; optionally, the communication interface 123 may also include a standard wired interface or a wireless interface. The memory 124 may be high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory 124 may also be at least one storage device located remotely from the aforementioned processor 121. The memory 124 stores application programs, and the processor 121 calls the program code stored in the memory 124 to execute any of the aforementioned method steps. The communication bus 122 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus 122 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 7The term 124 is represented by a single line, but this does not imply a single bus or a single type of bus. The memory 124 may include volatile memory, such as random-access memory (RAM); it may also include non-volatile memory, such as flash memory, hard disk drive (HDD), or solid-state drive (SSD); or it may include combinations of the above types of memory. The processor 121 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP. The processor 121 may further include hardware chips. These hardware chips may be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. Optionally, the memory 124 is also used to store program instructions. The processor 121 can call the program instructions to implement the frequency domain equalization method based on the PD-DD-LMS architecture as described in this embodiment.

[0115] This embodiment provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the frequency domain equalization method based on the PD-DD-LMS architecture described above.

[0116] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A frequency domain equalization method based on PD-DD-LMS architecture, characterized in that, The method comprises the following steps: S1: obtaining a plurality of data blocks according to an input sequence by using a parity separation and serial-parallel conversion method; S2: obtaining a plurality of frequency domain input block vectors according to the plurality of data blocks by using a fast Fourier transform; S3: obtaining a frequency domain output block vector according to the plurality of frequency domain input block vectors by using a multiple-input multiple-output frequency domain equalizer; S4: performing an inverse fast Fourier transform on the frequency domain output block vector and discarding a preset number of front elements to obtain a time domain output block vector; S5: updating filter tap weights according to the time domain output block vector by using a phase-related decision-directed least mean square multiplication algorithm and a gradient descent algorithm.

2. The frequency domain equalization method based on PD-DD-LMS architecture according to claim 1, wherein, Step S1 specifically comprises: S11: performing a parity separation on the input sequence to obtain the polar even sequence, the polar odd sequence, the polar even sequence, the polar odd sequence; the input sequence comprises a polar input sequence and a polar input sequence. S12: using a serial-parallel conversion method, the polarization even sequence and the polarization odd sequence are respectively divided into a plurality of data blocks according to a preset number. the polarization even sequence, the polarization odd sequence the polarization even sequence, the polarization odd sequence the polarization even sequence, the polarization odd sequence the polarization even sequence, the polarization odd sequence are respectively divided into a plurality of data blocks.

3. The frequency domain equalization method based on PD-DD-LMS architecture according to claim 1, wherein, Step S2 specifically comprises: obtaining a plurality of frequency domain input block vectors according to the plurality of data blocks by using a fast Fourier transform, as shown in the following formula: ， wherein represents the i-th frequency-domain input block vector, represents a fast Fourier transform, represents the i-th sample in the j-th data block; represents a transposition of a matrix; L represents a length of a data block.

4. The frequency domain equalization method based on PD-DD-LMS architecture according to claim 1, wherein, Step S3 specifically comprises: obtaining a frequency domain output block vector according to the plurality of frequency domain input block vectors by using a multiple-input multiple-output frequency domain equalizer, as shown in the following formula: ， ， wherein is polarized time-domain output block vector, is polarized time-domain output block vector, , , , , , , and represent the tap coefficients of the eight sub-equalizer frequency-domain filters in the multiple-input multiple-output frequency-domain equalizer, respectively; represents the dot product operation between frequency-domain vectors; , , , represent the even and odd sequences, respectively and polarized frequency-domain input block vector.

5. The frequency domain equalization method based on PD-DD-LMS architecture according to claim 1, wherein, Step S5 specifically comprises: S51: obtaining an error vector according to the time domain output block vector by using a phase-related decision-directed least mean square multiplication algorithm; S52: after filling the error vector with a preset number of 0s, obtaining a frequency domain error vector by using a fast Fourier transform; S53: obtaining a gradient vector according to the frequency domain error vector and the plurality of frequency domain input block vectors; S54: updating filter tap weights according to the gradient vector.

6. The frequency domain equalization method based on PD-DD-LMS architecture according to claim 5, wherein, Step S51 specifically comprises: obtaining an error vector according to the time domain output block vector by using a phase-related decision-directed least mean square multiplication algorithm, as shown in the following formula: ， ， ， ， ， wherein is an error vector, denotes polarization represents and a desired signal in training mode or a decoded signal in tracking mode; denotes a tap coefficient vector of the polarization first stage phase estimator, denotes a tap coefficient vector of the polarization second stage phase estimator, denotes an equalizer output block vector on the polarization; is a step size parameter, the sign means taking its conjugate vector, is an error signal controlling the tap coefficient vector of the first stage phase estimator; is a step size parameter, is an error signal controlling the tap coefficient vector of the second stage phase estimator.

7. The frequency domain equalization method based on PD-DD-LMS architecture according to claim 5, wherein, Step S54 specifically comprises: updating filter tap weights according to the gradient vector, as shown in the following formula: ， wherein is the updated filter tap weight applied to the next data block, is the filter tap weight applied to the current data block before the update, is a step size parameter for the stochastic gradient descent, is the gradient vector, denotes padding with zeros.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the frequency domain equalization method based on the PD-DD-LMS architecture according to any one of claims 1-7.

9. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the frequency domain equalization method based on the PD-DD-LMS architecture according to any one of claims 1-7.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the frequency domain equalization method based on the PD-DD-LMS architecture according to any one of claims 1-7.

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