Clock synchronization system and method based on dual-mode communication

Abstract

The invention relates to a clock synchronization system and method based on dual-mode communication, the system is a tree network and comprises a network main node CCO, a proxy node PCO and a child node STA device, the dual-mode communication is high-speed carrier and high-speed wireless, a time synchronization sub-layer is added in a data link layer, and the time synchronization sub-layer is used for synchronizing the data link layer. The frame structure of the time synchronization sub-layer comprises a time synchronization level for representing a clock synchronization priority; time synchronization operation of the system is carried out in a high-speed carrier channel and a high-speed wireless channel at the same time, transmitted time synchronization signals comprise time synchronization priority signals containing time synchronization levels, and synchronization of PCO and STA clocks and CCO clocks in the same low-voltage transformer area dual-mode communication network is achieved based on the time synchronization priority signals. Compared with the prior art, the method has the advantages of improving the clock synchronization efficiency, precision and robustness and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of clock synchronization, and in particular to a clock synchronization system and method based on dual-mode communication. Background Art

[0002] Low-voltage power line high-speed carrier communication, referred to as HPLC, is a stable and reliable communication method with fast communication rate and secure data transmission, which can use power lines for data transmission. At present, the dual-mode communication technology of power line high-speed carrier and high-speed wireless is widely used for low-voltage power information collection in the area, including power consumption information of power users and power information collection of facilities such as branch boxes and charging piles. Intelligent devices at the low-voltage side of the power distribution, low-voltage outgoing lines, low-voltage branch boxes, low-voltage meter boxes, charging piles, low-voltage photovoltaic users, etc., form the same communication network through dual-mode communication modules to realize centralized data collection.

[0003] The dual-mode communication network currently used in low-voltage areas consists of a central coordinator (CCO), a proxy coordinator (PCO) and a terminal station (STA). Figure 1 As shown in the figure, CCO is the center of the network and plays a role in scheduling and coordination. The dual-mode communication modules used by PCO and STA are functionally consistent and are slave nodes in the network. Figure 1 ,The connections in the network can be high-speed carrier or high-speed wireless.

[0004] Traditional time synchronization is performed at the application layer, and its protocol stack structure is as follows: Figure 2 The networking between the synchronization device and the synchronized device preferably uses high-speed carrier. When the high-speed carrier is unavailable, high-speed wireless is used. They are not performed simultaneously.

[0005] At present, various intelligent devices in low-voltage power grids use a time synchronization solution with a concentrator for unified timing. Generally, this solution can only achieve second-level or sub-second time synchronization between network devices, but cannot achieve millisecond-level or even microsecond-level clock synchronization, and cannot meet the application requirements of high-precision timing.

[0006] How to achieve higher-precision clock synchronization between dual-mode communication modules has become a technical problem that needs to be solved. Summary of the invention

[0007] The purpose of the present invention is to provide a clock synchronization system and method based on dual-mode communication in order to overcome the defects of the above-mentioned prior art.

[0008] The purpose of the present invention can be achieved by the following technical solutions:

[0009] According to one aspect of the present invention, there is provided a clock synchronization system based on dual-mode communication, the system comprising a network master node CCO, a proxy node PCO and a sub-node STA device, wherein the dual-mode communication is high-speed carrier and high-speed wireless, the system adds a time synchronization sublayer in the data link layer, the frame structure of the time synchronization sublayer comprises a timing level for characterizing the priority of clock synchronization; the timing operation of the system is performed simultaneously in the channels of the high-speed carrier and the high-speed wireless, the transmitted timing signal comprises a timing priority signal containing the timing level, and based on the timing priority signal, the clocks of the PCO and STA in the dual-mode communication network of the same low-voltage substation are synchronized with the CCO clock.

[0010] Preferably, the frame structure of the time synchronization sublayer also includes a data frame header, time data and data check; the time synchronization sublayer is located above the network management sublayer in the data link layer, and is used to maintain the clock synchronization of the low-voltage substation dual-mode communication network.

[0011] Preferably, the timing signal at least further includes a synchronization signal and a clock signal.

[0012] Preferably, the time synchronization priority signal is used to represent the priority of the current time synchronization.

[0013] More preferably, the PCO after synchronization initiates a synchronization operation, and the priority of the synchronization operation is downgraded.

[0014] Preferably, for the highest priority time synchronization signal received from the CCO, a time synchronization operation is performed after excluding duplicate signals.

[0015] Preferably, if timing signals with the same priority are received in the same timing cycle, the timing signal received first is selected for synchronization; if timing signals with different priorities are received in the same timing cycle, the timing signal with a higher priority is selected for synchronization; a node that receives a timing signal with too high a priority will no longer receive timing information of the same level or lower level in a timing cycle.

[0016] Preferably, the PCO and STA initially receive timing signals of any level, record the timing level after completing the first timing, only receive timing signals higher than the level before the timing cycle times out, and receive timing signals of any level after the timing cycle times out.

[0017] According to another aspect of the present invention, a clock synchronization method based on dual-mode communication is provided, the method comprising:

[0018] CCO regularly initiates timing communication, and the timing signal transmitted has the highest timing level;

[0019] STA and / or PCO receive the synchronization signal from CCO, and after verifying the data, they synchronize their own time. They will not process the synchronization signal sent by other nodes within the set time. The synchronization signal includes the synchronization level.

[0020] After receiving the timing signal, the STA does not forward it;

[0021] After receiving the time synchronization frame from the CCO, the PCO forwards the time synchronization frame to the next level based on the time it maintains and downgrades the time synchronization level.

[0022] Preferably, the PCO and STA initially receive synchronization signals of any level, and after completing the first synchronization, the synchronization level is recorded. Before the synchronization period times out, only synchronization signals higher than the level are received, and after the synchronization period times out, synchronization signals of any level are received.

[0023] After receiving the timing signal from CCO, STA and / or PCO automatically perform time calibration, where time calibration includes correcting the delay of the clock signal from the previous stage to the encoding, the transmission delay caused by the data transmission speed, and the delay from the current stage to the completion of decoding.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1) The present invention adds a time synchronization sublayer in the data link layer. The frame structure includes a timing level for characterizing the priority of clock synchronization. The transmitted timing signal includes a timing priority signal containing the timing level. The timing and clock maintenance at the data link layer realizes the synchronization of the clocks of each device with the CCO clock in the dual-mode communication network of the same low-voltage substation based on the timing priority signal. It does not occupy application layer resources, and improves the efficiency and accuracy of clock synchronization without affecting the original communication collection.

[0026] 2) The present invention introduces the concept of time synchronization priority, only receives high-level time synchronization signals in the same time synchronization cycle, and avoids repeated time synchronization operations, thereby improving the efficiency and accuracy of time synchronization.

[0027] 3) The timing operation of the present invention is performed simultaneously on high-speed carrier and high-speed wireless channels, which ensures the robustness of timing signal transmission and thus improves the robustness of clock synchronization.

[0028] 4) Based on the dual-mode communication network topology, a quasi-broadcast mechanism is adopted, and the end node STA no longer performs external time synchronization operations, which can greatly shorten the time of a time synchronization cycle.

[0029] 5) The time synchronization operation of the present invention can further improve the time synchronization accuracy through delay compensation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural schematic diagram of the dual-mode communication network of the medium and low voltage station area of ​​the present invention;

[0031] Figure 2 It is a schematic diagram of the protocol stack structure of a traditional dual-mode communication network;

[0032] Figure 3 It is a schematic diagram of the protocol stack structure of the dual-mode communication network in the present invention. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] In response to the above problems, this patent implements a clock synchronization system and method based on a dual-mode communication module, which realizes the synchronization of clock signals at the data link layer, allowing different dual-mode communication modules to have millisecond-level clock accuracy.

[0035] This embodiment relates to a clock synchronization system based on dual-mode communication, which is a tree network, including a network master node CCO, a proxy node PCO and a sub-node STA device, which performs clock synchronization of the entire network under application-irrelevant conditions, and unifies the clocks of devices in the same network to be consistent with the network master node (CCO) clock. If there are multiple central coordinators in the same low-voltage area dual-mode communication network, this method can also be used for clock synchronization between central coordinators.

[0036] Traditional dual-mode communication is divided into a network management sublayer and a media access control sublayer at the data link layer. The network management sublayer mainly implements the network management of the dual-mode communication network and the aggregation and distribution of application layer messages. The media access control sublayer mainly implements channel access competition to ensure the reliable transmission of messages in the dual-mode network.

[0037] The present invention adds a time synchronization sublayer in the data link layer, which is located above the network management sublayer and is used to maintain clock synchronization in the entire network. Figure 3 Specifically, clock synchronization is performed by adding a group of communication channels or selecting a group of existing communication channels from the original communication channels. The communication channels are hereinafter referred to as clock channels.

[0038] In the present invention, the modulation and demodulation principle of dual-mode communication remains unchanged, and a message with a special frame structure is added to the time synchronization sublayer for clock synchronization, and a clock synchronization priority mechanism is added to avoid repeated time synchronization of devices.

[0039] The data frame structure of the time synchronization sublayer includes a data frame header, a time synchronization level, time data, and data check, as shown in Table 1.

[0040] Table 1

[0041] Data frame header Time level Time data Data Verification

[0042] The time synchronization operation is performed using high-speed carrier and high-speed wireless synchronization. A time synchronization operation is performed both on the high-speed carrier channel and on the high-speed wireless channel. The time synchronization signal of the time synchronization sublayer contains at least a synchronization signal, a clock signal, and a time synchronization priority signal. The time synchronization level is contained in the time synchronization priority signal to characterize the priority of the time synchronization.

[0043] In the same network, the CCO initiates the time synchronization operation, and the time synchronization priority mechanism is used to grant time step by step. Each synchronization signal contains the current synchronization priority. After the synchronization, the PCO initiates a synchronization operation, and the priority of the synchronization operation is downgraded. After receiving the highest priority synchronization signal sent by the CCO, the synchronization operation will be performed after excluding the repeated signals received from the high-speed carrier and high-speed wireless in a short period of time (for example, a module receives two synchronization signals sent by the CCO from the carrier, and the synchronization operation will be performed regardless of the interval). In other cases, nodes that receive synchronization signals with too high a priority will no longer receive synchronization signals of the same or lower level within a synchronization cycle.

[0044] When a device in the network receives both high-speed carrier and high-speed wireless synchronized time data, it will prioritize the data received first for synchronization. If the later received data has a higher priority, the higher priority data will be used to update the clock and reset the synchronization cycle. Otherwise, the synchronization data will not be updated.

[0045] In the same low-voltage network, if there are multiple CCOs, the CCO will use the built-in arbitration mechanism to determine a CCO as the benchmark based on the time when it receives other CCOs. The built-in arbitration mechanism can be customized according to needs. For example, currently the CCO with a smaller ID is used as the benchmark first.

[0046] After signal acquisition and decoding, the dual-mode communication module automatically performs time calibration. This calibration operation is mainly used to correct the delay of the clock signal from the previous level to the encoding, the transmission delay caused by the data transmission speed, and the sum of the delay from the current level to the completion of decoding. The corrected clock is output to the external application through the external interface, and the dual-mode communication module's own clock is also updated. The non-end node uses the clock maintained by the module itself for the next level of time calibration operation.

[0047] CCO uses a fixed time interval to synchronize the clock downward. Other nodes can initially receive synchronization signals of any level. After the first synchronization is completed, the level of the synchronization signal is recorded. Before the timeout, only synchronization signals higher than the level will be received. After the timeout, synchronization signals of any level can be received.

[0048] CCO has a timing interface that can receive timing commands from peripheral devices. The timing command contains a clock signal. After receiving the signal, COO will update its own clock and use the new clock for timing operations.

[0049] The dual-mode communication module uses one pin (shared ground level) to connect with other external modules. The pin has a standard pulse width and uses high and low signals with standard pulse width for signal transmission.

[0050] This embodiment relates to a clock synchronization method based on dual-mode communication, such as Figure 1 In the network structure, CCO periodically initiates synchronization communication (for example, every 1 minute), and the synchronization level is 0. If there are multiple CCOs in the same low-voltage power distribution network, the CCOs communicate with each other. CCO will periodically search for other CCOs in the network. If so, it will obtain the other party's unique identification number (ID) information and then compare it with its own ID. For example, by comparing the size of the unique identification number (ID) of the device, confirm a CCO as the main CCO (benchmark) for synchronization operations.

[0051] STA1, PCO1, PCO2, PCO3 and STA9 receive the time synchronization frame from CCO, and after the data verification is correct, they synchronize their own time. The time data used for synchronization is the data after the delay correction based on the time in the data frame. Within the set time (for example, 1 minute), these nodes will not process the data synchronization frames sent by other nodes because the time level 0 is the highest level.

[0052] Assuming that PCO3 does not receive a subsequent time synchronization frame within 61 seconds after the set time expires, it will start to receive time synchronization frames of other time synchronization levels.

[0053] After STA1, PCO1, PCO2, PCO3 and STA9 receive the time synchronization frame, STA1 and STA9 are end nodes and will not forward the time synchronization frame. PCO1, PCO2 and PCO3 will send time synchronization frames downward based on the conflict avoidance mechanism. However, the time synchronization data in the time synchronization frame sent at this time is based on the time of the forwarding node itself.

[0054] PCO1, PCO2, and PCO3 send time synchronization frames, and the time synchronization level is adjusted to 1. They directly receive each other's time synchronization frames. Since the received time synchronization level is low, no time synchronization operation is performed.

[0055] Assuming that STA2, STA3, STA4 and STA1 can receive the time synchronization frame of PCO1, STA2, STA3 and STA4 will perform time synchronization, but STA1 will not perform time synchronization because it has already received the time synchronization level 0. STA2, STA3, STA4 and STA1 are all end nodes and will not forward the time synchronization frame.

[0056] Assuming that STA5, STA6, STA7, and STA8 receive the time synchronization data frame of PCO2 first, they will all perform the time synchronization operation. If they receive the time synchronization data frame of PCO3, they will no longer perform the operation because the time synchronization frame level of PCO3 is the same as the clock synchronization frame level of PCO2.

[0057] If STA2 receives a time synchronization frame from CCO with a time synchronization level of 0, it will immediately perform time synchronization operations regardless of the circumstances.

[0058] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A clock synchronization system based on dual-mode communication, the system comprising a network master node CCO, a proxy node PCO and a sub-node STA device, wherein the dual-mode communication is high-speed carrier and high-speed wireless, characterized in that: The system adds a time synchronization sublayer in the data link layer, and the frame structure of the time synchronization sublayer includes a time synchronization level for characterizing the clock synchronization priority; the time synchronization operation of the system is performed simultaneously in the high-speed carrier and high-speed wireless channels, and the transmitted time synchronization signal includes a time synchronization priority signal containing the time synchronization level, and based on the time synchronization priority signal, the clocks of PCO and STA in the dual-mode communication network of the same low-voltage station area are synchronized with the CCO clock.

2. A clock synchronization system based on dual-mode communication according to claim 1, characterized in that: The frame structure of the time synchronization sublayer also includes a data frame header, time data and data check; the time synchronization sublayer is located above the network management sublayer in the data link layer and is used to maintain the clock synchronization of the low-voltage station area dual-mode communication network.

3. A clock synchronization system based on dual-mode communication according to claim 1, characterized in that: The timing signal at least includes a synchronization signal and a clock signal.

4. A clock synchronization system based on dual-mode communication according to claim 1, characterized in that: The time synchronization priority signal is used to indicate the priority of the current time synchronization.

5. A clock synchronization system based on dual-mode communication according to claim 4, characterized in that: After the synchronization, the PCO initiates a synchronization operation, and the priority of the synchronization operation is downgraded.

6. A clock synchronization system based on dual-mode communication according to claim 1, characterized in that: For the highest priority timing signal sent by CCO, the timing operation will be performed after excluding duplicate signals.

7. A clock synchronization system based on dual-mode communication according to claim 1, characterized in that: If synchronization signals with the same priority are received in the same synchronization cycle, the synchronization signal received first will be selected for synchronization; if synchronization signals with different priorities are received in the same synchronization cycle, the synchronization signal with a higher priority will be selected for synchronization; a node that receives a synchronization signal with a priority that is too high will no longer receive synchronization information of the same or lower level in a synchronization cycle.

8. A clock synchronization system based on dual-mode communication according to claim 1, characterized in that: PCO and STA initially receive synchronization signals of any level. After the first synchronization is completed, the synchronization level is recorded. Before the synchronization cycle times out, only synchronization signals higher than the level are received. After the synchronization cycle times out, synchronization signals of any level are received.

9. A method for utilizing the clock synchronization system based on dual-mode communication according to any one of claims 1 to 8, characterized in that: The method includes: CCO regularly initiates timing communication, and the timing signal transmitted has the highest timing level; STA and / or PCO receive the synchronization signal from CCO, and after verifying the data, they synchronize their own time. They will not process the synchronization signal sent by other nodes within the set time. The synchronization signal includes the synchronization level. After receiving the timing signal, the STA does not forward it; After receiving the time synchronization frame from the CCO, the PCO forwards the time synchronization frame to the next level based on the time it maintains and downgrades the time synchronization level.

10. The method according to claim 9, characterized in that PCO and STA initially receive synchronization signals of any level. After the first synchronization is completed, the synchronization level is recorded. Before the synchronization cycle times out, only synchronization signals higher than the level are received. After the synchronization cycle times out, synchronization signals of any level are received. After receiving the timing signal from CCO, STA and / or PCO automatically perform time calibration, where time calibration includes correcting the delay of the clock signal from the previous stage to the encoding, the transmission delay caused by the data transmission speed, and the delay from the current stage to the completion of decoding.

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