A quantum-resistant cryptographic signature algorithm execution optimization system and communication equipment

Abstract

The application relates to the technical field of quantum computers, in particular to an anti-quantum password signature algorithm execution optimization method and a communication device. A first FIFO memory for storing a first random coefficient and a second random coefficient is arranged on a computing hardware, the number of times of writing and reading a secret polynomial into and from a storage unit is reduced through a cache mode; a second FIFO memory for storing polynomial coefficients on a cache finite field is arranged to balance data processing time, a third FIFO memory is arranged to perform bit width conversion of a key, and a storage module for storing a public polynomial is arranged, so that the data execution speed is balanced in combination. Through the above data storage arrangement, the number of data access and storage times is reduced, extra power consumption caused by memory access is reduced, high delay problems among modules are reduced, and the overall execution time required for calculation is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computers, and particularly relates to an anti-quantum password signature algorithm execution optimization method and a communication device. BACKGROUND

[0002] Many secure communication devices and hardware infrastructures use the security measures of classical cryptography systems, but due to the advent of quantum crisis, these devices are no longer secure, and new cryptography systems are needed to resist attacks by quantum computers. Since the United States NIST (National Institute of Standards and Technology) proposed the post-quantum cryptography algorithm collection plan in 2016, more and more post-quantum cryptography algorithms have been proposed. Taking the Dilithium signature algorithm in the anti-quantum signature algorithm as an example, there are many steps in the key generation and signature and signature verification processes of the Dilithium signature algorithm, and a large number of polynomial and hash operations need to be performed. It takes a lot of time to sequentially execute these polynomial calculations, and cannot meet the needs of fast key generation and data encryption, so the optimization of polynomial calculation is particularly important. SUMMARY

[0003] The present application provides an anti-quantum password signature algorithm execution optimization method and a communication device to solve the problem that the anti-quantum signature algorithm in the prior art needs to perform a large number of polynomial and hash operations, and it takes a lot of time to sequentially execute these polynomial calculations.

[0004] The embodiment of the present application provides an anti-quantum password signature algorithm execution optimization system, which comprises:

[0005] a hash sampling module configured to perform hash operation and sampling on a received random seed to obtain a sampling result, the sampling result comprising a first random coefficient, a second random coefficient and a polynomial matrix;

[0006] a first FIFO memory configured to buffer the first random coefficient and the second random coefficient;

[0007] a polynomial calculation module configured to perform polynomial calculation on the first random coefficient, the second random coefficient and the polynomial matrix to obtain a polynomial coefficient on a finite field;

[0008] a second FIFO memory configured to buffer the polynomial coefficient on the finite field;

[0009] a data processing module configured to calculate a key of an anti-quantum password signature algorithm according to the buffered polynomial coefficient on the finite field, and to pack the key;

[0010] A third FIFO memory is used to perform bit width conversion on the packed key;

[0011] A storage module, used for storing the polynomial matrix and the key after bit width conversion;

[0012] A scheduling state machine is used to schedule the hash sampling module, the first FIFO memory, the polynomial calculation module, the second FIFO memory, the data processing module, the third FIFO memory and the storage module.

[0013] Optionally, the hash sampling module includes:

[0014] A hash operation unit, configured to perform a hash operation on the received random seed to obtain a hash operation result;

[0015] A first Keccak operation unit is configured to perform a Keccak operation on a random seed of the secret polynomial in the hash operation result to obtain a secret polynomial;

[0016] A second Keccak operation unit is used to perform a Keccak operation on a random seed of the public polynomial in the hash operation result to obtain a public polynomial;

[0017] a first sampling unit, configured to sample the secret polynomial to obtain the first random coefficient and the second random coefficient;

[0018] The second sampling unit is used to sample the common polynomial to obtain a polynomial matrix.

[0019] Optionally, the first FIFO memory includes:

[0020] a first FIFO sub-memory, configured to cache the first random coefficient;

[0021] A second FIFO sub-memory, configured to cache the second random coefficient;

[0022] The third FIFO sub-memory is used to cache the polynomial matrix.

[0023] Optionally, the polynomial calculation module includes:

[0024] a first NTT unit, configured to perform a number theory transformation on the first random coefficient in the first FIFO sub-memory to obtain a first number theory transformation result;

[0025] a second NTT unit, configured to perform a number theory transformation on the second random coefficient in the second FIFO sub-memory to obtain a second number theory transformation result;

[0026] a fourth FIFO memory, configured to cache the first number theory transformation result;

[0027] a point multiplication operator, configured to perform a point multiplication operation on the first number theory transformation result in the fourth FIFO memory and the polynomial matrix in the storage module to obtain a point multiplication operation result;

[0028] a modular addition operator, configured to perform a modular addition operation on the dot product operation result and the second number theory transformation result to obtain a modular addition operation result;

[0029] a fifth FIFO memory, configured to cache the modular addition operation result;

[0030] The INTT unit is used to perform an inverse number theory transformation on the modular addition operation result in the fifth FIFO memory to obtain polynomial coefficients on a finite field.

[0031] Optionally, the data processing module includes:

[0032] a coefficient decomposition unit, configured to perform coefficient decomposition on the polynomial coefficients in the second FIFO memory to obtain first polynomial sub-coefficients and second polynomial sub-coefficients;

[0033] An encoding unit, configured to encode the second polynomial sub-coefficients and the random seed of the public polynomial to obtain a public key of a quantum-resistant cryptographic signature algorithm;

[0034] The hash operation unit is further configured to perform a hash operation on the public key to obtain a hash value;

[0035] The encoding unit is further used to encode the hash value, the random seed of the public polynomial, the key parameter in the hash operation result, the first random coefficient, the second random coefficient, and the first polynomial sub-coefficient to obtain a private key of the quantum-resistant cryptographic signature algorithm; the public key and the private key constitute the key.

[0036] Optionally, the storage module includes:

[0037] a polynomial matrix area, for storing the polynomial matrix cached in the third FIFO sub-memory in a matrix order after the polynomial matrix is ​​transposed;

[0038] A key data area, used for storing the key that has completed bit width conversion in the third FIFO memory according to a preset bit width;

[0039] The operation data area is used to store the first polynomial sub-coefficients, the second polynomial sub-coefficients, and the key parameters in the hash operation result.

[0040] Optionally, when the first NTT unit and / or the second NTT unit is in an idle state, and there is data to be processed that requires number theoretic transformation and is not generated by hash operation, the first NTT unit and / or the second NTT unit in the idle state is used to perform number theoretic transformation on the data to be processed, and the number theoretic transformation result is stored in the operation data area of ​​the storage module.

[0041] Optionally, the system further includes a checking module for performing a norm check on the polynomial coefficients on the finite field when the polynomial coefficients are polynomial coefficients generated during the signing process, and for feeding back a failure signal to the scheduling state machine when the check result shows failure.

[0042] This embodiment of the present invention further provides a communication device, the device comprising:

[0043] A key generation module, configured to generate the key by using the quantum-resistant cryptographic signature algorithm to execute an optimized system;

[0044] The signature module is used to use the private key in the key to sign the data to be encrypted, or use the public key in the key to verify the signature of the signed data to be encrypted.

[0045] Optionally, the types of the communication device include personal computers, mobile communication devices, routers, and gateways.

[0046] Its beneficial effect is that: the present application sets a first FIFO memory for storing the first random coefficient and the second random coefficient corresponding to the secret polynomial on the computing hardware, and reduces the number of times the secret polynomial is written to and read from the storage unit by caching; sets a second FIFO memory for caching the polynomial coefficients on the finite field to balance the data processing time, and sets a third FIFO memory for performing bit width conversion of the key, and sets a storage module for storing the public polynomial at the same time, and the combination of the two balances the data execution speed. By using the above-mentioned data storage setting, on the one hand, the number of data access and storage is reduced, and the additional power consumption caused by memory access is reduced; on the other hand, the high latency problem between modules is reduced. Moreover, the data storage method changes the order in which data is executed, which overall balances the data execution speed and reduces the overall execution time required for the calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0048] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0049] Figure 1 A hardware architecture diagram of a quantum-resistant cryptographic signature algorithm execution optimization system provided in an embodiment of this specification;

[0050] Figure 2 A detailed hardware architecture diagram of a quantum-resistant cryptographic signature algorithm execution optimization system provided in an embodiment of this specification;

[0051] Figure 3 A schematic diagram of the structure of a communication device provided in an embodiment of this specification. DETAILED DESCRIPTION

[0052] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention.

[0053] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention.

[0054] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0055] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0056] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0057] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0058] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0059] Reference Figure 1A schematic diagram of the structure of a quantum-resistant cryptographic signature algorithm execution optimization system is provided for an embodiment of this specification, including: a hash sampling module 01, configured to perform a hash operation and sampling on a received random seed to obtain a sampling result, wherein the sampling result includes a first random coefficient, a second random coefficient, and a polynomial matrix; a first FIFO memory 02, configured to cache the first random coefficient and the second random coefficient; a polynomial calculation module 03, configured to perform a polynomial calculation on the first random coefficient, the second random coefficient, and the polynomial matrix to obtain a polynomial coefficient on a finite field; a second FIFO memory 04, configured to cache the polynomial coefficient on the finite field. polynomial coefficients; a data processing module 05, used to calculate the key of the quantum-resistant cryptographic signature algorithm based on the cached polynomial coefficients on the finite field, and to package the key; a third FIFO memory 06, used to perform bit width conversion on the packaged key; a storage module 07, used to store the polynomial matrix and the key after bit width conversion; a scheduling state machine 08, used to schedule the hash sampling module 01, the first FIFO memory 02, the polynomial calculation module 03, the second FIFO memory 04, the data processing module 05, the third FIFO memory 06 and the storage module 07.

[0060] Optional, such as Figure 2 As shown, the first FIFO memory 02 includes: a first FIFO sub-memory 020, used to cache the first random coefficient; a second FIFO sub-memory 021, used to cache the second random coefficient; and a third FIFO sub-memory 022, used to cache the polynomial matrix. By setting the FIFO sub-memory, the execution speed of the overall data is balanced, thereby reducing the overall execution time required for the calculation.

[0061] In an alternative embodiment, Figure 2As shown, in the process of generating public and private keys of the quantum cryptographic signature algorithm, taking the calculation process of A*s1+s2 in the key generation process as an example, first, the scheduling state machine 08 sends an instruction to the quantum random number generator to generate a random seed. Then, the scheduling state machine 08 controls the hash operation unit 010 in the hash sampling module 01 to perform a hash operation on the received random seed to obtain a hash operation result, wherein the hash operation result includes the random seed ρ of the public polynomial, the random seed ρ′ of the secret polynomial, and the key K for the quantum cryptographic signature algorithm. After that, the scheduling state machine 08 schedules the hash sampling module 010 to perform a hash operation on the received random seed. The first Keccak operation unit 011 in block 01 performs a Keccak operation on the random seed ρ′ of the secret polynomial in the hash operation result to obtain the secret polynomial, and schedules the second Keccak operation unit 012 in the hash sampling module 01 to perform a Keccak operation on the random seed ρ of the public polynomial in the hash operation result to obtain the public polynomial. Subsequently, the scheduling state machine 08 schedules the first sampling unit 013 to sample the secret polynomial to obtain the first random coefficient s1 and the second random coefficient s2, and schedules the second sampling unit 014 to sample the public polynomial to obtain the polynomial matrix A. Finally, the scheduling state machine 08 controls the second sampling unit 014 to write the polynomial matrix A into the polynomial matrix area of ​​the storage module, and controls the first sampling unit 013 to cache the first random coefficient s1 and the second random coefficient s2 into the first FIFO memory. By providing a first FIFO memory on the computing hardware to store the first random coefficient s1 and the second random coefficient s2 corresponding to the secret polynomial, the number of times the random coefficients of the secret polynomial are written to and read from the storage module is reduced.

[0062] like Figure 2As shown, the scheduling state machine 08 schedules the first NTT unit 030 in the polynomial calculation module 03 to perform a number-theoretic transformation on the first random coefficient s1 in the first FIFO sub-memory 020 to obtain a first number-theoretic transformation result, and schedules the second NTT unit 031 in the polynomial calculation module 03 to perform a number-theoretic transformation on the second random coefficient s2 in the second FIFO sub-memory 021 to obtain a second number-theoretic transformation result, that is, to perform a positive transformation on s1 and s2. At the same time, the scheduling state machine 08 schedules the first NTT unit 030 to cache the first number-theoretic transformation result to the fourth FIFO memory 032. By setting the fourth FIFO memory, the pipeline speed of the polynomial matrix A is balanced to ensure that each module and / or unit does not generate a large delay when calculating the polynomial matrix A. Then, the scheduling state machine 08 schedules the dot multiplication operator 033 in the polynomial calculation module 03 to cache the first number-theoretic transformation result to the fourth FIFO memory 032. The first number-theoretic transformation result in the IFO memory is subjected to a point multiplication operation with the polynomial matrix A in the storage module to obtain a point multiplication operation result; then, the scheduling state machine 08 schedules the modular addition operator 034 in the polynomial calculation module 03 to perform a modular addition operation on the point multiplication operation result and the second number-theoretic transformation result to obtain a modular addition operation result, and caches the modular addition operation result in the fifth FIFO memory 035; finally, the scheduling state machine 08 schedules the INTT unit 036 in the polynomial calculation module 03 to perform an inverse number-theoretic transformation on the modular addition operation result in the fifth FIFO memory to obtain the polynomial coefficient t on the finite field, and caches the polynomial coefficient t on the finite field in the second FIFO memory. By setting the second FIFO memory to cache the polynomial coefficient on the finite field, the polynomial coefficient is kept from generating a large delay in each module and / or unit during the polynomial calculation, effectively balancing the data execution speed. By using the above data storage configuration, on the one hand, the number of data access and storage times is reduced, reducing the additional power consumption caused by memory access, and on the other hand, reducing the high delay problem between modules. Moreover, the data storage method changes the order in which data is executed, overall balancing the data execution speed, and reducing the overall execution time required for the calculation.

[0063] In an optional embodiment, the storage module stores the polynomial matrix in the fourth FIFO memory in the matrix order after the polynomial matrix A is transposed, so as to facilitate the subsequent reading of the polynomial matrix A.

[0064] like Figure 2As shown, after obtaining the polynomial coefficient t on the finite field, in order to generate the public key and private key of the quantum-resistant cryptographic signature algorithm, the scheduling state machine 08 schedules the coefficient decomposition unit 050 in the data processing module 05 to perform high-low bit decomposition of the polynomial coefficient in the second FIFO memory to obtain the first polynomial sub-coefficient t0 and the second polynomial sub-coefficient t1, wherein high-low bit decomposition refers to the process of decomposing a numerical value into its high-bit and low-bit parts. For example, for a 32-bit integer, the low 16 bits can be represented as the low-bit part, and the high 16 bits can be represented as the high-bit part; then, the scheduling state machine 08 schedules the encoding unit 051 in the data processing module 05 to perform high-low bit decomposition of the second polynomial sub-coefficient t1 and the random seed of the public polynomial. ρ is encoded, that is, (ρ, t1) is encoded to obtain the public key pk of the quantum-resistant cryptographic signature algorithm; then, the scheduling state machine 08 schedules the hash operation unit 010 to perform a hash operation on the public key pk to obtain a hash value tr. Finally, the scheduling state machine 08 schedules the encoding unit 051 to encode the hash value tr, the random seed ρ of the public polynomial, the key K in the hash operation result, the first random coefficient s1, the second random coefficient s2, and the first polynomial sub-coefficient t0, that is, (ρ, K, tr, s1, s2, t0) is encoded to obtain the private key sk of the quantum-resistant cryptographic signature algorithm, and the private key sk and the public key pk of the quantum-resistant cryptographic signature algorithm are packaged, that is, the key of the quantum-resistant cryptographic signature algorithm is packaged. The dispatch state machine 08 converts the bit width of the packaged key by calling the configured third FIFO memory 06 and writes the converted key to the address corresponding to the key data area in the storage module. When data requires signing and verification using the quantum-resistant signature algorithm, the public key pk and private key sk are directly extracted from the addresses corresponding to the key data area in the storage module. Using the third FIFO memory to convert the bit width of the public key pk and private key sk ensures that the public key pk and private key sk are stored in the key data area of ​​the storage module according to the configured bit width, facilitating data storage and transmission.

[0065] Optionally, the storage module 07 includes: a polynomial matrix area 070 for storing the polynomial matrix cached in the third FIFO sub-memory 022 in matrix order after the polynomial matrix is ​​transposed; a key data area 071 for storing the key that has undergone bit width conversion in the third FIFO memory 06 in a preset bit width; and an operation data area 072 for storing the first polynomial sub-coefficients, the second polynomial sub-coefficients, and the key parameters in the hash operation result. By dividing the storage module 07 into multiple areas, different data can be stored more specifically, facilitating subsequent data reading and use.

[0066] Optionally, when the first NTT unit 030 and / or the second NTT unit 031 is in an idle state, and there is data to be processed that requires number theoretic transformation and is not generated by hash operation, the first NTT unit 030 and / or the second NTT unit 031 in the idle state is used to perform number theoretic transformation on the data to be processed, and the number theoretic transformation result is stored in the operation data area of ​​the storage module.

[0067] In an optional embodiment, when there is data to be processed that requires number-theoretic transformations and is not generated by hash operations, if the first NTT unit 030 and / or the second NTT unit 031 are idle, the scheduling state machine 08 will control the first NTT unit 030 and / or the second NTT unit 031 to process the currently input external data to be processed, utilizing parallel processing between modules. The processing results are written to the computational data area 072 of the storage module 07. For example, during the signature process, the private key needs to be decompressed to obtain the polynomial coefficients therein. Then, the NTT transformation is performed on these polynomial coefficients. In this case, the scheduling state machine 08 will control the idle first NTT unit 030 and / or the second NTT unit 031 to perform the NTT transformation on these polynomials. Using this scheduling method, each NTT unit can be better utilized, making the execution of the entire algorithm more compact and preventing a single unit or module from experiencing significant delays. This avoids slowing down the execution speed of the overall quantum-resistant cryptographic signature algorithm due to delays in a single unit or module. The data to be processed can be understood as data that is not generated by the hash sampling module but requires an NTT transformation.

[0068] Optionally, the system further includes a checking module 09 for performing a norm check on the polynomial coefficients on the finite field when the polynomial coefficients are polynomial coefficients generated during the signature process, and for feeding back a failure signal to the scheduling state machine 08 when the check result shows failure.

[0069] In an alternative embodiment, Figure 2 As shown, the checking module 09 is responsible for performing a norm check on the polynomial coefficients generated during the signature process. For example, during the signature process using a quantum-resistant signature algorithm, the checking unit performs a norm check on the specific polynomial coefficient z. If any coefficient does not meet the check requirements, a failure signal will be returned to the scheduling state machine 08, indicating that the specific polynomial coefficient cannot be used to generate a valid signature. The scheduling state machine 08 will then control the quantum random number generator to regenerate a random seed and generate a new specific polynomial coefficient z. If the norm check passes, the specific polynomial coefficient z meets the requirements and can be used to generate a valid signature. At the same time, the polynomial coefficients over the finite field are cached in the third FIFO memory, which can balance the checking unit's inspection time during the norm check process and improve the execution efficiency of the checking unit.

[0070] In an optional embodiment, the entire polynomial matrix A can be written into the polynomial matrix area 070 of the storage module 07 in advance, so there is no need to repeat the process of calculating the polynomial matrix A, thereby achieving the effect of increasing the data calculation speed by increasing the on-chip storage area.

[0071] In an optional embodiment, the data processing module 05 is also used for data recovery, data packaging and other processing, thereby diversifying the data processing capabilities of the data processing module.

[0072] like Figure 3 As shown, the embodiments of this specification also provide a communication device, comprising: a key generation module 1 for generating the key using the quantum-resistant cryptographic signature algorithm to execute an optimized system; a signature module 2 for signing encrypted data using a private key sk in the key, or verifying the signature of the encrypted data using a public key pk in the key. The communication device includes a personal computer, a mobile communication device, a router, and a gateway.

[0073] The present application sets a first FIFO memory for storing the first random coefficient and the second random coefficient corresponding to the secret polynomial on the computing hardware, and reduces the number of times the secret polynomial is written to and read from the storage unit by caching; sets a second FIFO memory for caching the polynomial coefficients on the finite field to balance the data processing time, and sets a third FIFO memory for performing bit width conversion of the key, and sets a storage module for storing the public polynomial at the same time. The combination of the two balances the data execution speed. By using the above data storage setting, on the one hand, the number of data access and storage is reduced, and the additional power consumption caused by memory access is reduced. On the other hand, the high latency problem between modules is reduced. Moreover, the data storage method changes the order in which data is executed, which overall balances the data execution speed and reduces the overall execution time required for the calculation.

[0074] The specific embodiments described above further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the present invention is not inherently related to any specific computer, virtual device, or electronic device, and various general-purpose devices can also implement the present invention. The above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.

[0075] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0076] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A quantum-resistant cryptographic signature algorithm execution optimization system, characterized in that: include: A hash sampling module, configured to perform a hash operation and sampling on a received random seed to obtain a sampling result, wherein the sampling result includes sampling a secret polynomial to obtain a first random coefficient and a second random coefficient and sampling a public polynomial to obtain a polynomial matrix; a first FIFO memory, configured to cache the first random coefficient and the second random coefficient; a polynomial calculation module, configured to perform polynomial calculation on the first random coefficient, the second random coefficient, and the polynomial matrix to obtain polynomial coefficients on a finite field; A second FIFO memory, configured to cache polynomial coefficients over the finite field; a data processing module, configured to calculate a key of a quantum-resistant cryptographic signature algorithm based on the cached polynomial coefficients over the finite field, and to package the key; A third FIFO memory is used to perform bit width conversion on the packed key; A storage module, used for storing the polynomial matrix and the key after bit width conversion; A scheduling state machine is used to schedule the hash sampling module, the first FIFO memory, the polynomial calculation module, the second FIFO memory, the data processing module, the third FIFO memory and the storage module.

2. The system according to claim 1, wherein The hash sampling module includes: A hash operation unit, configured to perform a hash operation on the received random seed to obtain a hash operation result; A first Keccak operation unit is configured to perform a Keccak operation on a random seed of the secret polynomial in the hash operation result to obtain a secret polynomial; The second Keccak operation unit is used to perform a Keccak operation on a random seed of the public polynomial in the hash operation result to obtain a public polynomial.

3. The system according to claim 2, wherein: The first FIFO memory comprises: a first FIFO sub-memory, configured to cache the first random coefficient; A second FIFO sub-memory, configured to cache the second random coefficient; The third FIFO sub-memory is used to cache the polynomial matrix.

4. The system according to claim 3, wherein: The polynomial calculation module includes: a first NTT unit, configured to perform a number theory transformation on the first random coefficient in the first FIFO sub-memory to obtain a first number theory transformation result; a second NTT unit, configured to perform a number theory transformation on the second random coefficient in the second FIFO sub-memory to obtain a second number theory transformation result; a fourth FIFO memory, configured to cache the first number theory transformation result; a point multiplication operator, configured to perform a point multiplication operation on the first number theory transformation result in the fourth FIFO memory and the polynomial matrix in the storage module to obtain a point multiplication operation result; a modular addition operator, configured to perform a modular addition operation on the dot product operation result and the second number theory transformation result to obtain a modular addition operation result; a fifth FIFO memory, configured to cache the modular addition operation result; The INTT unit is used to perform an inverse number theory transformation on the modular addition operation result in the fifth FIFO memory to obtain polynomial coefficients on a finite field.

5. The system according to claim 4, wherein: The data processing module includes: a coefficient decomposition unit, configured to perform coefficient decomposition on the polynomial coefficients in the second FIFO memory to obtain first polynomial sub-coefficients and second polynomial sub-coefficients; An encoding unit, configured to encode the second polynomial sub-coefficients and the random seed of the public polynomial to obtain a public key of a quantum-resistant cryptographic signature algorithm; The hash operation unit is further configured to perform a hash operation on the public key to obtain a hash value; The encoding unit is further used to encode the hash value, the random seed of the public polynomial, the key parameter in the hash operation result, the first random coefficient, the second random coefficient, and the first polynomial sub-coefficient to obtain a private key of the quantum-resistant cryptographic signature algorithm; the public key and the private key constitute the key.

6. The system according to claim 5, wherein: The storage module includes: a polynomial matrix area, for storing the polynomial matrix cached in the third FIFO sub-memory in a matrix order after the polynomial matrix is ​​transposed; A key data area, used for storing the key that has completed bit width conversion in the third FIFO memory according to a preset bit width; The operation data area is used to store the first polynomial sub-coefficients, the second polynomial sub-coefficients, and the key parameters in the hash operation result.

7. The system according to claim 6, wherein: When the first NTT unit and / or the second NTT unit is in an idle state, and there is data to be processed that requires number theoretic transformation and is not generated by hash operation, the first NTT unit and / or the second NTT unit in the idle state is used to perform number theoretic transformation on the data to be processed, and the number theoretic transformation result is stored in the operation data area of ​​the storage module.

8. The system according to claim 1, wherein: The system further includes a checking module for performing a norm check on the polynomial coefficients on the finite field when the polynomial coefficients are polynomial coefficients generated during the signature process, and for feeding back a failure signal to the scheduling state machine when the check result indicates failure.

9. A communication device, characterized in that: The device comprises: A key generation module, configured to generate the key by executing an optimized system using the quantum-resistant cryptographic signature algorithm according to any one of claims 1 to 8; The signature module is used to use the private key in the key to sign the data to be encrypted, or use the public key in the key to verify the signature of the signed data to be encrypted.

10. The communication device according to claim 9, wherein The types of communication devices include personal computers, mobile communication devices, routers, and gateways.

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