Clock buffer device and clock buffer method, data transmission system

Abstract

The application discloses a clock buffering device and method, and a data transmission system. The device is arranged between a data transmission layer and a physical layer of a sending end. The device comprises a configuration module, a monitoring module and a buffering module. The configuration module is used for configuring a buffering clock period and redundant data corresponding to synchronous transmission of the buffering clock period. The monitoring module is used for monitoring whether a sending data transmission state of the data transmission layer is switched from an idle state to a starting transmission data state. The buffering module is used for sending the redundant data corresponding to the synchronous transmission to a receiving end in the buffering clock period before sending effective data of the data transmission layer. The frequency of the buffering clock period is lower than that of a normal clock period of the effective data.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, in particular to a clock buffering device and a clock buffering method, and a data transmission system. BACKGROUND

[0002] For data transmission in a manner of clock matching data synchronous transmission, when the data transmission signal changes from an "idle" state to a "busy" state, that is, when the data transmission state switches from an idle state to a start data transmission state, due to the influence of inter-symbol interference in transmission, the waveform of the first few clock signals sent by the sending end after the start of the jump is severely distorted. The duty cycle of the first few clock signals sampled by the IO of the receiving end after the start of the jump changes greatly, and the receiving end cannot recognize the corresponding clock, so the jump of the clock signal is lost. Correspondingly, the synchronous transmission data sampled by the receiving end is incorrect.

[0003] To solve the above problems, a decision feedback equalizer (DFE) module is added at the receiving end to reduce the influence of inter-symbol interference on the signal, or a feedforward equalizer (FFE) function is used at the sending end to reduce inter-symbol interference by changing the driving strength of the IO output from a constant level to a sudden jump when transmitting the signal.

[0004] However, the above method requires adding corresponding analog circuits in the storage device, which not only increases the complexity of the circuit design, but also increases the design area of the chip IO of the storage device, and also increases the power consumption of the chip. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide a clock buffering device and a clock buffering method, and a data transmission system, to solve the problem of inter-symbol interference in data transmission of a storage device.

[0006] To solve the above technical problems, the present specification is implemented as follows:

[0007] In a first aspect, a clock buffering device is provided, which is applied to a sending end, and the device is arranged between a data transmission layer and a physical layer of the sending end. The device comprises:

[0008] A configuration module is configured to configure a buffering clock period and redundant data corresponding to the buffering clock period for synchronous transmission;

[0009] A monitoring module is configured to monitor whether the sending data transmission state of the data transmission layer switches from an idle state to a start transmission data state;

[0010] a buffering module, configured to transmit redundant data corresponding to the synchronous transmission to the receiving end in the buffering clock cycle before transmitting the valid data of the data transmission layer; wherein the frequency of the buffering clock cycle is lower than the frequency of the normal clock cycle of the synchronous transmission of the valid data.

[0011] In a second aspect, a clock buffering device is provided, which is applied to a receiving end, and is arranged between a physical layer and a data transmission layer of the receiving end. The device comprises:

[0012] a configuration module, configured to configure a first number based on the number of the redundant data corresponding to the synchronous transmission in the buffering clock cycle;

[0013] a monitoring module, configured to monitor whether the receiving data transmission state of the physical layer is switched from an idle state to a data transmission start state;

[0014] a buffering module, configured to remove the first number of data received first from the data of the sending end received by the physical layer.

[0015] In a third aspect, a clock buffering method is provided, which is applied to a sending end, and comprises:

[0016] configuring a buffering clock cycle and redundant data corresponding to the synchronous transmission in the buffering clock cycle;

[0017] monitoring whether the sending data transmission state of the data transmission layer is switched from an idle state to a data transmission start state;

[0018] transmitting redundant data corresponding to the synchronous transmission to the receiving end in the buffering clock cycle before transmitting the valid data of the data transmission layer; wherein the frequency of the buffering clock cycle is lower than the frequency of the normal clock cycle of the synchronous transmission of the valid data.

[0019] In a fourth aspect, a clock buffering method is provided, which is applied to a receiving end, and comprises:

[0020] configuring a first number based on the number of the redundant data corresponding to the synchronous transmission in the buffering clock cycle;

[0021] monitoring whether the receiving data transmission state of the physical layer is switched from an idle state to a data transmission start state;

[0022] removing the first number of data received first from the data of the sending end received by the physical layer.

[0023] In a fifth aspect, a data transmission system is provided, which comprises a sending end and a receiving end,

[0024] The sending end sends the redundant data corresponding to the synchronous transmission to the receiving end in the configured buffer clock period before sending the valid data of the data transmission layer when monitoring that the sending data transmission state of the data transmission layer of the sending end switches from the idle state to the start transmission data state; wherein the frequency of the buffer clock period is lower than the frequency of the normal clock period of the synchronous transmission of the valid data.

[0025] The receiving end eliminates the data of the number of the redundant data corresponding to the synchronous transmission of the buffer clock period which is received first in the data of the sending end received by the physical layer when monitoring that the receiving data transmission state of the physical layer switches from the idle state to the start transmission data state.

[0026] In the embodiment of the present application, the clock buffer device arranged between the data transmission layer and the physical layer of the sending end comprises: a configuration module configured to configure the buffer clock period and the redundant data corresponding to the synchronous transmission of the buffer clock period; a monitoring module configured to monitor whether the sending data transmission state of the data transmission layer switches from the idle state to the start transmission data state; and a buffer module configured to send the redundant data corresponding to the synchronous transmission to the receiving end in the buffer clock period before sending the valid data of the data transmission layer; wherein the frequency of the buffer clock period is lower than the frequency of the normal clock period of the synchronous transmission of the valid data, so that the code interference in the data transmission only affects the burst jump signal of the first few buffer clock periods, the valid data loss caused by the code interference is avoided, and the valid data sent can be completely transmitted to the receiving end, so that the receiving end can accurately sample the valid data. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and serve to explain the present application, and do not limit the present application in any manner. In the drawings:

[0028] Figure 1 is a schematic diagram of an application scenario of a data transmission system of an embodiment of the present application.

[0029] Figure 2 is a structural block diagram of a data transmission system of an embodiment of the present application.

[0030] Figure 3 is a waveform diagram of a data transmission signal of an embodiment of the present application.

[0031] Figure 4 is a waveform diagram of a data transmission signal of another embodiment of the present application.

[0032] Figure 5 is a flowchart of a clock buffering method of a first embodiment of the present application.

[0033] Figure 6 is a flowchart of a clock buffering method of a second embodiment of the present application.

[0034] Figure 7 is a structural block diagram of a clock buffering device of an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application. The numbering in the drawings in the present application is only used to distinguish various steps in the solutions, and is not used to limit the execution order of the various steps, and the specific execution order is subject to the description in the specification.

[0036] To solve the problems in the prior art, the embodiments of the present application provide a clock buffering device and a clock buffering method, and a data transmission system, Figure 1 is an application scenario diagram of a data transmission system of an embodiment of the present application.

[0037] The data transmission system of the embodiments of the present application is suitable for clock and data synchronous transmission of data transmission. The sending end 10 sends data to the receiving end 20 in a clock and data synchronous transmission mode. Correspondingly, the receiving end 20 receives data in a clock and data synchronous transmission mode.

[0038] In one embodiment, the master control chip and the storage grain inside the target storage device are the sending end 10 and the receiving end 20. As shown in Figure 1 When the master control chip is the sending end 10 and the storage grain is the receiving end 20, the master control chip sends data of an external device (not shown in the figure) to the storage grain through the transmission line 30 between the input / output (IO) of the sending end 10 and the input / output (IO) of the receiving end 20, so as to realize writing data of the external device to the storage grain through the master control chip. Alternatively, when the storage grain is the sending end 10 and the master control chip is the receiving end 20, the storage grain sends internally stored data to the master control chip through the transmission line 30, so as to realize reading data of the external device from the storage grain through the master control chip.

[0039] Figure 2 is a structural block diagram of a data transmission system of an embodiment of the present application. In this embodiment, the data transmission system includes a sending end 10 and a receiving end 20. The clock buffering device 100 provided in the embodiments of the present application is applied to the sending end 10, and the clock buffering device 200 provided in the embodiments of the present application is applied to the receiving end 20.

[0040] For the clock buffering device 100 applied to the sending end 10, as shown in the figure, the clock buffering device 100 is arranged between the data transmission layer 12 and the physical layer 14 of the sending end 10, and the clock buffering device 100 comprises: a configuration module 120 configured to configure a buffering clock period and redundant data corresponding to synchronous transmission of the buffering clock period; a monitoring module 140 configured to monitor whether the sending data transmission state of the data transmission layer is switched from an idle state to a starting transmission data state; and a buffering module 160 configured to send the redundant data corresponding to synchronous transmission to the receiving end in the buffering clock period before sending the valid data of the data transmission layer; wherein the frequency of the buffering clock period is lower than the frequency of the normal clock period of the valid data of the synchronous transmission. Figure 2

[0041] In combination with Figure 2 , the data transmission layer 12 of the sending end 10 is configured to perform protocol conversion on the signal sent to the receiving end 20, and the physical layer 14 of the sending end 10 is configured to perform digital / analog signal conversion on the signal after the protocol conversion.

[0042] Specifically, for example, in the case of a master chip as the sending end 10 and a storage grain as the receiving end 20, the data transmission layer 12 of the sending end 10 is configured to convert the received data of the external device into the protocol of the storage device, and the physical layer 14 of the sending end 10 is configured to convert the data after the protocol conversion into an analog signal, obtain the valid data of the analog signal, and transmit the valid data to the physical layer of the receiving end 20. Correspondingly, the physical layer 24 of the receiving end 20 is configured to convert the received analog signal into a digital signal, and the data transmission layer 22 of the receiving end 20 is configured to perform protocol conversion on the converted digital signal and then store the digital signal.

[0043] For the case of a storage grain as the sending end 10 and a master chip as the receiving end 20, the principle is the same as above, which will not be described here.

[0044] In order to avoid the case that the jump signal of the first one or more clocks sent by the sending end 10 after the start jump is severely distorted and lost due to inter-code interference during transmission, the configuration module 120 can buffer the clock period and the redundant data corresponding to the synchronous transmission, so that the buffering module 160 sends the redundant data corresponding to the synchronous transmission to the receiving end 20 in the configured buffering clock period before sending the valid data of the data transmission layer 12.

[0045] ​The number and frequency of the buffer clock cycles configured by the configuration module 120 can be determined in advance through experiments. The number can be one or multiple, and the signal loss of the buffer clock cycle can be avoided. In this way, even if the first few buffer clock cycles jump, since the frequency of the first few buffer clock cycles is low, even if the buffer clock signal is deformed due to the influence of inter-symbol interference in transmission, it will not be serious enough to lose the buffer clock signal at the receiving end 20. That is, the number of buffer clock cycles received by the receiving end 20 is consistent with the number of buffer clock cycles sent by the sending end 10.

[0046] Optionally, the configuration module 120 is specifically configured to: configure the number of buffer clock cycles to be multiple; and configure the frequencies of the multiple buffer clock cycles to be the same and lower than the frequency of the normal clock cycle, or configure the frequencies of the multiple buffer clock cycles to gradually increase from low to high and the frequency of the highest buffer clock cycle to be less than the frequency of the normal clock cycle.

[0047] For the case where the frequencies of the multiple buffer clock cycles gradually increase from low to high, for example, 2 buffer clock cycles are used, and the corresponding frequencies from low to high are 1 / 4 and 1 / 2 of the frequency of the normal clock cycle, respectively. Alternatively, for example, 4 buffer clock cycles are used, and the corresponding frequencies from low to high are 1 / 8, 1 / 8, 1 / 4, and 1 / 2 of the frequency of the normal clock cycle, respectively. The frequency of the buffer clock cycle that jumps first is the lowest, and then gradually increases. The last buffer clock cycle is adjacent to the first normal clock cycle, and the frequency of the last buffer clock cycle is still less than the frequency of the first normal clock cycle.

[0048] In the embodiments of the present application, the sending data transmission state of the data transmission layer 12 of the sending end 10 needs to be monitored by the monitoring module 140 to monitor whether data transmission starts to exist between the sending end 10 and the receiving end 20, that is, whether the sending data transmission state of the data transmission layer 12 switches from the idle state to the start data transmission state. If it is monitored that the sending data transmission state switches from the idle state to the start data transmission state, data transmission between the sending end 10 and the receiving end 20 is started.

[0049] In the case where the sending end 10 or the receiving end 20 is a different device, the monitoring module 140 performs different functions.

[0050] In one embodiment, the sending end 10 is a master chip of a storage device, and the receiving end 20 is a storage grain of the storage device. The monitoring module 140 is specifically configured to: in the case where it is monitored that the level of the transmission bus of the data transmission layer jumps from a constant first level value to a second level value, it is determined that the sending data transmission state of the data transmission layer switches from the idle state to the start data transmission state, and the second level value is different from the first level value.

[0051] In this embodiment, the monitoring function can be implemented by the master chip, for example, by the control unit on the master chip. If it is monitored that the level on the transmission line 30 changes from keeping unchanged (a constant first level value) to suddenly starting to jump (a second level value), it is determined that the sending data transmission state of the data transmission layer 12 of the sending end 10 is switched from the idle state to the start transmission data state. For example, when the master chip receives a write request of an external device, it is monitored that the sending data transmission state of the data transmission layer 12 of the sending end 10 is switched from the idle state to the start transmission data state.

[0052] In another embodiment, the sending end 10 is a storage grain of a storage device, and the receiving end 20 is a master chip of the storage device. The monitoring module 140 is specifically configured to: in a case where a read command sent by the master chip in the plurality of buffer clock cycles is received, determine that the sending data transmission state of the data transmission layer is switched from the idle state to the start transmission data state, and the read command carries the number of valid data read from the storage grain and the number of redundant data corresponding to synchronous transmission of each buffer clock cycle.

[0053] In this embodiment, the storage grain as the sending end 10 does not have the function of actively monitoring the sending data transmission state. If the storage grain needs to be switched from the idle state to the start transmission data state, the master chip actively sends a read command to the storage grain when receiving a read request of an external device, so that the storage grain monitors the sending data transmission state of the data transmission layer based on the read command, switches from the idle state to the start transmission data state, and reads the internally stored data and sends it to the master chip.

[0054] As described above, the buffer module 160 is configured to send the redundant data corresponding to synchronous transmission to the receiving end in the buffer clock cycle before the valid data of the sending data transmission layer 12.

[0055] The buffer module 160 sends the redundant data corresponding to synchronous transmission to the receiving end 20 in the buffer clock cycle configured by the configuration module 120 before the sending end 10 sends the valid data of the sending data transmission layer 12 to the receiving end, that is, before the data read / written by the external device is sent, so as to avoid the case that the jump signal of the first one or more clocks sent by the sending end after the start jump is severely distorted and lost due to inter-code interference in transmission. The frequency of the buffer clock cycle is lower than the frequency of the normal clock cycle used for synchronous transmission of the valid data. By synchronously transmitting the redundant data in the buffer clock cycle with a frequency lower than the normal clock cycle before synchronously transmitting the valid data in the normal clock cycle, the level of the idle state can be first jumped from the idle state to the level of the buffer clock cycle, and then switched to the level of the normal clock cycle.

[0056] Therefore, compared with directly jumping from the level of the idle state to the level of the normal clock period, by introducing the buffer clock period with a frequency lower than that of the normal clock period, the level jump difference of adjacent clock periods can be reduced, so that the first clock signal transmitted by the sending end 10 can be prevented from being lost due to waveform distortion caused by inter-symbol interference.

[0057] Reference Figure 3 In the example of FIG. 1, the buffer module 160 inserts the waveforms of the additional two buffer clock periods before the sending end 10 transmits the valid data D0, D1, D2,... corresponding to the synchronous transmission of the normal clock period, and inserts the redundant data N0, N1, N2, N3 corresponding to the synchronous transmission on the data transmission line. The frequency at which the buffer clock period transmits the redundant data is different from the frequency at which the normal clock period transmits the valid data, and the frequency of the buffer clock period is lower than the frequency of the normal clock period.

[0058] For the embodiment in which the sending end 10 is a host chip of a storage device and the receiving end 20 is a storage grain of the storage device, the buffer module 160 is specifically configured to: based on the number of the redundant data configured by the configuration module, acquire the redundant data corresponding to the synchronous transmission of each buffer clock period, and transmit the redundant data to the storage grain based on the frequency of each buffer clock period configured by the configuration module 120; and after the transmission of the redundant data corresponding to the synchronous transmission of the plurality of buffer clock periods is completed, receive the valid data of the data transmission layer and transmit the valid data to the storage grain.

[0059] In the above embodiment, the number and frequency of the buffer clock periods transmitted by the host chip and the number of the redundant data corresponding to the synchronous transmission of each buffer clock period can be configured by the configuration module 120 of the host chip. In combination with Figure 2 , the configuration module 120 first configures the buffer clock period and the corresponding redundant data, and the monitoring module 140 monitors the data transmission state of the data transmission layer 12 of the sending end 10, which is the host chip. When it is monitored that the sending data transmission state of the data transmission layer 12 switches from the idle state to the data transmission state, the buffer module 160, before the host chip transmits the valid data of the data transmission layer 12, appends the configured buffer clock period and the corresponding redundant data between the data transmission layer 12 and the physical layer 14 of the host chip, and transmits the valid data to the storage grain of the receiving end 20 based on the frequency of each buffer clock period through the physical layer 14 and the transmission line 30.

[0060] After the transmission of the redundant data corresponding to the synchronous transmission of the plurality of configured buffer clock periods is completed, the valid data of the data transmission layer 12 is received and transmitted to the storage grain of the receiving end 20.

[0061] For the embodiment that the sending end 10 is a storage grain of a storage device, and the receiving end 20 is a master chip of a storage device, the configuration module 120 configures a plurality of buffer clock cycles and the number of redundant data corresponding to each buffer clock cycle based on the read command; the buffer module 160 obtains the redundant data corresponding to each buffer clock cycle based on the read command, and sends the redundant data to the master chip based on the frequency of each buffer clock cycle; and after the sending of the redundant data corresponding to each buffer clock cycle is completed, the effective data of the data transmission layer 12 is received and sent to the master chip.

[0062] In the above embodiment, the number and frequency of the buffer clock cycles sent by the storage grain, and the number of the redundant data corresponding to each buffer clock cycle, can be configured based on the read command sent by the master chip.

[0063] The master chip can send a read command to the storage grain based on the number and frequency of a plurality of buffer clock cycles configured in advance, and the read command carries the number of effective data required to be read from the storage grain and the number of redundant data corresponding to each buffer clock cycle. The storage grain can return the configured number of redundant data based on the read command sent by the master chip. The master chip sends a read command to the storage grain, and the storage grain returns the read command and the corresponding number of redundant data. The storage grain can receive the effective data of the data transmission layer 12 based on the number of effective data required by the read command, and send the effective data to the master chip of the receiving end 20 after the sending of the redundant data corresponding to the configured plurality of buffer clock cycles is completed.

[0064] The corresponding working principle can be referred to Figure 2 As the storage grain of the sending end 10, the monitoring module 140 first monitors the sending data transmission state of the data transmission layer 12 to switch from an idle state to a start transmitting data state based on the read command. Then, the configuration module 120 configures buffer clock cycles and corresponding redundant data based on the read command, and the buffer module 160, before the storage grain sends the effective data of the data transmission layer 12, according to the configuration, appends the corresponding configured buffer clock cycles and corresponding redundant data between the data transmission layer 12 and the physical layer 14 of the storage grain, and sends the buffer clock cycles and the corresponding redundant data to the master chip of the receiving end 20 through the physical layer 14 and the transmission line 30 based on the frequency of each buffer clock cycle.

[0065] For each of the above embodiments, the number of redundant data transmitted synchronously corresponding to the plurality of buffer clock cycles is determined by the main control chip, specifically including: determining the number of redundant data transmitted synchronously corresponding to the plurality of buffer clock cycles based on the number of the plurality of buffer clock cycles and the number of redundant data transmitted synchronously corresponding to each buffer clock cycle; or determining the number of redundant data transmitted synchronously corresponding to the plurality of buffer clock cycles based on the sum of the frequencies of the plurality of buffer clock cycles, the frequency of the normal clock cycle, and the number of valid data transmitted synchronously corresponding to one normal clock cycle.

[0066] In one embodiment, the number of redundant data transmitted synchronously across multiple buffer clock cycles is related to the number of buffer clock cycles and the number of redundant data transmitted synchronously within each buffer clock cycle. Combined with Figure 3 For example, if the sending end is configured with two buffer clock cycles, and the frequency of redundant data transmitted synchronously in each buffer clock cycle is the same as the frequency of the buffer clock cycle, then the number of redundant data transmitted synchronously in each buffer clock cycle is two, corresponding to... Figure 3 In the first buffered clock cycle, two redundant data points N0 and N1 are transmitted synchronously. In the subsequent second buffered clock cycle, two redundant data points N2 and N3 are transmitted synchronously. Each buffered clock cycle includes a high level and a low level, with each level transmitting one redundant data point synchronously.

[0067] In one embodiment, the amount of redundant data transmitted synchronously across multiple buffered clock cycles can be determined based on the total frequency of the multiple buffered clock cycles, the frequency of the normal clock cycle, and the amount of valid data transmitted synchronously across one normal clock cycle. Combined with... Figure 4 For example, the number of buffered clock cycles configured at the transmitting end is still 2, and the frequencies of these 2 buffered clock cycles are 1 / 4 and 1 / 3 of the frequency of the normal clock cycle, respectively. If one normal clock cycle corresponds to the synchronous transmission of 2 valid data, such as valid data D0 and D1, each normal clock cycle includes a high level and a low level, and each level synchronously transmits one valid data.

[0068] If the frequency of redundant data transmitted synchronously in the buffer clock cycle is the same as the frequency of the normal clock cycle, then the total number of redundant data transmitted synchronously in these two buffer clock cycles is 7, that is... Figure 4 Redundant data N0 to N6. Since redundant data is the data that the receiver 20 ultimately needs to remove, the quantity and frequency of redundant data can be determined in any way.

[0069] The buffer module 160 can acquire the redundant data and synchronously transmit the redundant data in each buffer clock cycle. In one embodiment, the buffer module 160 acquires the redundant data synchronously transmitted in each buffer clock cycle, including: determining the number of redundant data transmitted in a target buffer clock cycle; determining the data transmission width of each redundant data; and based on the number of redundant data and the corresponding data transmission width, acquiring a corresponding number of serial data as the redundant data synchronously transmitted in the target buffer clock cycle.

[0070] The target buffer clock cycle is any one of the plurality of buffer clock cycles. After determining the number of redundant data transmitted in the target buffer clock cycle, for example Figure 4 The first buffer clock cycle of the target buffer clock cycle transmits four redundant data N0-N3, and the data transmission width of each redundant data is determined. If the data transmission width of each redundant data is 8 bits, 32 serial data can be acquired as redundant data. The serial data used as redundant data is acquired in the plurality of buffer clock cycles, which can be calculated according to the frequency and number of each buffer clock cycle and saved in a predetermined storage unit. When insertion is needed, the corresponding number of serial data is acquired and transmitted according to the corresponding buffer clock cycle.

[0071] In the embodiment of the present application, the clock buffer device arranged between the data transmission layer and the physical layer of the sending end includes: a configuration module configured to configure buffer clock cycles and redundant data synchronously transmitted in the buffer clock cycles; a monitoring module configured to monitor whether the sending data transmission state of the data transmission layer is switched from an idle state to a start transmitting data state; and a buffer module configured to transmit the redundant data synchronously transmitted to the receiving end in the buffer clock cycles before transmitting the valid data of the data transmission layer. The frequency of the buffer clock cycle is lower than the frequency of the normal clock cycle for synchronously transmitting the valid data. Thus, the code interference in data transmission can only affect the burst jump signal of the first few buffer clock cycles, and the code interference can be avoided to cause the loss of valid data, so that the transmitted valid data can be completely transmitted to the receiving end, and the receiving end can accurately sample the valid data.

[0072] Optionally, the embodiment of the present application further provides a clock buffer device 200, which is combined with Figure 2 In the embodiment, the clock buffer device 200 is arranged between the physical layer 24 and the data transmission layer 22 of the receiving end 20, and the clock buffer device 200 is applied to the receiving end 20.

[0073] As Figure 2As shown, the clock buffering apparatus 200 comprises: a configuration module 220, configured to configure a first quantity of redundant data transmitted synchronously based on a buffering clock cycle; a monitoring module 240, configured to monitor whether a receiving data transmission state of the physical layer 24 switches from an idle state to a start transmitting data state; and a buffering module 260, configured to remove the first quantity of data received first from data transmitted by the sending end 10 and received by the physical layer 24.

[0074] In the embodiments of the present application, the receiving end 20 can be a storage grain of a storage device, and the sending end 10 can be a master chip of the storage device. Alternatively, the receiving end 20 can be a master chip of a storage device, and the sending end 10 can be a storage grain of the storage device.

[0075] The clock buffering apparatus 200 of the receiving end 20 provided by the embodiments of the present application can realize the processes of the clock buffering apparatus 200 of the receiving end 20 in the embodiments. Figures 1 to 4 The clock buffering apparatus 100 of the sending end 10 provided by the embodiments of the present application can realize the processes of the clock buffering apparatus 100 of the sending end 10 in the embodiments. To avoid repetition, details are not described herein. Figures 1 to 4 The clock buffering apparatus 100 of the sending end 10 provided by the embodiments of the present application can realize the processes of the clock buffering apparatus 100 of the sending end 10 in the embodiments. To avoid repetition, details are not described herein.

[0076] In one embodiment, when the master chip is the receiving end 20 and the storage grain is the sending end 10, based on the above description about the sending end in the embodiments, the configuration module 220 of the master chip is pre-configured with the buffering clock cycle of the redundant data transmitted by the storage grain and the quantity of the redundant data. Therefore, after the monitoring module 240 of the master chip determines that the receiving data transmission state of the physical layer 24 switches from the idle state to the start transmitting data state, the buffering module 260 of the master chip removes the redundant data transmitted synchronously based on the buffering clock cycle from the data transmitted by the storage grain and received by the physical layer 24 first.

[0077] After the storage grain transmits the redundant data to the master chip through the transmission line 30, the monitoring module 240 of the master chip can monitor that the receiving data transmission state of the physical layer 24 switches from the idle state to the start transmitting data state.

[0078] In one embodiment, the receiving end 20 is a storage grain of a storage device, and the sending end 10 is a master chip of the storage device. The configuration module 220 is specifically configured to: receive an initialization command transmitted by the master chip, the initialization command carrying a quantity of redundant data transmitted synchronously based on a buffering clock cycle; and configure the quantity of removed data based on the initialization command.

[0079] In the embodiment, as the storage particle of the receiving end 20, after the monitoring module 240 of the storage particle determines that the receiving data transmission state of the physical layer 24 is switched from the idle state to the start data transmission state, the buffering module 260 of the storage particle first eliminates the first received predetermined number of data of the physical layer 24 according to the number of the eliminated data, i.e., the number of the redundant data, which is pre-configured by the configuration module 220 of the storage particle, before the physical layer 24 transmits the received data to the data transmission layer 22. The master control chip can configure the number of the buffered data, i.e., the number of the redundant data, of the storage particle through an initialization command.

[0080] After the master control chip transmits the redundant data to the storage particle through the transmission line 30, the monitoring module 240 of the storage particle can monitor that the receiving data transmission state of the physical layer 24 is switched from the idle state to the start data transmission state.

[0081] In combination with Figure 3 , after the receiving end 20 receives the data, the buffering module 260 can eliminate the corresponding number of the redundant data N0-N3 which is synchronously transmitted in the buffering clock cycle of the dashed line part according to the configuration. Alternatively, in combination with Figure 4 , after the receiving end 20 receives the data, the buffering module 260 can eliminate the corresponding number of the redundant data which is synchronously transmitted in the buffering clock cycle of the dashed line part according to the configuration. For Figure 4 , the sending end 10 transmits 7 redundant data on the corresponding data line in the two buffering clock cycles of the dashed line part, but since there are only 4 edges, i.e., two rising edges and two falling edges in the two buffering clock cycles, the receiving end 20 can only perceive the redundant data corresponding to the 4 edges, and thus the receiving end 20 samples 4 valid redundant data in the corresponding buffering clock cycle and eliminates the 4 valid redundant data by the buffering module 260. Correspondingly, the configuration module 220 configures the first number according to the number of the synchronously transmitted redundant data which can actually be sampled by the receiving end 20 in the corresponding buffering clock cycle.

[0082] In the embodiment, the clock buffering device arranged between the physical layer and the data transmission layer of the receiving end comprises: a configuration module, configured to configure a first number based on the number of the redundant data which is synchronously transmitted in a buffering clock cycle; a monitoring module, configured to monitor that the receiving data transmission state of the physical layer is switched from the idle state to the start data transmission state; and a buffering module, configured to eliminate the first number of the data which is first received in the data transmitted by the sending end and received by the physical layer, so that the loss of the valid data caused by the inter-symbol interference in the data transmission can be avoided, and the complete valid data can be accurately sampled.

[0083] Optionally, as shown in Figure 5 , the first embodiment of the present application further provides a clock buffering method applied to a sending end, and the method comprises:

[0084] Step 102, configure a buffer clock period and redundant data corresponding to synchronous transmission in the buffer clock period;

[0085] Step 104, monitor whether the sending data transmission state of the data transmission layer switches from an idle state to a start transmitting data state;

[0086] Step 106, before sending valid data of the data transmission layer, send redundant data corresponding to synchronous transmission in the buffer clock period to a receiving end; wherein the frequency of the buffer clock period is lower than the frequency of a normal clock period for synchronously transmitting the valid data.

[0087] The clock buffering method provided by the embodiments of the present application can achieve Figures 1 to 4 The embodiments of the clock buffering device 100 applied to the sending end 10 achieve various processes, and thus details are not repeated here.

[0088] Optionally, as Figure 6 shown, the second embodiment of the present application further provides a clock buffering method applied to a receiving end, and the method comprises:

[0089] Step 202, configure a first quantity based on the quantity of redundant data corresponding to synchronous transmission in a buffer clock period;

[0090] Step 204, monitor whether the receiving data transmission state of the physical layer switches from an idle state to a start transmitting data state;

[0091] Step 206, among the data of the sending end received by the physical layer, eliminate the first quantity of data received first.

[0092] The clock buffering method provided by the embodiments of the present application can achieve Figures 1 to 4 The embodiments of the clock buffering device 200 applied to the receiving end 20 achieve various processes, and thus details are not repeated here.

[0093] Optionally, as Figure 2 shown, the embodiments of the present application further provide a data transmission system comprising a sending end 10 and a receiving end 20, wherein the sending end 10, when monitoring that the sending data transmission state of the data transmission layer of the sending end switches from an idle state to a start transmitting data state, sends redundant data corresponding to synchronous transmission in a configured buffer clock period to the receiving end before sending valid data of the data transmission layer; wherein the frequency of the buffer clock period is lower than the frequency of a normal clock period for synchronously transmitting the valid data.

[0094] The receiving end 20, when monitoring that the receiving data transmission state of the physical layer of the receiving end switches from the idle state to the start transmission data state, eliminates the first received data of the number of redundant data of the buffer clock cycle synchronization transmission in the data of the sending end received by the physical layer.

[0095] Optionally, as shown in Figure 7 The embodiment of the application further provides a clock buffering device 2000, which comprises a processor 2400 and a memory 2200, and the memory 2200 stores a program or instructions which can be run on the processor 2400, and when the program or instructions are executed by the processor 2400, the steps of the clock buffering method embodiment are realized, and the same technical effects are achieved. To avoid repetition, details are not described herein.

[0096] The embodiment of the application further provides a readable storage medium, which stores a program or instructions, and when the program or instructions are executed by a processor, the steps of any one of the clock buffering method embodiments are realized, and the same technical effects are achieved. To avoid repetition, details are not described herein. The readable storage medium comprises a computer readable storage medium, such as a read-only memory (ROM), a random access memory (RAM), a magnetic disc or an optical disc.

[0097] The embodiment of the application further provides a computer program product, which comprises a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute the steps of any one of the clock buffering method embodiments, and the same technical effects are achieved. To avoid repetition, details are not described herein.

[0098] It should be noted that, in this document, the term "comprising" or "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or further include elements inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0099] Those skilled in the art can clearly understand the above-mentioned embodiment method can be realized by means of software and the necessary general hardware platform, of course, also can be through hardware, but many cases the former is the better embodiment. Based on such understanding, the technical solutions of the present application essentially or say the part of the prior art contribution can be embodied in the form of software products, the computer software product is stored in a storage medium (such as ROM / RAM, disk, optical disc), including a number of instructions to make a terminal (may be a mobile phone, computer, server, air conditioner, or network equipment, etc.) executes the method described in various embodiments of the present application.

[0100] The embodiments of the present application are described above in conjunction with the drawings, but the present application is not limited to the above-mentioned specific embodiments, the above-mentioned specific embodiments are only illustrative, but not limited, those skilled in the art can make many forms without departing from the purpose of the present application and the scope of the claims under the inspiration of the present application, all belong to the protection of the present application.

Claims

1. A clock buffer apparatus, characterized by, Applied to a sending end, the device is arranged between a data transmission layer and a physical layer of the sending end, and the device comprises: A configuration module, configured to configure a buffer clock period and redundant data corresponding to synchronous transmission in the buffer clock period; A monitoring module, configured to monitor whether a sending data transmission state of the data transmission layer is switched from an idle state to a data transmission starting state; A buffer module, configured to send the redundant data corresponding to synchronous transmission to a receiving end in the buffer clock period before sending valid data of the data transmission layer; wherein a frequency of the buffer clock period is lower than a frequency of a normal clock period for synchronously transmitting the valid data.

2. The apparatus of claim 1, wherein, The configuration module is specifically configured to: configure a number of the buffer clock periods as multiple; and configure the multiple buffer clock periods with the same frequency which is lower than the frequency of the normal clock period, or configure the multiple buffer clock periods with the frequency gradually increasing from low to high, and a highest frequency of the multiple buffer clock periods is lower than the frequency of the normal clock period.

3. The apparatus of claim 2, wherein, The sending end is a master chip of a storage device, and the receiving end is a storage grain of the storage device, The monitoring module is specifically configured to: in a case that a level of a transmission line of the data transmission layer is jumped from a first constant level value to a second level value, determine that the sending data transmission state of the data transmission layer is switched from the idle state to the data transmission starting state, and the second level value is different from the first level value.

4. The apparatus of claim 3, wherein, The buffer module is specifically configured to: based on a number of the redundant data configured by the configuration module, acquire the redundant data corresponding to synchronous transmission in each buffer clock period, and send the redundant data to the storage grain based on the frequency of each buffer clock period configured by the configuration module; after the redundant data corresponding to synchronous transmission in the multiple buffer clock periods is sent, receive the valid data of the data transmission layer and send the valid data to the storage grain.

5. The apparatus of claim 2, wherein, The sending end is a storage grain of a storage device, and the receiving end is a master chip of the storage device, The monitoring module is specifically configured to: in a case that a read command sent by the master chip in the multiple buffer clock periods is received, determine that the sending data transmission state of the data transmission layer is switched from the idle state to the data transmission starting state, and the read command carries a number of valid data read from the storage grain and a number of the redundant data corresponding to synchronous transmission in each buffer clock period.

6. The device of claim 5, wherein: the configuration module configures multiple buffer clock periods and the number of the redundant data corresponding to synchronous transmission in each buffer clock period based on the read command; the buffer module acquires the redundant data corresponding to synchronous transmission in each buffer clock period, and sends the redundant data to the master chip based on the frequency of each buffer clock period; and after the redundant data corresponding to synchronous transmission in the multiple buffer clock periods is sent, receives the valid data of the data transmission layer and sends the valid data to the master chip.

7. The apparatus of claim 4 or 6, wherein, The number of the redundant data corresponding to synchronous transmission in the multiple buffer clock periods is determined by the master chip, and specifically comprises: determining the number of the redundant data corresponding to the synchronous transmission of the plurality of buffering clock cycles based on the number of the plurality of buffering clock cycles and the number of the redundant data corresponding to the synchronous transmission of each buffering clock cycle; or determining the number of the redundant data corresponding to the synchronous transmission of the plurality of buffering clock cycles based on the total frequency of the plurality of buffering clock cycles, the frequency of the normal clock cycle and the number of the effective data corresponding to the synchronous transmission of one normal clock cycle.

8. The apparatus of claim 4 or 6, wherein, the buffering module acquires the redundant data corresponding to the synchronous transmission of each buffering clock cycle, including: determining the number of the redundant data sent by the target buffering clock cycle; determining the data transmission width of each redundant data; acquiring a corresponding number of serial data as the redundant data corresponding to the synchronous transmission of the target buffering clock cycle based on the number of the redundant data and the corresponding data transmission width.

9. A clock buffer apparatus, characterized by comprising: application to the receiving end, the device is arranged between the physical layer and the data transmission layer of the receiving end, and the device includes: The configuration module is configured to configure the number of redundant data based on buffering clock cycle synchronous transmission as a first number; wherein the sending end sends the redundant data before sending the effective data, and the frequency of the buffering clock cycle is lower than the frequency of the normal clock cycle for synchronous transmission of the effective data; The monitoring module is configured to monitor whether the receiving data transmission state of the physical layer is switched from an idle state to a start transmission data state; The buffering module is configured to eliminate the first number of data received first from the data of the sending end received by the physical layer.

10. The apparatus of claim 9, wherein, The receiving end is a storage grain of a storage device, and the sending end is a master chip of the storage device, The configuration module is specifically configured to: receive an initialization command sent by the master chip, the initialization command carrying the number of redundant data based on buffering clock cycle synchronous transmission; configure the first number based on the initialization command.

11. A clock buffering method, characterized by, application to the sending end, the method includes: configuring a buffering clock cycle and redundant data corresponding to the synchronous transmission of the buffering clock cycle; monitoring whether the sending data transmission state of the data transmission layer of the sending end is switched from an idle state to a start transmission data state; sending the redundant data corresponding to the synchronous transmission to the receiving end in the buffering clock cycle before sending the effective data of the data transmission layer; wherein the frequency of the buffering clock cycle is lower than the frequency of the normal clock cycle for synchronous transmission of the effective data.

12. A clock buffering method, characterized by, application to the receiving end, the method includes: configuring the number of redundant data based on buffering clock cycle synchronous transmission as a first number; wherein the sending end sends the redundant data before sending the effective data, and the frequency of the buffering clock cycle is lower than the frequency of the normal clock cycle for synchronous transmission of the effective data; monitoring whether the receiving data transmission state of the physical layer of the receiving end is switched from an idle state to a start transmission data state; eliminating the first number of data received first from the data of the sending end received by the physical layer.

13. A data transmission system, characterized by including the sending end and the receiving end, The sending end sends the redundant data corresponding to the synchronous transmission to the receiving end in the configured buffer clock period before sending the valid data of the data transmission layer when monitoring that the sending data transmission state of the data transmission layer of the sending end switches from the idle state to the start transmission data state; wherein the frequency of the buffer clock period is lower than the frequency of the normal clock period of the synchronous transmission of the valid data; The receiving end eliminates the data of the number of the redundant data of the buffer clock period synchronous transmission which is firstly received in the data of the sending end received by the physical layer when monitoring that the receiving data transmission state of the physical layer of the receiving end switches from the idle state to the start transmission data state.

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